PAE2248 System-on-Chip Design

UI-SoC Design Issues

L8: Physical Design and Deliverable

Models

Presented By
Dr. V. Vaithianathan
Associate Professor, ECE Dept
 Lesson Plan
Sl. No. of
Lecture
No Hours
L1 Architecture of the SoC 1
L2 Design Issues of SoC 1

Hardware-Software Codesign - Codesign Flow &

L3 2
Codesign Tools

L4 Core Libraries, EDA tools, Web Pointers 1

L5 SoC Design Flow 1
L6 General Guidelines for Design Reuse 1
L7 On Chip Buses – Clock Distribution 1
L8 Physical Design and Deliverable Models 1
 Lecture 8
• Physical Design
• Deliverable Models
 Session Objectives
• To understand basic of Physical Design
• To learn about Deliverable Models
 Session Outcomes
• At the end of this lecture, the students will
be able to know about
– Physical Design
– Deliverable Models
 Physical Design
• Several physical design issues are extremely
important from the reuse point of view.
• In the development of hard cores, physical design is a
key item for the success of the core.
• Although soft and firm cores are not delivered in
layout form, consideration of their physical design
issues is still necessary.
 Physical Design
• Floor Plan
• Floor planning should start early in the design cycle.
• It helps in estimating the size and in determining if area,
timing, performance, and cost goals can be satisfied.
• The initial floor plan also helps in determining the functional
interfaces among different cores as well as clock distribution
at the chip level.
• When a SoC combines hard and soft cores, the fixed-aspect
ratio of the hard core can impose placement and routing
constraints on the rest of the design.
• Therefore, a low-effort SoC-level floor planning should be
done in the early design process.
 Physical Design
• Synthesis
• The overall synthesis process should also be planned early in
the design phase and should include specific goals for area,
timing, and power.
• Present-day synthesis tools do not handle very large design
all at once. Hence, hierarchically incremental synthesis
should be done.
• For this, whole design should be partitioned into blocks small
enough to be used by EDA tools.
• However, in this process each block should be floor-planned
as a single unit to maintain the original wire load model.
• Chip-level synthesis then consists of connecting various
blocks and resizing the output drive buffers to meet the
actual wire load and fan-out constraints.
• Hence, each block at this level should appear as two modules
(in hierarchy), one enclosing the other, similar to a wrapper.
 Physical Design
• Synthesis
• The outer module contains output buffers, and it can be
incrementally compiled by the synthesis tool, whereas the
inner module that contains functional logic of the core is not
to be changed (“don’t touch”) by the tool.
• This type of synthesis wrapper ensures that the gate-level
netlist satisfies area, speed, and power constraints.
 Physical Design
• Timing
• Static timing analysis should be done before layout on floor-
planned blocks.
• The final timing verification should be done on postlayout
blocks.
• During timing analysis careful attention should be paid to
black boxing, setup/hold time checks, false path elimination,
glitch/hazard detection, loop removal, margin analysis,
min/max analysis, multipath analysis, and clock skew
analysis.
• This timing analysis should be repeated over the entire range
of PVT (process, voltage, and temperature) specifications.
• Like the synthesis wrapper, a timing wrapper should be
generated for each block.
• This timing wrapper provides a virtual timing representation
of the gate-level netlist to other modules in the hierarchy.
 Physical Design
• Inputs/Outputs
• The definition of core I/Os is extremely important for design
reuse.
• The configuration of each core I/O, whether it is a clock input
or a test I/O, should be clearly specified.
• These specifications should include type of I/Os
(input/output/bidirect signal, clock, Vdd/Gnd, test-related
I/O, as well as dummy I/Os), timing specifications for bidirect
enable signals, limits on output loading (fan-out and wire
load), range of signal slew rate for all inputs, and noise
margin degradation with respect to capacitive load for
outputs.
• Placement of I/Os during the core design phase is also
important because their placement impacts core placement in
SoC.
 Physical Design
• Inputs/Outputs
• As a rule of thumb, all power/ground pins of the cores
should be placed on one side so that when a core is placed
on one side of the chip, these pins become chip-level
power/ground pins.
• This rule is a little tricky for signal I/Os.
• However, placing signal I/Os at two sides of the core
(compared to distributing along all four sides) is beneficial in
most cases.
 Physical Design
• Validation and Test
• Design validation and test are critical for successful design
reuse.
• Validation
• Test methodologies and manufacturing test
 Deliverable Models
• The reuse of design is pretty much dependent on the
quality of deliverable models.
• These models include
• a behavioral or instruction set architecture (ISA) model,
• a bus functional model for system-level verification,
• a fully functional model for timing and cycle-based logic
simulation/emulation,
• physical design models consisting of floor planning, timing,
and area.
• Table 1 summarizes the need and usage for each
model.
• One of the key concerns in present-day technology is
the piracy of IP or core designs.
 Deliverable Models
Table 1 Summary of Core Models and Their Usage
 Deliverable Models
• With unprotected models, it is easy to reverse
engineer the design, develop an improved design,
learn the trade secrets, and pirate the whole design.
• To restrict piracy and reverse engineering, many of
the models are delivered in encrypted form.
• The most used method is to create a top-level module
and instantiate the core model inside it.
• Thus, the top-level module behaves as a wrapper
(shell) and hides the whole netlist, floor planning, and
timing of the core.
• This wrapper uses a compiled version of the
simulation model rather than the source code and,
hence, it also provides security against reverse
engineering of the simulation model.
 Review Questions
1. State and explain various physical design issues in
SoC.
2. What are deliverable models? State their
importance.
3. Summarize Core Models and Their Usage.
 Session Summary
• In this lecture, we have discussed about
– Physical Design
– Deliverable Models
 Text Books & References
1. Rochit Rajsuman, “System-on-a-chip: Design and
Test”, Advantest America R & D Centre, 2000.
2. Hubert Kaeslin, “Digital Integrated Circuit Design: From
VLSI Architectures to CMOS Fabrication”, Cambridge
University Press, 2008.
3. B. Al Hashimi, “System on chip-Next generation
electronics”, The IET, 2006.
4. P Mishra and N Dutt, “Processor Description Languages”,
Morgan Kaufmann, 2008.
5. Michael J. Flynn and Wayne Luk, “Computer System
Design: System-on-Chip”, Wiley, 2011.
Thank You