VLSI Testing

Lecture 25
18-322 Fall 2003

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Announcement
Homework 9 is due next Thursday (11/20)

Exam II is on Tuesday (11/18) in class

Review Session:
When: Next Monday (11/17) afternoon, 4pm – 6pm
Where: B131, HH

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Outline
Defects and Faults
Reasons for IC malfunctioning

Fault Modeling
Types of faults (Stuck-At, bridge, Stuck Open)
Automatic Test Pattern Generation
Path Delay Fault

Design for Testability

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Why Testing?
Manufacturing is imperfect
No. of good chips on wafer
Y=
Total no. of chips

Yield (Y) depends on technology, chip area and layout

⌧Ydecreases as the area of chip is increased
⌧Defect density (D)
• Modern technologies yield a value of 1-5 defects/cm2
Yield starts out low (~10%) moves up (95%)

High quality expectation

The earlier you detect a fault, the cheaper it is to fix
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Reasons for IC Malfunction - Contamination,
Defects and Faults
Contamination / Instabilities - Process induced
impurities and random fluctuations of process
conditions

Defects - Permanent deformation in IC layer which may

but does not have to result in fault

Faults - Functional misbehaviors i.e. IC malfunctions

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Reasons for IC Malfunction -
Defects and Faults
B C 13 VDD
VDD
N1
M9
Metal
M11
M14
Poly
M12
N13
M13
C OUT Contact

M10
13 N+
A A
C N B
M25
P
N2
M27 M28 N13
GND
M26
M23 M24
GND

B C 13
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Reasons for IC Malfunction -
Defects and Faults

V DD
M10
B M9 M13
N3
A N1 M12
M14
M11
C OUT
M25 M26
N13 N2 M28
N4
M24
M27
M23
GND
C

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Reasons for IC Malfunction -
Defects and Faults
B C VDD
13
VDD
N1
M9 M9
M11 Metal
M14
Poly
M12 N13
M13
C OUT Contact

M10
13 N+
A
A
B
C N

M25 N2
P N13
M27 M28 GND
M26
M23 M24
GND

B C 13
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Reasons for IC Malfunction -
Defects and Faults

C out

Defect
A B C
M10
no yes
M13 VDD
B M9 0 0 0 0 0
0 0 1 0 0
A M11 M12 M14
0 1 0 0 0
C
OUT 0 1 1 1 1
M25 M26 M28 1 0 0 0 0
1 0 1 1 0
M24
M23
M27
GND 1 1 0 1 0
GND
1 1 1 1 1
C
N1 - N13 short

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Outline
Defects and Faults
Reasons for IC malfunctioning

Fault Modeling
Types of faults (Stuck-At, bridge, Stuck Open)
Automatic Test Pattern Generation
Path Delay Fault

Design for Testability

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Test Complexity

In Out
n+m
Exhaustive test 2
“n”
Combinational
Logic

Circuit with n = 25 and m = 50

1µsec/test
QQ DD Exhaustive test time is over 1 billion years!
QQ DD
(Registers make life harder!)
clock

Registers
“m”
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Testing Strategies
Functional Test: (go/no go)
Does the part work?
Do this fast & cheap

Diagnostic Test:
What in the chip is broken?

Parametric Test:
What is:
⌧ max clock frequency
⌧ min supply voltage
⌧ max operating temp
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Test Implementation
Runs Test Vectors/Programs on Device Under Test
(DUT)
Goal: Find a SMALL set of test vectors that has a BIG fault
coverage

Testers
Clock rate in the range of GHz
Resolutions measured in psec
Large very fast memory
Cost 1 - 5 million dollars
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Fault Models

• Modeling physical faults is complex

• Need models that simplify the behavior of faults

a f
b h
x
c g
d
e

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Stuck-At Fault

a f
b h S-A-0
Stuck-at-0 x
c g
d
e

a f
b h
S-A-1 x
Stuck-at-1 c g
d
e

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Bridge & Stuck Open

a f
b h
x
c g
d Bridging
fault
e

a f
b h
x
c g
d Open
fault
e

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Automatic Test Pattern Generation (ATPG)
Given a logic circuit:
Generate test program to cover all SA faults

The D-Algorithm
The D-Calculus
⌧Problem: Reconvergent Fanouts

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D-Algorithm
Step 1: Choose a fault to “insert”
Select from a fault dictionary

Step 2: Activate (excite) the fault

Drive the faulty node to the opposite value of the fault
Example: for SA-1, drive the node to 0

Step 3: Sensitize a path to an output

Propagate the fault so that it can be observed at the output
pin
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Path Sensitization
Goals: Determine input pattern that makes a fault
controllable (triggers the fault, and makes its impact
visible at the output nodes)

sa0
1
Fault enabling 1 1
Out
1
1
1 0
Fault propagation
0

Techniques Used: D-algorithm, Podem

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D-Algorithm

a f
b h
x
c g D = 1/0
d
e
value in value in
good ckt faulty ckt
a f
b h S-A-0
x
c g D = 0/1
d
e

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D-Algorithm

Five value logic simulation

X =NOT(A) X = AB
B
A X A 0 1 X D D
0 1 0 0 0 0 0 0
1 0 1 0 1 X D D
X X X 0 X X X X
D D D 0 D X D 0
D D D 0 D X 0 D

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D-Algorithm

Five value logic simulation

X=A+B
B
A 0 1 X D D
0 0 1 X D D
1 1 1 1 1 1
X X 1 X X X
D D 1 X D 1
D D 1 X 1 D

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D-Algorithm

1/0 = D
1
a f 1
b 1 h S-A-0
D x
1 1
c g
d 0

e 1

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D-Algorithm

1/0 = D
1
a f 1
b 1 h
x
1 1
c g
d 0
1

Conflict !
Need backtracks

Reconvergent Fanout
x
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Fault Simulation

Random Number Generator,

Test Program Genetic Algorithm, etc.

Fault Free Circuit w/

Circuit One Fault

Compare

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Path Delay Fault
A defect can affect the speed of a path in the circuit

Let’s see a Path Delay Fault example

slow slow
a c
T0 e slow T1+∆T
b
11 d
11

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Path Delay Fault

Path c-g2-g4-g5-x

a 00
g1
b g4
g5 x
c
00 g2
d
00
11 g3
e

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Outline
Defects and Faults
Reasons for IC malfunctioning

Fault Modeling
Types of faults (Stuck-At, bridge, Stuck Open)
Automatic Test Pattern Generation
Path Delay Fault

Design for Testability

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Scan-based Test

Modified to support two

operation modes
ScanIn ScanOut

Out
In Combinational Combinational
Register

Register
Logic Logic
A B

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Scan Based Methods

R Logic R Logic R Logic R

Level Sensitive Scan Design (LSSD) - IBM

Test Mode: OFF Test Mode: ON

R L R L R R R

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Boundary Scan (JTAG: IEEE 1149.1b)
Printed-circuit board
Logic Packaged IC

normal interconnect
Scan-in si so

Scan-out
scan path

Bonding Pad

Board testing becomes as problematic as chip testing

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Built-In Self-Testing (BIST)

(Sub)-Circuit

Stimulus Generator Under Response Analyzer

Test

Test Controller

Rapidly becoming more important with increasing

chip-complexity and larger modules

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Linear-Feedback Shift Register (LFSR)

R R R

S0 S1 S2
1 0 0
0 1 0
1 0 1
1 1 0
1 1 1
0 1 1
0 0 1
1 0 0

Pseudo-Random Pattern Generator

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