Basic MOS transistors

IT
M
• E-MOSFET – does not conduct when Vgs =0 ( as

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there is no channel established between

E
C
source and drain)

rE
fo
• D-MOSFET remains in the conducting mode

t.p
when Vgs=0( due to presence of channel).

s
as
• For switching off D-MOSFET a negative voltage
s
an
has to be applied to the gate.
et
ch
ch
et
an
s
as
st.p
fo
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C
E
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MOSFET as switch
Circuit Symbols of MOSFET

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E
C
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t.p
s
as
s
an
et
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N-MOS Device formation

IT
M
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• Substrate used is of P-type with
moderate doping level

E
• Source and drain are formed with

C
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suitable masks by diffusing n-type
impurities

fo
• For connections metal is

t.p
deposited on S&D

s
as
• Oxide layer is formed between

s
S&D
an
• Polysilicon is deposited on top of
et

insulation layer and metal contact

ch

is made for gate

 For D-MOSFET

IT
M
• Channel is established in manufacturing

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E
process itself by implanting suitable impurities

C
rE
in between S&D.

fo
t.p
s
as
s
an
et
ch
ch
et
an
s
as
st.p
fo
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C
E
E-MOSFET

SJ
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IT
 E-MOSFET Action

IT
M
• When Vgs Vt then (Vgs –Vt) is called as the

SJ
E
‘effective gate voltage’

C
rE
• Because there will be no current flow when

fo
t.p
Vgs Vt

s
as
s
• Based on value of Vds , there are three
an
et

conditions
ch
 a)

ch
et
an
s
as
st.p
fo
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C
E
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M
IT
 b)

ch
et
an
s
as
st.p
fo
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C
E
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M
IT
 c)

ch
et
an
s
as
st.p
fo
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C
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M
IT
• In saturated region as Vds is positive the depletion region expands
near the drain (channel established between S&D) and transistor

IT
will be in conducting state

M
SJ
• In saturation region as Vds Vgs-Vt the depletion region’s expansion
 part of the channel get piched off.

E
is much larger due to which

C
rE
• How ever transistor remains in the conducting state due to diffusion

fo
t.p
current.

s
as
• But the current remains constant the onwards thus the channel
s
exhibits high resistance and the transistor behaves as a constant
an
current source
et
ch
ch
et
an
s
as
st.p
fo
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C
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ch
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as
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 Module 1- fabrication
nMOS FABRICATION
1. A thin wafer cut from a cylindrical

IT
crystal of silicon is used as substrate.

M
• Typical dimentions: 75-150mm dia

SJ
0.4 mm thickness.

E
• Substrate is doped with boron to make it p-type

C
• Impurity concentration is 10 15 /cm3 to 2516/ cm3

rE
• Resistivity of 25Ω-cm to 2Ω-cm.

fo
st.p
as
s 2. An oxide layer is grown all over the surface called
an
‘THICK-OXIDE’ or ‘FIELD-OXIDE’.
et

• Thickness - 1µm, acts as protective layer to

ch

• the wafer for the subsequent processes

 3. Surface is covered with an even distribution of PR
• Two types in PR – positive and negetive
• +ve PR – the exposed areas are removed

IT
• -ve PR- the unexposed areas are removed

M
• Here –ve PR is used

SJ
E
C
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fo
4. PR layer is then exposed to UV light

t.p
by means of the required mask.
• The exposed areas are polymerized and they get

s
as
hardened

s
an
et
ch

5. The unexposed areas are then etched away

Along with the underlying Sio2
 6. Remaining PR is removed and,
• A thin layer of 0.1µm thickness is grown
over the entire chip surface.
• This layer is called as ‘THINOX’ or ‘GATE-OXIDE’
• heavily doped polysilicon is deposited over this

IT
‘THINOX’ to define gate areas.

M
• Polisilicon deposition is done by CVD –chemical

SJ
vapour depostion.

E
C
rE
7. The ‘thinox’ is removed by further

fo
processes of PR coating, masking and etching

t.p
• The S and D are formed by diffusion of n-type

s
impurities, by passing PH3 over the surface.

as
As the polisi & oxide layer acts as masks, the
process is called self aligned.
s
an
et

8. Thick oxide is grown all over gain and then

ch

the previous processes(PR coating, masking and

etching) are carried out, to expose the selected
Areas where contact cuts are to be made for S,G &D.
 9. Finally a metal of 1µm thickness is
deposited all over the surface
• It is again processed to form the required

IT
Interconnections.

M
SJ
E
C
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Note :

fo
• For D-mosfet fabrication ‘ION IMPLEMENTATION’ process is performed

t.p
in which the n-type impurities are made to pass through the ‘thinox’.

s
as
• ‘self-alligning’ reduces the no of masks that are goin to be utilized.
s
an
et

• After metallization a final process called ‘ OVER GLASSING ‘ is performed to

ch

prevent exposure of chip to the external atmosphere. This layer is called

‘pevention layer.
ch
et
an
s
as
st.p
fo
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C
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IT
 CMOS FABRICATION

IT
M
When we need to fabricate both nMOS and pMOS transistors on

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the same substrate we need to follow different processes. The

E
C
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three different processes are, P-well process ,N-well process and

fo
Twin tub process.

t.p
s
as
s
an
et
ch
 P-WELL PROCESS
• The p-well process starts with a n type substrate. The n type substrate can be used
to implement the pMOS transistor,

IT
• But to implement the nMOS transistor we need to provide a pwell, hence we have

M
SJ
provided he place for both n and pMOS transistor on the same n-type substrate.

E
C
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fo
st.p
as
s
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et
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ch
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as
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 Mask sequence.
Mask 1: Defines the areas in which the deep p-well diffusion takes place.

Mask 2: It defines the thin oxide region (where the thick oxide is to be removed or stripped

IT
and thin oxide grown)

M
SJ
Mask 3: It‘s used to pattern the polysilicon layer which is deposited after thin oxide. Mask

E
C
Mask 4: A p+ mask (anded with mask 2) to define areas where p-diffusion is to take place.

rE
fo
Mask 5: We are using the –ve form of mask 4 (p+ mask) It defines where n-diffusion is to

t.p
takeplace.

s
as
Mask 6: Contact cuts are defined using this mask.
s
an
Mask 7: The metal layer pattern is defined by this mask.
et
ch

Mask 8: An overall passivation (over glass) is now applied and it also defines openings for
accessing pads.
The cross section below shows the CMOS pwell inverter.

IT
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E
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st.p
as
s
an
et
ch

CMOS inverter (P-WELL)

 1.8.2 The n-WELL PROCESS

Advantages of n-well CMOS Device

IT
M
 Lower substrate bias effects on transistor V t.

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 Lower parasitic capacitances associated with S & D regions.

E
C
N-well fabrication steps

rE
fo
1. The first mask defines n –well region

t.p
2. Followed by low dose PH implant driven by a high temperature diffusion

s
as
step to form n-wells

s
3. Define devices and diffusion paths
an
4. Grow field oxide
et

5. Deposit and pattern the polysilicon and carryout the diffusion

ch

6. Make contact cuts

7. metallization
 1. n+ mask and its complement may
be used to define the n- and

IT
M
p+ diffusion regions respectively

SJ
E
2. These same masks also include the

C
VDD and Vss contacts.(respectively)

rE
fo
3. Alternatively, we could have used

t.p
a p+ mask and its Complemet

s
as
since the n+ and p+ masks are

s
generally complementary
an
et
ch
Inverter circuit fabricated by the n-well process

IT
M
SJ
E
C
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fo
s t.p
as
s
an
et
ch
ch
et
an
s
as
st.p
fo
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C
1.8 TWIN-TUB process

E
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IT
 Twin-tub process allows separate optimization of the n- and p-transistors. Due
to individual control of doping. Due to which gain and vt can be individually adjusted.

IT
 Start with a substrate of high resistivity n-type material and then create both

M
n-well and p-well regions.

SJ
 Through this process it is possible to preserve the performance of

E
n-transistors without compromising the p-transistors.

C
rE
 Epi layer utilized here to prevent short circuit of the device
 Epi layer is lightly doped hence has higher resistivity is used to prevent latch-up

fo
s t.p
Latch-up

as
During fabrication of n-well and p-well it gives rise to formation of parasitic
s
bipolar transistors these gives rise to ‘LATCH-UP’ in which
an
Vdd and Vss is shortened.
et
ch
 • nmos is a lower temperature process

IT
Compared to cmos.

M
SJ
• Hence nmos has advantage of ease fabrication

E
C
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•And also it has higher density per unit area

fo
t.p
•In contrast , cmos has the advantages of lower

s
as
power consumption an ease of circuit design.

s
an
et
ch
 BICMOS TECHNOLOGY

• nmos technology has limited source and sinking capabilities.

IT
M
• to design so called super-buffers using MOS transistors alone, such arrangements do not

SJ
always compare well with the capabilities of bipolar transistors.

E
C
rE
•Bipolar transistors also provide higher gain and have generally better noise and high

fo
frequency characteristics than MOS transistors and it may be seen Figure that BiCMOS

t.p
gates could be an effective way of speeding up VLSI circuits.

s
as
s
an
et
ch
ch
et
an
s
as
st.p
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C
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IT
• The production of NPN bipolar transistors with good performance characteristics can be
achieved, for example,

IT
M
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• by extending the standard n-well CMOS processing to include further masks to add two
additional layers, the n + subcollector and p + base layers.

E
C
rE
•The npn transistor is formed in an n-well and the additional P+ base region is located in

fo
the well to form the p-base region of the transistor.

s t.p
• The second additional layer-the buried n+ subcollector (BCCD) is added to reduce the n-

as
well (collector) resistance and thus improve the quality of the bipolar transistor.
s
an
• The simplified general arrangement of such a bipolar npn transistor may be appreciated
et
ch

with regard to Figure 1.16.

 IT
For clarity, the layers have not been drawn

M
transparent but, BCCD underlies the entire

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area the layers have not been drawn

E
transparent but BCCD underlies the entire

C
area and the p+ base underlies all within its

rE
boundary. and the p+ base underlies all

fo
within its boundary.

st.p
as
s
Arrangement of BiCMOS NPN
an
transistor (Orbit 2 µm CMOS).
et
ch
Ideal v-I characteristics
• A voltage on the gate terminal
induces a charge in the channel

IT
that exists b/w S and D

M
• The charge then move from S

SJ
to D under influence of electric

E
C
field generated by voltage VDS

rE
applied b/w D&S.

fo
• The charge induced is

t.p
dependent on VGS. The current

s
as
IDS is dependent on both VGS &
s
VDS
an
• the relationship between
et

these parameters can be

ch

developed
• Expression for transit time

IT
M
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E
C
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fo
t.p
s
as
s
an
et
ch
ch
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an
s
as
st.p
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C
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IT
ch
et
an
s
as
st.p
fo
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C
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M
IT
Non saturated region
 ch
et
an
s

14
as
st.p
fo
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C
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IT
15

16
 VDS = VD – Vs =10-9.9=0.1V
VGS = 0v
Given Vt = -1v

IT
ß=1mA/v2

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drain current ID is given by

E
C
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fo
st.p
as
s
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 Saturation region
• Device enter into

IT
saturation when Vds 17

M
= VGS –Vt

SJ
• At this point the IR 18

E
drop in channel

C
rE
equals to the
effective gate 19

fo
t.p
voltage.

s
• Current through the

as
channel remailns
s
20
constant for any
an
further increment
et
ch

in VDS.
• The expression for IDS hold for both, the depletion and enhancement mode devices
• Vt for nmos-D device is –ve and denoted by Vtd

IT
• Typical characteristics for nMOS

M
SJ
Transistors are shown in fig.
• pMOS transistor characteristics

E
C
are similar With reversal of polarity

rE
fo
summary

s t.p
as
s
an
et
ch
 Non ideal I-V characteristics
• In all three regions we derived some non theoretical effects were neglected.
• Practically in nonlinear saturation region, the saturation current increases less than quadraticaly

IT
with increasing VGS because of velocity saturation and mobility degradation.

M
SJ
1.VELOCITY SATURATION

E
C
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fo
s t.p
as
s
an
et
ch
• If the transistor is completely velocity saturated i.e V=Vsat ,saturation current
expression is modified to IDS = C0 W(Vgs –Vt)Vsat
• here the Id is quadraticaly dependent on voltage without velocity saturation and

IT
linearly dependent when fully velocity saturated.

M
SJ
• This behaviour is approximated by -power model where is called velocity
modulation index.

E
C
• where ID can be moderated as

rE
fo
s t.p
as
s
an
et
ch
2. MOBILITY DEGRADATION
• Due to large VGS, vertical electrical fields cause the carriers to scatter and
reduces the carrier mobility-µ - this phenomenon is called mobility

IT
M
degradation. Modeled by µeff.

SJ
3. CHANNEL LENGTH MODULLATION

E
Perfect current source- transistor in saturation – ideally IDS independent of V DS

C
•

rE
Reverse biased p-n junction between D&B forms depletion region with width
Ld that increases with reverse bias vg. The depletion region effectively shortens

fo
t.p
the channel length

s
Leff =L-Ld

as
• s
Shorter channel length results in higher I ds increases with Vds.
an
• (vgs  vt )2
et

Id in saturation is given by
Id   (1  Vds )
ch

2
• λ = channel length modulation factor. And inversely proportional to channel
length.
4. BODY EFFECT – EFFECT OF SUBSTRATE BIAS

• Consider 2 nmos transistors connected in

IT
vertically series.

M
• And Source to substrate vg Vsb is observed vertically

SJ
Upward .

E
• Vsb1 =0, Vsb2 ≠0 variation of Vsb leads to variation in Vt’s

C
• Vsb2 >Vsb1 therefore Vt2 >Vt1

rE
• This variation of threshold voltage is referred as

fo
‘BODY EFFECT’

t.p
• Body effect is because of variation in depletion

s
• region under oxide

as
s
an
et
ch
Mos models – small signal model

IT
M
SJ
E
C
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fo
t.p
s
as
s
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ch
et
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s
as
st.p
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IT
 MOS LAYERS
MOS design is aimed at turning a specification into masks for processing silicon to meet the
specification.

IT
M
SJ
We have seen that MOS circuits are formed on four basic layers-n-diffusion, p-diffusion,
polysilicon, and metal, which are isolated from one another by thick or thin

E
C
(thinox) silicon dioxide insulating layer.

rE
fo
The thin oxide (thinox) mask region include

s t.p
as
n-diffusion , p-diffusion, and transistor channels . Polysilicon and thinox regions interact so

s
that a transistor is formed where they cross one another.
an
et

In some processes, there may be a

ch

second metal layer and also, in some processes, a second polysilicon layer. Layers may
deliberatelY joined together where contacts are formed .
Encodings for a simple metal nMOS process

IT
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st.p
as
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ch
et
an
s
as
st.p
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IT
ch
et
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s
as
st.p
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IT
COLOR PLATE 1(a) Encodings for a simple single metal nMOS process.

IT
M
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C
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fo
st.p
as
s
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et
ch
ch
et
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s
as
st.p
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IT
COLOR PLATE 1 (b) Color encodings for a double metal CMOS p-well process. The same well encoding and demarcation
line is used for an n-well process. For a p-well process, the n features are in the well. For an n-well process, the p features
are in the well.

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fo
s t.p
as
s
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et
ch
Additional encodings for a double metal double poly. BiCMOS n-well process

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M
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C
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fo
st.p
as
s
an
et
ch
Stick diagrams and simple symbolic encoding

IT
M
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C
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fo
st.p
as
s
an
et
ch
ch
et
an
s
as
st.p
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ch
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as
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IT
Transistors
A transistor exists where a polysilicon stick crosses either an N diffusion stick
(NMOS transistor) or a P diffusion stick (PMOS transistor).

IT
M
Stick Diagram Colour Code

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st.p
as
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ch
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an
s
as
st.p
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ch
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as
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IT
 DESIGN RULES AND LAYOUT

•Design Rules objective: to allow a ready translation of circuit design concepts, usually in stick

IT
diagram or symbolic form, into actual geometry in silicon.

M
SJ
•The design rules are the effective interface between the circuit/system designer and the

E
C
fabrication engineer.

rE
fo
•Circuit designers in general want tighter, smaller layouts for improved performance and

t.p
decreased silicon area.

s
as
• The process engineer wants design rules that result in a controllable and reproducible
s
an
process.
et
ch
 Lambda(ƛ)-based Design Rules

IT
M
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fo
st.p
as
s
an
et
ch
ƛ - Design rules can be conveniently set out in diagrammatic form as - for the widths and
separation of conducting paths.

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st.p
as
s
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et
ch
ƛ - Design Rules for extensions and separations associated with transistor layouts

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s t.p
as
s
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ch
The design rules associated with contacts between layers are set out in Figures (a) and (b) and it will be noted that connection can be made
between two or, in the case of nMOS designs, three layers.

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s t.p
as
s
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et
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 Contact Cuts
• There are three possible approaches When making contacts between polysilicon and diffusion in nMOS circuits.

1. Poly. to metal then metal to diff.,

IT
2. Buried contact poly. to diff – Polysilicon comes over diffusion.

M
3. Butting contact (poly. to diff. using metal) – Polysilicon and diffusion are joined by metal.

SJ
• Buried contact is the most widely used, giving economy in space and a reliable contact.

E
C
rE
• In CMOS designs, poly. to diff. contacts are almost always made via metal. When making connections between metal and
either of the other two layers ,

fo
t.p
• The process is quite simple. The 2ƛ. x 2ƛ. contact cut indicates an area in which the oxide is to be removed down to the

s
underlying polysilicon or diffusion surface. When deposition of the metal layer takes place. the metal is deposited through

as
the contact cut areas onto the underlying area so that contact is made between the layers.

s
an
et
ch
When connecting diffusion to polysilicon using the butting contact approach, the process is rather more
complex
• In effect, a 2ƛ. x 2ƛ. contact cut is made
down to each of the layers to be joined.

IT
M
• The layers are butted together in such a

SJ
way that these two contact cuts become

E
contiguous.

C
rE
• Since the polysilicon and diffusion

fo
outlines overlap and thin oxide under

t.p
polysilicon acts as a mask in the diffusion

s
as
process , the polysilicon and diffusion
layers are also butted together.
s
an
• The contact between the two butting
et
ch

layers is then made by a metal overlay as

shown in the figure.

Contacts polysilicon to diffusion (nMOS only in the main text).

ch
et
an
s
as
st.p
fo
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C
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M
IT
 The buried contact approach shown in Figures is
simpler,
• The contact cut (broken line) in this case indicating
where the thin oxide is to be removed to reveal the

IT
surface of the silicon wafer before polysilicon is

M
deposited.

SJ
E
•Thus, the polysilicon is deposited directly on the

C
underlying crystalline wafer. When diffusion takes

rE
place, impurities will diffuse into the polysilicon as

fo
well as into the diffusion region within the contact

t.p
area.

s
as
•Thus a satisfactory connection between polysilicon
s and diffusion is ensured .
an
et

•Buried contacts can be smaller in area than their

ch

butting contact counterparts and, since they use no

metal layer, they are subject to fewer design rule
restrictions in a layout
 Double Metal MOS Process Rules
•Here the oxide below the metal is deposited by means of APCVD(atmospheric pressure
CVD)

IT
M
SJ
•For the removal of selected areas of the oxide, plasma etching is employed

E
C
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fo
st.p
as
s
an
Routing tips :
et

1.use metal -1 for local distribution of power and signal lines

ch

2.use metal -2 for global distribution of power buses (vdd, Vss , CLK)
3. Lay the two metal layers such that the conductors are mutually orthogonal, wherever
possible.
 Lambda based Design Rules for CMOS
•The CMOS fabrication process is much more complicated and elaborate design rules exist for the same.
A simplified abstract of the actual processing steps which are used to produce the chip are shown.

IT
M
• Otherwise the documentation of actual

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set of design rules used in practice would

E
run into several pages of diagrams and

C
description. Two such micron-based rule

rE
sets are presented here.

fo
t.p
• Actually these rules are an extension of the

s
lambda-based rules set out in Fig. 2.3.1 to

as
Fig. 2.3.5 for nMOS designs with the butting
s and buried contacts excluded.
an
et
ch
 • The additional rules for CMOS
are given in Fig. and are,
pertaining to those features

IT
M
unique to thep-well CMOS, like p+

SJ
mark and p-well and some special
'substrate' contacts.

E
C
rE
• We note that the rules given for

fo
the p-transistors and p-contacts

t.p
are also easily translatable to an

s
as
n-well process

s
an
et
ch
ch
et
an
s
as
st.p
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ch
et
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as
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ch
et
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s
as
st.p
fo
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C
E
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M
IT
ch
et
an
s
as
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A set of construction rules can be derived to construct logic functions.
• NMOS devices connected in series corresponds to an AND function.

IT
• NMOS transistors connected in parallel represent an OR function

M
• A conducting path exists between the output and input terminal if at least one of the

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inputs is high.

E
C
Using similar arguments, construction rules for

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PMOS networks can be formulated. A series connection of PMOS conducts if both

fo
inputs are low, representing a NOR function (A.B = A+B), while PMOS transistors in

t.p
parallel implement a NAND (A+B = A·B)

s
as
Using De Morgan’s theorems ((A + B) = A·B and A·B = A + B), it can be shown that the
s
pull-up and pull-down networks of a complementary CMOS structure are dual networks.
an
This means that a parallel connection of transistors in the pull-up network corresponds
et

to a series connection of the corresponding devices in the pull-down network, and vice
ch

versa.
 Basic Circuit Concepts

• The MOS devices are fabricated by superimposing various layers of conducting,

IT
insulating and transforming materials.

M
• In a conventional silicon gate process an active device requires a gate forming

SJ
region and source-drain forming region, which consists of diffusion, polysilicon and

E
metal layers separated by insulating layers.

C
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• There are resistance and capacitance associated with each layer. These
resistances and capacitances are fundamental components in estimating

fo
t.p
performance of overall system.

s
• System performance is evaluated in terms of delays and power dissipation. The

as
issues to be considered are listed here –
s
1. Resistance, capacitance and inductance. 2. Delay computation. 3. Calculation of
an
conductor size for clock and power. 4. Power dissipation/consumption. 5. Charge
et
ch

sharing mechanism. 6. Design margin. 7. Reliability. 8. Effects of scaling.

 Sheet Resistance ( RS )
•The sheet resistance Rs is a measure of resistance of a thin
film that have a uniform thickness.

IT
M
•The sheet resistance is used to evaluate the outcome of

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semiconductor doping, metal deposition and resistive paste

E
printing.

C
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• A uniform slab of conducting material is shown in Fig. with

fo
dimensions. Resistance of sheet along its length AB is given

t.p
by

s
as
•. Where A = cross-section area
Note that Rs is completely independent of the area of the
s square.
an
Thus
et
ch

Now, consider the case in which L = W, that is, a where

square of resistive material, then Rs = ohm per square or sheet resistance
 Thus

ch
et
an
s
as
st.p
fo
rE
C
E
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IT
 IT
M
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E
C
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fo
st.p
as
Area Capacitances of Layerss
an
• The conducting layers are separated from the substrate and each other by
et
ch

insulating (dielectric) layers. Therefore parallel plate capacitive effects are

present.
For any layer, the area capacitances can be computed by knowing the dielectric (silicon
dioxide) thickness.
by formula,

IT
M
SJ
E
C
rE
fo
st.p
as
s
an
et
ch
ch
et
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s
as
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IT
Standard unit of capacitance

IT
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E
C
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fo
st.p
as
s
an
et
ch
Some Area Capacitance Calculations
The calculation of capacitance
values may now be undertaken by

IT
establishing the ratio between the area of

M
interest and the area of standard (feature That is, the defined area in metal has a capacitance to

SJ
size square) gate (2λx2λ for λ-based rules) substrate 1.125 times that of a feature size square gate area.

E
and multiplying this ratio by the

C
appropriate relative C value from Table, The

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product will give the required capacitance

fo
in Cg units. units.

t.p
First, we must calculate the area relative to that of a

s
as
standard gate. By,

s
an
Capacitance Calculation for Multilayer
et
ch

In multilayer substrate total capacitance calculation is sum

of metal capacitance (Cm), polysilicon capacitance (Cp ) and
gate capacitance (Cg).
Total capacitance CT= Cm + Cp + Cg
 3.

Therefore,

IT
M
SJ
E
C
Consider the metal area (less the contact region where the

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metal is connected to polysilicon and shielded from the
substrate)

fo
s t.p
as
1.

s
an
2.
et
ch
 THE DELAY UNIT τ
For defining standard units for basic circuit
parameters, a standard delay unit τ is defined.

IT
Consider one standard (feature size square) gate area

M
capacitance being charged through one feature size

SJ
square of n-channel resistance (that is through
substrate resistance RS of nMOS pass transistor

E
channel). As in fig we have,

C
However, circuit wiring and parasitic capacitances have an

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effect on propagation of signals which must be catered

fo
for.

t.p
Hence, in practice, the figure for τ is often increased by a

s
factor of two or three and then used for design. Then

as
value of τ for 5 4m circuit comes out to τ = 0.2 to 0.3 n sec for
assessing likely worst case delays.
s
an
et

The τ so obtained is quite close to the transit time

ch

τ sd calculated above.
As the gate capacitance Cg charges from 0 V to 63 % The safe figures recommended for use for
of Vdd Vds also varies. Referring Fig. we take an design in different technologies are as follows :
appropriate value for Vds as the average value of (a) 5 µm MOS technology, τ = 0.3 nsec
3 volts. Then, for the 5µm process,

IT
(b) 2 µm MOS technology, τ = 0.2 nsec

M
(c) 1.2 µm MOS technology, τ = 0.1 nsec

SJ
E
C
rE
Which is not much different from the theoretical time

fo
constant τ calculated above as 0.1 nsec. Thus the

t.p
transit time and time constant (as defined for the delay

s
unit τ ) are synonymous and can be interchangeably

as
used.
s
an
The 'stray' capacitances are usually catered for by
et

doubling (or more) the theoretical values

ch

calculated. Thus τ serves as a fundamental time

unit and all timings in a system can be assessed
interms of τ .
INVERTER DELAYS - Delay Associated with Single and Cascaded Inverters
• Thus there is an asymmetry in and Rp.u and Rp.d
Hence delay associated with inverter will depend on
whether it is being turned-off or on. However, conditions are

IT
different with a pair of cascaded inverters.

M
SJ
• As shown in Fig. , here the delay over the inverter pair is
constant irrespective of the type of logic level transition of

E
C
the input of the first inverter. This is because transition

rE
at input of second inverter is opposite to that at the input
of first inverter.

fo
t.p
• Note that the delay in turning on is τ while the

s
corresponding delay in turning-off is 4 τ. Taking τ = 0.3

as
nsec and making no extra provisions for wiring

s
capacitances, the overall delay comes out to τ + 4 τ = 5 τ.
an
Interms of p.u. and p.d. impedances, the delay through a
et

pair of identical nMOS inverters can be generalized as

ch

Thus, the inverter pair delay for inverters having 4: 1 ratio is 5 τ

• As per this formula, also, delay for pair of inverters
having 4 : 1 ratio comes to 5 τ.

IT
• In case of CMOS inverters, the ratio rule relevant in

M
nMOS no longer applies. However there is a natural

SJ
asymmetry in the Rs between the pull-up and pull-

E
down devices which has to be catered for.

C
rE
• This is because the pull-up device is a p-type and

fo
the pull-down device is of n-type. Estimation of delay

t.p
associated with a pair of minimum size (both n and p-
transistors) lambda-based inverters.

s
as
• is illustrated in Fig.Since the input to a CMOS inverter is
s
connected to the gate of both the transistor the gate Note:
an
capacitance is double that of the comparable nMOS The asymmetry of resistance values can be eliminated by
et

inverter. Fig. also indicates the consideration made increasing the width of the p-device channel by a factor of
ch

for the asymmetric channel resistances. two or three, but it should be noted that the gate input
capacitance of the p-transistor is also increased by the same
factor.
 A More Formal Estimation of CMOS Inverter Delay

• The delay associated with the CMOS inverter can be

more precisely estimated by splitting the output

IT
transitions into fall-time τf and rise-time τr corresponding

M
to the charging and discharging of the capacitive load CL.

SJ
• These two phenomenon can be independently

E
C
estimated more precisely to arrive at the overall delay.

rE
Estimation of Rise-time.

fo
Estimation of Rise-time

s t.p
• The pull-up p-device drives the capacitive load and

as
can be assumed to be in saturation for the entire

s
charging period of the load capacitor CL.
an
This current being constant the output voltage is given
et

• The equivalent circuit for this condition is shown in by

ch

Fig. Now the saturation current for the p-transistor is

given by
 Estimation of Fall-time
• Fall-time is associated with the discharging of LC
through the pull-down n-type device. The equivalent
circuit model for fall-time estimation is shown in Fig.

IT
which shown a constant discharge current.

M
SJ
E
• the rise time τr corresponds to time taken by

C
Vout to reach Vdd (apprx.) so that

rE
fo
s t.p
as
s
an
Making similar assumptions we may write for fall-time:
et
ch
 • From τf and τr , we can deduce • The analytical models used above for the
estimation of rise and fall-times are
adequate enough to get optimistic

IT
results. However, they do not consider

M
SJ
certain factors affecting the rise and fall-
times such as,

E
• However µn and µp are not same, But µn =

C
2.5µp and ßn = 2.5 ßp. so that the rise-time is

rE
slower by a factor of 2.5 when using minimum

fo
size devices for both 'n' and 'p’.

t.p
s
as
• we would need to make WP = 2.5Wn and for
minimum size lambda-based geometries this
s
an
would result in the inverter having an input
et

capacitance of 1 Cg (n-device) + 2.50 Cg(p-

ch

device) = 3.50 Cg in total In order to achieve

symmetrical operation using minimum
channel length.
 Driving Large Capacitive Loads

• For driving large capacitive loads, inverters This situation can be improved by using N

IT
should present low pull-down and pull-up cascaded inverters, each one of which is

M
resistances. This, in turn means that MOS devices larger than the stage that it follows by a

SJ
must be designed with low L : W ratios to have width factor f as shown in Fig. where
low resistance values for Zp.u and Zp.d

E
nMOS inverters are taken as an example.

C
• For this, channels must be made very wide to

rE
reduce resistance value which in consequence

fo
makes the inverter occupy a larger area.

t.p
• Another limitation on L is that it cannot be

s
reduced below the minimum feature size

as
which makes L : W ratio large.

s
• Hence the gate region area L x W becomes
an
significant and a comparatively large
et

capacitance is presented at the input.

ch

• This in turn increases time required for

transitions of voltages at the input.
 Super Buffers
• A "super buffer" is a specially designed nMOS drive
circuit that eliminates the basic asymmetry in

IT
ratio-type logic, which is unable to provide equal

M
SJ
amounts of currents during the rising and falling
transitions because of differing Rpu and Rpd .

E
• An inverting type nMOS super buffer is shown

C
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in Fig, This is how the circuit works.

fo
• A positive going (0 to 1) transition at input Vi n turns

t.p
on the inverter formed by T1 and T2. With a small delay,

s
as
the gate of T3 is pulled down to 0 volts. Thus device T3 is approximating VDD. This gate voltage is twice the
cut-off. average voltage that would appear if the gate was
•
s
However, since gate of T4 is connected to Vi n, it is connected to the source as in the conventional nMOS
an
turned ON and the output is pulled down very fast. inverter.
et

For the opposite transition of Vin (1 to 0), Vin drops to 0 • Now, as I ds vgs doubling the effective Vgs increases
ch

volts. the current and thereby reduces the delay in

• The gate of device T3 is allowed to rise to Vdd very charging at the load capacitance of the output. The
quickly. Simultaneously the low Vin turns-off T4 very fast. result is more symmetrical transitions.
This makes T3 to conduct with its gate voltage
 A non-inverting nMOS super buffer circuit is
given in Fig.

IT
M
SJ
• To Gain an idea of the effectiveness of super

E
buffer designs, we note that the structures

C
fabricated in 5 µm technology are capable of driving

rE
capacitance of 2 pF i with a rise-time of 5 nsec.

fo
st.p
as
s
an
et
ch
 MODULE 3 : Scaling of MOS Circuits
OBJECTIVES

IT
M
Microelectronic technology may be characterized in terms of several indicators, or

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figures of merit. Commonly, the following are used:
SCALING MODELS AND SCALING FACTORS

E
• Minimum feature size

C
• Number of gates on one chip

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• Power dissipation

fo
• Maximum operational ·frequency

t.p
• Die size

s
as
• Production cost.

s
an
et
ch
ch
et
an
s
as
st.p
fo
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C
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IT
SCALING FACTORS FOR DEVICE PARAMETERS

IT
M
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E
C
rE
fo
t.p
s
as
s
an
et
ch
ch
et
an
s
as
st.p
fo
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C
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IT
ch
et
an
s
as
st.p
fo
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C
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IT
ch
et
an
s
as
st.p
fo
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C
E
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ch
et
an
s
as
st.p
fo
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C
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M
IT
 Summary of Scaling Effects

IT
M
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E
C
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fo
st.p
as
s
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et
ch
ch
et
an
s
as
st.p
fo
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C
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M
IT
 Subsystem Design Processes - General Considerations

• The aim of any practicing VLSI designer is to produce • Improved repeatability - Fewer processes

IT
'better' products with expectations like, are required to be controlled if the complete

M
system or most of it is realized on a single chip.

SJ
• Higher reliability - By having reduced
interconnections, by high levels of system integration • Better performance

E
- This can be gauged in

C
(more regularity). Interconnections happen to be a terms of speed power product.

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weak spot in any system.
• Any scope for reducing

fo
• Lower power dissipation

t.p
- lower weight and
design/development period - By adopting
lower volume in comparison with most other

s
suitable design procedures and using design aids,

as
approaches to a given system.
this can be tried, especially for more complex

s
systems.
• Lesser cost
an
In comparison with other approaches meeting the
et

same requirement. Cost is generally closely related to

ch

quantity being produced. However by adopting co-

operative ventures such as multiproduct wafer (MPW)
and multiproject chip (MPC), cost can be substantially
reduced.
 An Illustration of Design Processes
Documentation of a design may be
• Design processes are basically undertaken
done by different representations
bearing in mind the following rules.

IT
at different stages such as :

M
SJ
1. The process is strictly a top-down approach.
• Stick diagrams
2. The top-down approach dictates that any

E
• Logic symbols

C
complex function is possible to be divided into
• Conventional circuit symbols

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less complex subfunctions - bottom level
• A combination of stick diagrams

fo
defining the leaf-cells or basic structures.

t.p
and circuit symbols as found
3. Layout should ensure that components

s
convenient at the particular

as
interacting more frequently -physically in close
stage
proximity otherwise long, high bandwidth
s • Mask layouts
an
interconnects may cause severe problems.
• Floor plans
et

5. Design should be aimed at minimum

• Block diagrams showing the
ch

interaction between subparts in order to

architecture.
achieve independence of design.
 4-Bit Arithmetic Processor

IT
M
SJ
Communication strategy for data path

E
C
• These two data ports can be conveniently combined

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into a single bidirectional port assuming that storage
facilities exist in the data path. Control signals dictate

fo
the control over functions to be performed by this

t.p
port.

s
as
s
an
et
ch
 Sequence:
1. 1st operand from registers to ALU. Operand is stored
there.
2. 2nd operand from register to ALU and added.

IT
3. Result is passed through shifter and stored in the

M
register.

SJ
4. Hence it requires 3 clock cycles.

E
C
rE
fo
st.p
as
s
an
Sequence:
et

1. Two operands (A & B) are sent from register(s) to ALU &

ch

are operated upon, results in S from ALU.

2. Result is passed through the shifter & stored in
registers.
3. It requires 2 clk pulses.
 IT
M
SJ
E
C
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Sequence:

fo
1.Two operands (A & B) are sent from registers,

t.p
operated upon, and shifted result (S) returned to another

s
register, all in same clock period.

as
2. It does not require any clock pulse

s
an
In pursuing this design exercise, it was decided to
implement the structure with a 2 - bus architecture. A
et

tentative floor plan of the proposed design which

ch

includes some form of interface to the parent system data

bus is shown following fig.
 Design of a 4-bit Shifter

• Any general purpose n-bit shifter should be able to

IT
shift incoming data by up to n-1 place in a right-

M
shift or left-shift direction.

SJ
• all shifts should be on an end-around basis, so that any
bit shifted out at one end of a data word will be shifted

E
in at the other end of the word, then the problem

C
of right shift or left shift is greatly eased.

rE
• It can be analyzed that for a 4-bit word, that a 1-bit shift

fo
right is equivalent to a 3-bit shift left and a 2-bit shift

t.p
right is equivalent to a 2-bit shift left etc. Hence, the

s
design of either shift right or left can be done. Here the

as
design is of shift right by 0, 1, 2, or 3 places.

s
an
The shifter must have:
et

• input from a four line parallel data bus

ch

• four output lines for the shifted data

• means of transferring input data to output lines with any
shift from 0 to 3 bits.
 In this arrangement ,any input can be connected to any or
all the outputs. Furthermore, 16 control signals (swoo -
sw15), one for each transistor switch, must be provided

IT
to drive the crossbar switch, and such complexity is highly

M
undesirable.

SJ
An adaptation of this arrangement - we couple the

E
C
switch gates together in groups of four and also form

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four separate groups corresponding to shifts of zero,
one, two and three bits.

fo
Which results in a BARREL SHIFTER

s t.p
as
s
an
et
ch
ch
et
an
s
as
st.p
fo
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C
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IT
ch
et
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s
as
st.p
fo
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C
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IT
 DESIGN OF AN ALU SUBSYSTEM
• Now we undertake the design of the ALU on the next It will be seen that for any column k
subsystem of 4 bit data path shown below
there will be three inputs-the

IT
corresponding bits of the input numbers,

M
Ak and Bk, and the ' previous carry' -carry

SJ
in (Ck - 1). It will also be seen that there

E
are two outputs, the sum (Sk) and a new

C
carry (Ck).

rE
fo
t.p
•

s
The heart of the ALU is a 4-bit adder circuit

as
• A 4-bit adder must take sum of two 4-bit

s
numbers, and there is an assumption that all
an
4-bit quantities are presented in parallel form
et

and that the shifter circuit is designed to

ch

accept and shift a 4-bit parallel sum from

the ALU.
Standard adder equations assuming not a ‘look
ahead carry adder’.
These equations may be directly
implemented as And-Or functions or,

IT
M
most economically,

SJ
Sk and Hk can be directly implemented

E
with Exclusive-Or gates

C
rE
fo
s t.p
as
s
an
et
ch
ch
et
an
s
as
st.p
Adder Element

fo
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C
E
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IT
ch
et
an
s
as
st.p
fo
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C
E
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M
IT
ch
et
an
s
as
st.p
fo
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C
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M
IT
 Standard cells required to be designed for the adder
element

IT
M
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E
C
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fo
st.p
as
s
an
et
ch
ch
et
an
s
as
st.p
fo
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C
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IT
ch
et
an
s
as
st.p
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C
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IT
ch
et
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s
as
st.p
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C
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IT
Adder element bounding box
• First estimate the bounding box for the multiplexer area
of the adder. Each standard multiplexer cell (Figure 8.6)

IT
is 7λ x 11λ. and there are .16 such elements side by side

M
'horizontally' and four stacked 'vertically'.

SJ
• width for the metal to metal spacings required by

E
the clock bus passing through the center.

C
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•

fo
In the vertical direction we must allow spacings

t.p
for the interconnections between the tops of the

s
multiplexers

as
•
s
further lOA. for the connection out from Sk and C k
an
at the bottom.
et
ch
ch
et
an
s
as
st.p
fo
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C
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IT
Implementing ALU Functions with an Adder

IT
M
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E
C
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fo
st.p
as
s
an
et
ch
ch
et
an
s
as
st.p
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Adder Enhancement Techniques

IT
M
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E
C
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fo
st.p
as
s
an
et
ch
ch
et
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s
as
st.p
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IT
 Carry select adder

IT
M
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E
C
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fo
st.p
as
s
an
also referred to as a conditional sum adder-the adder is divided into blocks. Each block is
et

composed of two adders, one with a logical 0 carry in and the other with a logical 1 carry in.
ch

The sum and carry out generated are then selected by the actual carry in which comes from
the carry out output of the previous block as shown in Figure.
 Optimization of the carry select adder
consider an n-bit ripple carry adder. The
computation time T is given by, For ex..

IT
the n-bit adder is divided into M blocks, and that

M
each block contains P adder cells in series, and

SJ
considering the arrangement of Figure 8.17, we may
where k1 is the delay through one adder see that the completion time T for the overall carry

E
cell. If we now divide the adder into blocks,

C
output signal is composed of two parts:

rE
each with two parallel paths, then the
completion, time T becomes

fo
• the propagation delay through the first block.

t.p
• the propagation delay through the multiplexers.

s
so that,

as
where k2 is the time needed by the
s
multiplexer of the next block to select the
an
actual output carry.
et
ch
 Carry Skip(carry bypass) Adders
• Improves on the delay of ripple carry adder.

IT
• The improvement of worst case delay is achieved by using several carry skip adders to

M
form a block carry skip adder.

SJ
• It utilizes advantages of both generation(gk) and propagation(pk).

E
•

C
Working principle :

rE
1. The adder can be divided into several blocks,
for each block a special circuit is used to detect

fo
the condition , when A and B bits differ

t.p
in all bit positions in the block.

s
as
(i.e pi =1 for all ‘i’ in the block).

s
an
2. The output signal from such a circuit is called
Block propagation signal, if BP signal =1,
et
ch

then the carry signal entering the block

can bypass it and be transmitted through
a multiplexer to the next block.
 Optimization of the carry skip adder

1.Let k1 denote the time needed by the carry signal to propagate through the adder cell, and k2 the
time needed for a carry to skip over a block. Further, let us divide the n-bit carry skip adder into M

IT
blocks-each block containing P adder cells.

M
2. Since, as was the case for the ripple carry adder, the actual computing time depends on the

SJ
configuration of the input numbers, the completion time may well be small but may also reach the

E
worst case.

C
The total (worst case) propagation delay time T is given by

rE
where,

fo
s t.p
as
s
an
et
ch
 carry Look ahead adder

ch
et
an
s
as
st.p
fo
rE
C
E
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M
IT
Reg expressions
In particular the expression for carry,

IT
M
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E
C
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ch
et
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ch
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ch
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 Module 4 – Sub System Design
SOME ARCHITECTURAL ISSUES
In all design processes, a logical and systematic approach is essential. Guidelines may be set out as follows:

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 Switch logic is based on the 'pass
SWITCH LOGIC
transistor' or on transmission gates.
This approach is fast for small arrays
and takes no static current from the

IT
supply rails. Thus, power dissipation

M
SJ
of such arrays is small since current
only flows on switching.

E
C
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fo
•

t.p
The Pass transistor is used as a
switch in relaying the signals. The

s
as
path through each switch is
isolated from the signal activating
the switch.
s
an
• Switch logic arrangements using basic
et

OR and AND connections are shown in Fig.

ch

many such combinations of switches are possible

 Pass Transistors and Transmission Gates

IT
Switches or switch logic can be realized either using simple n or p pass

M
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transistors or from transmission gates.

E
C
The transmission gates are complementary switches made up of a p-

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pass and a n-pass transistor in parallel as shown in Fig.

fo
s t.p
Simple pass transistors may suffer from undesirable threshold voltage

as
effects which gives rise to loss of logic levels as indicated in Fig.
s
an
et
ch
ch
et
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s
as
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fo
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IT
• The transmission gate is free from any such degradation of logic levels although it occupies
more area and requires complementary signals to drive it. Also, the ’on’ resistance of
transmission gates is lower than that of the simple pass transistor switches.

IT
M
• There is one restriction which must be observed when using nMOS switch logic in the way

SJ
that no pass transistor gate input must be driven through one or more pass transistors.

E
C
• As shown here, the logic levels, logic levels propagated through pass transistors get

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degraded by threshold voltage effects. The signal out of the pass transistor T1 is not a full

fo
logic 1 but rather a voltage that is one transistor threshold below the true logic 1. Hence

t.p
this degraded voltage does not permit the output of T2 to reach an acceptable logic 1 level.

s
as
Gate (Restoring) Logic

s
• In the gate logic, the inverter is the simplest gate on which are
an
built logic circuits. With this, AND and OR gate arrangements are
et

possible with CMOS and NAND and NOR for other systems.
ch

Another use of inverters is to complement and restore logic levels

that may have passed through pass transistors and got degraded.
 Inverter
Inverters come in all the CMOS, nMOS and

IT
BiCMOS technologies and the most

M
commonly used inverter circuit diagrams

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along with the inverter symbol and the

E
corresponding stick and symbolic diagrams

C
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are shown in Fig

fo
t.p
Note that the channel length to width ratio

s
for each mos transistor and/or the nmos the

as
nmos inverter Zp.u /Zp.d is usually indicated as
shown. s
an
et
ch
 IT
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E
C
A particular pull-up to pull-down

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ratio can be achieved in several

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possible ways as shown in Fig

st.p
as
s
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An 8:1 nMOS inverter is considered
here and effect on power dissipation

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Pd, area occupied, resistance and

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capacitance values due to different

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approaches is clearly indicated.

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fo
st.p
as
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 Two-Input nMOS, CMOS and BICMOS nand Gates
The nMOS (and pseudo-nMOS) L: W ratios should be carefully noted since they must be chosen to
achieve the desired overall Zp.u / Zp.d ratio.

IT
M
In order to arrive at the required L: W ratios for an

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nMOS (or pseudo-nMOS) Nand gate with n inputs,
consider simple circuit model of the gate in the

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C
condition when all n pull-down transistors are

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conducting as in following fig.

fo
The critical factor here is that the output

t.p
voltage vout be near enough to ground

s
as
to turn off any following inverter-like stages,
that is
s
an
et

thus
ch

nMOS Nand ratio determination.

 where Zp.d applies for any one pull-down transistor. The boundary condition then is

IT
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from which the ratio for nMOS NAND gate is =

SJ
E
the ratio between Zp.u and the sum of all the pull-down Zp.d must be 4:1 (as for the nMOS

C
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inverter). This ratio must be adjusted appropriately.

fo
This ratio requirement and the other aspects pertaining to the nMOS NAND gate

t.p
geometry bring out two significant factors

s
as
s
1. nMOS Nand gate area requirements are considerably greater than nMOS inverter, since
an
not only must pull-down transistors be added in series to provide the desired number of
et

inputs, but, as inputs are added, so must there be a corresponding adjustment of the length
ch

of the pull-up transistor channel to maintain the required overall ratio.

2. nMOS Nand gate delays are also increased in direct proportion to the number of
inputs added. If each pull-down transistor is kept to minimum size (2λx 2λ), then
each will present at its input, but ..

IT
M
SJ
if there are n such inputs, then the length and resistance of the pull-up transistor must
be increased by a factor of n to keep the correct ratio.

E
C
Thus, delays associated with the nMOS Nand are

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fo
t.p
Where,

s
as
n is the number of inputs

s
τ inv is the corresponding nMOS inverter delay
an
The alternative approach of keeping Z p.u constant and widening the pull-down
et

channels has the same effect, since in this case Cg for each pull-down transistor will
ch

be increased to
nMOS, CMOS and BICMOS 2-input Nand gates

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t.p
s
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ch
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Two-Input nMOS, CMOS and BICMOS nor Gates

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(c) Stick diagrams (nMOS and CMOS) and symboliC form (BiCMOS)

s t.p
as
s
an
et
ch

(a)~(c) nMOS, CMOS and BiCMOS two-input Nor gate.

 • Arrangements for 2 input NOR gates in CMOS, nMOS and BiCMOS are shown in Fig. The
nMOS two-input NOR gate can be expanded for more number of inputs and wherever
possible, it is preferred to the NAND gate.

IT
• The CMOS NOR gate has a pull-up p-transistor-based structure for the logic 1 conditions

M
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and a complementary n-transistor arrangement to implement logic 0 at the output.

E
Due to this, the already higher resistance of the p-devices is further increased by the

C
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number of devices connected in series. This thus increases the asymmetry in rise and fall

fo
times on capacitive loads.

s t.p
as
s
an
• Risetime and fall-time asymmetry on capacitive loads is thus increased and there will also
et

be a shift in the transfer (Vin vs Vout) characteristic which will reduce noise immunity.
ch

• For these reasons, CMOS (complementary logic) Nor gates with more than two inputs
may require adjustment of the p- and/or n-transistor geometries (L: W ratios).
•As already mentioned, the nMOS NOR gate can be expanded to accommodate more
number of inputs.

IT
•Since there are two paths to ground from p.u for two input NOR gate. Hence the ratio

M
SJ
should be like providing any one path to give inverter like structure.

E
C
•Thus each 'leg' would have the same ratio as would be in an nMOS inverter. This applies

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for any number of inputs.

fo
t.p
• An advantage of the nMOS NOR gate is that the dimensions of the pull-up transistor are

s
as
unaffected number of inputs incorporated because of which the area occupied by the NOR

s
gate is quite reasonable making the NOR gate as fast as the corresponding inverter.
an
et
ch
 Comparison of CMOS and BiCMOS Logic

1. CMOS logic supports technology scaling i.e lower supply voltage and large number of

IT
M
transistors on chip. But technology scaling is not possible in bicmos.

SJ
2. BiCMOS inverters offers several advantages in applications like high current sinking and

E
C
sourcing compared to CMOS inverters.

rE
fo
3. BiCMOS cricuits are free from latchup problems (due to parasitics ---- +ve or –ve

t.p
spikes).

s
as
s
an
et
ch
 Pseudo-nMOS logic

• Clearly, if we replace the depletion mode pull-up transistor of the

standard nMOS circuits with a p-transistor with gate connected to

IT
Vss , we have a structure similar to the nMOS equivalent.

M
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• Structure In which(b) a pseudo-nMOS inverter is being driven by

E
C
another similar inverter, and we consider the conditions necessary

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to produce an output voltage of Vinv for an identical input voltage.

fo
t.p
• As for the nMOS analysis, we consider the conditions for which

s
as
Vinv = Vdd /2

s
• At this point the n-device is in saturation (i .e. 0 < Vgsn -Vtn < Vdsn)
an
et

• p-device is operating in the resistive region (i.e. 0 < Vdsp < Vgsp –V
ch

tp )
equating currents of n-transistor & the p-transistor, and by suitable rearrangement, we
get

IT
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E
C
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fo
t.p
with We obtain

s
as
s
an
et

A transfer characteristic, Vout vs Vin can be drawn and, as

ch

for the nMOS case, the characteristic will shift with

changes of Zp.u./Zp.d. ratio.
• the ratio obtained indicates that pseudo nMOS consumes lesser area when compared
to nMOS. And,

IT
• pseudo nMOS offers large resistance and thus it has about 60% lesser power consumption.

M
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•Due to large resistance in pull up network the delay get increases (about 70%) compare

E
to nMOS.

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fo
st.p
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 Dynamic CMOS logic

IT
The actual logic fig(a)is implemented in the

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inherently faster nMOS logic (the n-block)

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E
C
 for the non-time-critical
a p-transistor is used

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precharging of the output line 'Z' so that the output

fo
capacitance is charged to V DD during the OFF period of

t.p
the clock signal . During this same period the inputs

s
as
are applied to the n-block and,
s
an
the state of the logic is then evaluated during the on
et

period of the clock when the bottom n-transistor is

ch

turned ON.
 As we know and observed that single phase dynamic
logic structures cannot be cascaded

IT
However, this limitation can be overcome by

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utilization of MULTIPHASE CLOCKING for four

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phase clocking. As shown in which the actual signals

E
used are the derived clocks

C
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, and as illustrated in Figure.

fo
t.p
The basic circuit of Figure (a) is modified by the

s
inclusion of a transmission gate as in Figure (c), the

as
function of which is to sample the output during the
s'evaluate‘ period and to hold the output state while
an
the next stage logic evaluates.
et
ch

For this strategy to work, the next stage must operate

on overlapping but later clock signals
 A Parity Generator

A circuit is to be designed to indicate the

IT
parity of a binary number or word.

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st.p
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 A little reflection will readily reveal that the
requirements are:

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fo
A suitable arrangement for such a cell is given in stick

t.p
diagram form in Figure (a) (nMOS) and 6. 18(b) (CMOS)

s
as
The circuit implements the function.
s
an
et
ch
ch
et
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as
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 FPGA BASED SYSTEM

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A FPGA is a programmable logic device

C
which supports implementations of relatively

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large logic circuits. • The building blocks of

fo
FPGA are :

t.p
1. Logic cells (LCs) grouped into configurable

s
as
logic blocks (CLBs)

s
2. I/O blocks
an
3. Programmable interconnects.
et
ch
1. Logic Cells : Each logic block is an FPGA
typically has a smaller number of inputs and
outputs.

IT
• The most commonly used logic block is a

M
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lookup table (LUT), which contains storage
cells that are used to implement a small logic

E
function.

C
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• Each cell is capable of holding a single logic
value, either 0 or 1. The stored value is

fo
t.p
produced as the output of the storage cell.
• where the size is defined by the number of

s
as
inputs.

s
an
• Two Input LUT
et
ch

shows the structure of a small LUT. It has two

inputs, it has 2 inputs x1 and x2 and one o/p ‘f’
• It is capable of implementing any logic function of
two variables. Because a two-variable truth

IT
table has four rows, this LUT has four

M
storage cells. One cell corresponds to the

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output value in each row of the truth table.

E
• Similarly, for all valuations of x1 and x2,

C
• The input variables x 1 and x2 are used as the the logic value stored in the storage cell

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select inputs of three multiplexers, which corresponding to the entry in the truth

fo
depending on the valuation of X1 and X2, select table chosen by the particular valuation

t.p
the content of one of the four storage cells as the appears on the LUT output.

s
as
ouptut of the LUT.

• s
The arrangement of multiplexers in the LUT
an
correctly realizes the function f.
et

• When x1 = x 2 = 0, the output of the LUT is

ch

driven by the top storage cell, which

represents the entry in the truth table for x1 x2 =
00.
 Three Input LUT
It has eight storage cells because a three-variable
truth table has eight rows.

IT
M
Some FPGAs, usually have extra circuitry, besides

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LUT in each logic block.

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C
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Fig. 4.6.4 shows how a flip-flop may be included in
an FPGA logic block.

fo
t.p
When a circuit is implemented in an FPGA, the

s
as
logic blocks are programmed to realize the
necessary functions and the routing channels are
programmed to make the s required
an
interconnections between logic blocks.
et
ch
 I/O Blocks

• Each bank can be configured individually to support a particular I/O standard

IT
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• Allows the FPGA to work with device using multiple I/O standard.

E
C
• FPGA can actually be used to interface between different I/O standards.

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fo
• Modem FPGA output signals with fast edge rates requires termination to prevent

t.p
reflections and maintain signal integrity.

s
as
s
• High pin count package cannot accommodate external termination registers.
an
Thus a Digitally Controlled Impedance (DCI) is employed.
et
ch

• DCI eliminates the need for external register and improves signal integrity.
 Programmable Interconnect
A programmable switch matrix form the heart of interconnect in a FPGA.
The actual switching matrix employed is a structure of six pass transistors

IT
per cross point.

M
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Types of connections

E
C
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1) Single lines : Used to connect a CLB to 3)Long lines : Wires in long groups do not go
another CLB is one hop way. These wires through any programmable switch at all,

fo
instead they travel all the way across or down

t.p
have to go through a programmable switch
hence add delay. a row or column and are driven by tri-state

s
as
drivers.

s
2) Double lines : These wires travel past two
an
CLB before hitting the switch, hence they 4) Global clock lines : These lines are
optimized for case as clock inputs to the CLB,
et

provide shorter delays for longer connections.

ch

providing short delay and minimal skew(clock

skew).
 The FPGA has two-input LUTs, and there are four
wires in each routing channel.
The Fig. 4.6.5 shows the programmed states of both

IT
the logic blocks and wiring switches in a section of

M
the FPGA.

SJ
• Programmable wiring switches are indicated by
an X. Each switch shown in blue is turned on

E
C
and makes a connection between a horizontal and

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vertical wire. The switches shown in black are turned

fo
off.

t.p
The truth tables programmed into the logic blocks in

s
the top row of the FPGA correspond to the

as
functions

s
f1 = X1 X2 and f2 = X2 X3
an
et

• The logic block in the bottom right of the figure is

ch

programmed to produce
 FPGA Programming
• FPGAs are configured by using the ISP(in SRAM based FPGA

IT
system programming) method.

M
• The storage cells in the LUTs in an FPGA The SRAM based FPGA uses SRAM cells for following

SJ
are volatile, which means that they loose purposes.
- Storing logic value 0 or 1.

E
their stored contents

C
- Storing value of Look-up Table (LUT) in logic

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blocks.
• Often a small memory chip that -

fo
To configure interconnection of FPGA.
holds its data permanently, called a -

t.p
Reprogramming of SRAM is possible.
programmable read-only memory -

s
The SRAM based FPGA uses one or two way

as
(PROM), is included on the circuit switches and multiplexers for defining paths.

s
board that houses the FPGA(volatile)
an
et
ch
Fig. shows six pass transistors that allow any
combination of connections of the four wires.
• SRAM cells may be used to control the state of
these pass transistors, which can establish

IT
connections between horizontal and vertical wires

M
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(N, S, E, W). When T1 is ON, it makes connection
between N and W wires.

E
C
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An SRAM memory cell consists of five transistors as
shown in Fig.

fo
t.p
• One transistor used for addressing i.e. used

s
as
to select the memory cell for programming,
four transistors are used to form two inverters.
• s
an
An SRAM cell is reprogrammable and volatile.
• The programming circuitry for SRAM elements
et
ch

must include the addressing and data registers.

• SRAM FPGAs do not have routing architectures
for which there is a programmable element at
nearly intersection.
Antifuse base FPGA 1- Poly-diffusion antifuse :
• An oxide nitride dielectric
• Devices based on antifuse technology are one normally prevents current from

IT
time programmable. An antifuse initially provides flowing between diffusion and poly-

M
insulation between two conductors, but when

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silicon layers.
sufficient programming voltage is applied across
• When programming pulse is

E
it, conducting path forms.

C
applied the dielectric melts and a

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• It is one time programmable, once an antifuse circuit formed between the diffusion

fo
is blown it can not be removed. and poly-silicon.

s t.p
as
• There exists two classes of antifuse technology. 2. Metal-metal antituse :
1. Poly-diffusion antifuse • The link is an alloy of tungsten
2. Metal-metal antifuse s
an
titanium and silicon. Usually the
et

conductive link is formed at the corner

ch

or at via where the electric field is

highest during programming.
 Antifuse Element

• Fig. 4.6.8 shows an unprogrammed antifuse element and programmed antifuse

IT
element.

M
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• In an amorphous silicon based FPGA, two
layers of metal are separated by amorphous

E
C
silicon, it provides electrical insulation.

rE
fo
• A programming pulse of 10V to 12 V

t.p
and of necessary duration can be applied

s
as
across the via. It creates a bidirectional
conductive link between two metals.
s
an
et

• The programmable elements can . be placed

ch

very densely. Once programmed, an antifuse

element cannot be erased or reprogrammed.
Features of Antifuse based FPGA Difference between SRAM & ANTIFUSE FPGA

1. Highest density

IT
M
2. Lowest switch resistance

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3. Very low capacitance
4. Non-volatile

E
C
5. Radiation hard

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6. Software is easy to place
and route.

fo
t.p
s
as
s
an
et
ch
 Module 5
Memory,registers, aspects of system timing, testing and verification
SYSTEM TIMING CONSIDERATIONS

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t.p
s
as
s
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 SOME COMMONLY USED STORAGE/MEMORY ELEMENTS

Some important factors for assessing storage/ memory elements are :

IT
M
• Area Requirement

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• Estimated dissipation per bit stored;

E
• volatility

C
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The Dynamic Shift Register Stage

fo
t.p
One method of storing a single bit is to use the shift register approach

s
as
s
an
et
ch
 IT
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st.p
as
s
an
et
ch

Layout of nmos shift register cell

Area:
This calculation applies to an nMOS design, as in Figure, with buried contacts .
Allowing for the sharing of VDD and GND rails between adjacent rows of register cells, area of each bit
stored will require.

IT
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E
C
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Dissipation:

fo
For CMOS circuits, dynamic power consumption Pd is given by

s t.p
as
s
Where, m is the duty cycle, CL is effective load
an
capacitance and f is the clock frequency.
et
ch

Volatility:
Data is stored by the charge on the gate capacitance of each inverter · stage, so that data
storage time (without refresh) is limited to 1 msec or less.
 A Three-transistor Dynamic RAM Cell
An arrangement which has been used in RAM (random access memory) and other storage arrangements is
set out in Figure
1. Dynamic : Must be refreshed(re

IT
energized) periodically.

M
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2. Volatile : Loses data when power is
removed.

E
C
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Comparing with SRAM

fo
t.p
Static RAM(SRAM) is faster and less

s
volatile than Dynamic RAM(DRAM), but

as
it requires more power and is more
s
an
expensive.
et
ch
This utilize a single transistor as storage device and
one transistor each for RD and WR operation.

IT
When control line RD is LOW,

M
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Then a bit may be read from bus through T1 by
making WR to HIGH this in turns WR to LOW through

E
T2.

C
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fo
The bit value is stored by gate capacitance (Cg) of T2

t.p
while RD and WR are LOW. by making WR to HIGH.

s
as
To read the stored bit, it is only necessary to make RD
s
HIGH and the bus will be pulled down to ground
an
through T3 and T 2 if a 1 was stored, otherwise T2 will
et

be non conducting and the bus will remain HIGH due

ch

to its pull-up arrangements .

ch
et
an
s
as
st.p
fo
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C
E
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M
IT
A One-transistor Dynamic Memory Cell

It is one of the approaches to reduce the area

IT
per bit requirements.

M
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consists of a capacitor Cm which can be charged

E
C
during 'write' from the read/write line, keeping

rE
the row select line HIGH.

fo
t.p
The state of the charge Cm can be read

s
subsequently by detecting the state of the

as
charge via the same read/write line with the row
s
an
select line HIGH again, and a sense amplifier of a
et

suitable nature can be designed to differentiate

ch

between a stored 0 and a stored 1.

ch
et
an
s
as
st.p
fo
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C
E
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M
IT
ch
et
an
s
as
st.p
fo
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C
E
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M
IT
 A One-transistor Dynamic Memory Cell
• This is an approach which reduces area/bit
• It consists of capacitor Cm and pass transistor. The circuit arrangement and
stick diagram is shown in Fig a & b. Write operation

IT
• The capacitor Cm will be charged when Read/Write =

M
1 and Row Select = 1

SJ
• If the Read/Write line is provided with logic 1, Cm will
be charged to logic 1 and,

E
• If the line is provided with logic 0 charge stored will

C
be logic 0.

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fo
Read operation

s t.p
• If logic 0 is stored in Cm and when Row select line is

as
high M1 is ON. Then,
•The sense amplifier at the bit line will sense and give
s
an
the output as logic 0
• If logic 1 is stored in Cm and when Row select line is
et

high M1 is ON, the logic 1 stored will begin to discharge

ch

as the path exists.

•The sense amplifier senses this and this gives the
output as logic 1
 Pseudo-static RAM/register cell
•This is a memory cell which combines high storage capability of DRAM and ease of use of SRAM.
• It can be used as SRAM as no external refreshing circuit is required and also used as a DRAM having built-in refresh
logic.

IT
•This is a static storage cell which will hold data indefinitely. This is achieved by storing bit in 2 inverters with

M
feedback. This feedback is used to refresh the data in every clock cycle.

SJ
• ϕ1 and ϕ2 are mutually exclusive clock signals, WR

E
C
and RD signal coincides with ϕ1 signals

rE
•When ϕ1 is high and WR = 1, transistor T1 is ON and
data is charged/stored on Cg (gate capacitance) of

fo
inverter. ---WRITE operation

t.p
•When ϕ1 is high and RD = 1, transistor & the data

s
stored at inverter stage is made available at the

as
output and also the compliment. Thus data is READ at

s
the output.
an
•When Φ2 = 1, T3 is ON. The output is read and
et

feedback i.e., refreshed (reading and

ch

storing back the data). The gated feedback path from

output of T2 is fed to the input of T1
 IT
M
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E
C
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fo
s t.p
as
s
an
et
ch

The pseudo static memory cell can also be implemented

using transmission gate (TG).
 ▪ The cells here include both n type and p

IT
type transistors and are intended for CMOS

M
SJ
systems.

E
C
• Both the dynamic and static elements uses

rE
2 bus per bit arrangement so that the bit is

fo
available in both normal and compliment

t.p
form on bit and bit’ bus

s
as
s
▪ Prior to reading and writing operation of
an
the data, the buses are precharged to VDD or
et

logic 1.
ch
ch
et
an
s
as
st.p
fo
rE
C
E
SJ
M
IT