Department of Electronics and Communication Engineering

CMOS Processing Technology

By
Dr.K.Ezhilarasan,
Associate Professor,
Department of ECE,
SJC Institute of Technology

Course Code: BEC602 Course Name: VLSI Design and Testing

 Outline
• Silicon Semiconductor Technology
• Wafer Processing, Oxidation, Selective Diffusion, Silicon gate Process,
• CMOS technologies
• P-Well Process, n-Well Process, Twin Tub Process, Silicon on insulator
(SOI), CMOS Process Fundamentals
• Layout Design Rule
• Layer Representation, Lambda Based p-Well rules, Lambda based SOI
Rule, Double Metal Design Rules, Design Rules Summary

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 Silicon Semiconductor Technology
• Silicon is a semiconductor with a bulk electrical resistance
between conductor and insulator.
• Conductivity can be varied by introducing impurity atoms.
• Impurities that use electrons: acceptors (p-type), e.g., Boron.

• Impurities that provide electrons: donors (n-type), e.g., Phosphorous.

• Dopants supply free electrons or holes.

• Acceptors use electrons, leaving vacancies or holes.
• Donor elements provide electrons.
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• Silicon with majority of donors is n-type, and p-type
contains majority of acceptors.
• Junctions are formed when n-type and p-type materials are
combined.
• Junctions can be arranged in physical structures to construct
various semiconductor devices.
• Silicon semiconductor processing has evolved techniques for
building junctions and other structures.
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 Wafer Processing

• The basic raw material in modern

semiconductor plants is a wafer or disk of
silicon, ranging from 150mm – 300mm in
diameter and less than 1mm thick.
• Wafers are cut from single crystal silicon
ingots pulled from a crucible melt of pure
molten polycrystalline silicon, known as
the "Czochralski" method.
Figure; An nMOS transistor showing the growth of field oxide in both vertical directions
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• Controlled amounts of impurities are added to the melt to provide the crystal
with the required electrical properties.
• The crystal orientation is determined by a seed crystal dipped into the melt to
initiate single crystal growth.
• The melt is contained in a quartz crucible surrounded by a graphite
radiator, heated by radio frequency induction and maintained above the
melting point of silicon.
• The diameter of the ingot is determined by the seed withdrawal rate and
the seed rotation rate (Growth Rate is Range from 30 – 180mm/Hr).
• Wafers are usually between 0.25mm and 1.0mm thick, depending on their
diameter.
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 Oxidation Process

• Silicon integrated circuits rely on

silicon dioxide (Si02) properties.
• Reliable Si02 manufacture is
crucial.
• Oxidation of silicon is achieved by
heating silicon wafers in an
oxidizing atmosphere.

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• Two common approaches:
• Wet oxidation (containing water vapor) and
• Dry oxidation (pure oxygen).

• Wet oxidation grows at temperatures between 900°C and 1000°C.

• Si02 layer grows almost equally in both vertical directions due to its
twice the volume of silicon.(Temp are in the regions of 1200 degree C)

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 Selective Diffusion Process
Silicon Processing and Doping
• Different types of silicon require precise placement and size.
• Si02 acts as a barrier against doping impurities in selective
diffusion.
• Si02 layer can be used as a pattern mask.
• Absence of Si02 on silicon wafer surface allows dopant atoms
to pass, altering silicon characteristics.
• Si02 overlays act as barriers to dopant atoms.
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 • The selective diffusion entails
• Opening windows in a layer of
Si02 grown on the surface of
the wafer.

• Removing Si02, but not Si, with

a suitable etchant.

• Subjecting exposed Si to a

dopant source

Figure:. Simplified steps involved in the patterning of SiO2

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Selective Oxide Removal Process
• Covers oxide surface with acid-resistant coating, except diffusion windows.
• Removes SiO2 using etching technique.
• Acid-resistant coating is photosensitive organic material called photoresist (PR),
polymerized by UV light.
• UV light passes through a mask containing desired pattern, polymerizing the coating.
• Unpolymerized areas can be removed with an organic solvent.
• Etching of exposed SiO2 proceeds.
• Established processes limit line widths to 1.5 um to 2 um.
• Recent years, Electron Beam Lithography (EBL) offers line widths of 0.5 um with good
definition.
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• Advantages of EBL Pattern Generation

• Patterns are derived directly from digital data.

• There are no intermediate hardware images such as recticles or masks; that is the
process may be direct.

• Different patterns may be accommodated in different sections of the wafer without difficulty.

• Changes to patterns can be implemented quickly

• Disadvantages

• The use of this technique in commercial fabrication lines is the cost of equipment and the
large amount of time required to access all points on the wafer.
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 Silicon Gate Process
• Silicon is used in wafer manufacturing and circuit operation.
• Polycrystalline silicon, or polysilicon, is an amorphous form used as an
interconnect in silicon ICs and as the gate electrode on MOS transistors.
• Polysilicon acts as a mask for precise definition of source and drain
electrodes, improving circuit performance
• Polysilicon is formed when silicon is deposited on SiO2 or other surfaces.
• In MOS transistor gate electrodes, undoped polysilicon is deposited on
the gate insulator.

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• Silicon Gate Process Overview
• Initial patterning of SiO2 involves photomasking and oxide etching.
• Field oxide, a thick layer of SiO2, is etched to the silicon surface for transistor
placement.
• Gate oxide, a thin layer of Si02, grows on the exposed silicon surface.
• Polysilicon is deposited over the wafer surface and etched to form
interconnections and transistor gates.
• Exposed thinox is etched away.

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 Figure: Fabrication Steps for a silicon gate nMOS Transistor
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 Figure: Fabrication Steps for a silicon gate nMOS Transistor
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• The wafer is exposed to a dopant source, forming diffusion
junctions and doping polysilicon with a specific dopant.
• Diffusion junctions form the drain and source of the MOS transistor,
forming only in regions where the polysilicon gate doesn't shadow
the underlying substrate.
• The structure is covered with SiO2, and contact holes are etched to
make contact with underlying layers.
• Aluminum or other metallic interconnect is evaporated and etched to
complete the final connection of elements.
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CMOS Technologies

• CMOS (Complementary Metal Oxide Silicon) technology is

recognized leading contender for existing and future VLSI
systems.

• CMOS provides an inherently low power static circuit

technology that has the capability of providing a lower
power-delay product than parable design-rule nMOS or
pMOS technologies
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Four Dominant CMOS Technologies
• P-Well Process
• N-Well Process
• Twin Tub Process
• Silicon On Insulator (SOI)

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 P-Well Process
Step 1: A thin Sio2 layer is deposited on an
n-type semiconductor material which
acts insulator to the environment.

Step 2: Using chemical vapor deposition

(CVD) the thick silicon nitride layer is
deposited on the SiO2 layer.

Step 3: A plasma etching process is used to

make trenches for insulating the device
from the external environment.

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 P-Well Process
Step 4: These trenches are filled
with SiO2 which is called the
field oxide which insulates the
device.

Step 5: Using the mechanical

planarization process the
sacrificial nitride layer and the pad
oxide are removed until the flat
surface is on the layer.

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P-Well Process Continue..
Step 6: To adjust the doping process the p-well areas
are exposed with masks and later annealing and
implant are applied. This is followed by a second
implant step to adjust the threshold voltage of the
NMOS transistor.

Step 7: The implant step is performed to adjust the

threshold voltage of the PMOS transistor.

Step 8: The metal contacts are made at the positions

and the grounds are connected which prevents the
device from high currents and voltages.

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P-Well Process Continue..
Step 9: Ion implantation is carried out at the source and drain regions of PMOS (p+) and NMOS
(n+) transistors, this will also form the n+ polysilicon gate and p+ polysilicon gate for NMOS and
PMOS transistors respectively. This process is also known as the self-aligned method.

Step 10: Oxide and Nitride spacers are formed by the

chemical vapor deposition.

Step 11: Holes are etched, metal is deposited,

and patterned. After the deposition of the last metal layer

final over-glass is deposited for protection.

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STEP -1: The first mask defines the p-well (or p-tub); n-channel
transistors will be fabricated in this well. Field oxide (FOX) is etched away
to allow a deep diffusion

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STEP-2: The next mask is called the “thin oxide” or “thinox” mask, as it
defines where areas of thin oxide are needed to implement transistor gates
and allow implantation to form p- or n-type diffusions for transistor
source/drain regions.
• The field oxide areas are etched to the silicon surface and then the thin oxide
is grown on these areas (Fig. 3.6b). Other terms for this mask include active
area, island, and mesa. In nMOS this would be the diffusion mask

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STEP – 3: Polysilicon gate definition is then completed. This involves
covering the surface with polysilicon and then etching the
required pattern (in this case an inverted “U”). As noted previously,
the “poly” gate regions lead to “self-aligned” source-drain regions

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STEP-4: A p-plus (p + ) mask is then used to indicate those thin-oxide areas
(and polysilicon) that are to be implanted p +.
• Hence a thin-oxide area exposed by the p-plus mask will become a p +
diffusion area (Fig. 3.6d).
• If the p-plus area is in the n-substrate, then a p-channel transistor or p-type
wire may be constructed.
• If the p-plus area is in the p-well (not shown), then an ohmic contact to the p-
well may be constructed

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STEP-5: The next step usually uses the complement of the p-plus mask, although an extra
mask is normally not needed.
• The "absence” of a p-plus region over a thin-oxide area indicates that the area will be
an n + diffusion or n-thinox. n-thinox in the p-well defines possible n-transistors and
wires (Fig. 3.6e).
• An n ~ diffusion in the n-substrate allows an ohmic contact to be made. Following this
step, the surface of the chip is covered with a layer of Si02

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STEP – 5 & 6: Contact cuts are then defined. This involves etching any
Si02 down to the contacted surface (Fig. 3.6f). These allow metal (next
step) to contact diffusion regions or polysilicon regions. • Metallization is
then applied to the surface and selectively etched.

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STEP – 7: As a final step (not shown), the wafer is passivated and
openings to the bond pads are etched to allow for wire bonding.
Passivation protects the silicon surface against the ingress of
contaminants that can modify circuit behavior in deleterious ways

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Cross Sectional View of P-Well Process

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P-Well Diffusion and Its Impact on N-channel Devices

• P-well diffusion affects threshold voltages and breakdown

voltages of n-channel devices.
• Deep well diffusion or high well resistivity is needed for low
threshold voltages (0.6V—1.0V).
• Deep junctions require larger spacings between n-type and p-
type transistors due to lateral diffusion.
• High resistivity can exacerbate latch-up problems.
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• N-transistors suffer from excessive source/drain to p-well
capacitance due to higher concentration.
• Circuits involving n-transistors are slower than typical nMOS
depletion load process.
• To prevent "latch-up," the well must be grounded to minimize
voltage drop due to injected current in the substrate.

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• Positive p-well supply process
(VDD) connects the substrate to
contacts.
• Well is connected to negative
supply (Vss) through Vss substrate
contacts.
• Vss contact uses topside
connection of substrate, reducing
parasitic resistances.
• VDD backside contact may be used,
but topside connection is preferred. Figure: P-Well Substrate Contact
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• Contacts formed by placing p+ regions in the p-well (Vss contacts) and n+ in
the n-type substrate (VDD contacts).
• Terminologies for these contacts include "well contacts" for Vss substrate
connection or "body ties.“
• Contacts are formed during p-channel and n-channel transistor formation
implants.

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 Other - P-Well CMOS Process

• To meet the growing need for higher packing density, improvements in

latch-up, and independent threshold adjustment, a number of improved
p-well CMOS processes have emerged during recent years.

• Retrograde p-well CMOS process developed by GE-Intersil, Inc.

• “CMOSC” process developed by Hewlett-Packard

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 GE-Intersil’s retrograde p well process
“ - ”

Retrograde Boron Implant Process.

• Involves a thermal implanted diffusion process.
• P-well impurities do not diffuse from their original position, reducing
lateral diffusion.
• Allows reductions in spacing between p- and n-transistors.
• Junction depth sheet resistance and threshold voltage are
independent, allowing separate adjustment for optimizing CMOS
device behavior.
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 Figure: GE-Intersil’s “retrograde p-well” process

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 Figure: GE-Intersil’s “retrograde p-well” process

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 Hewlett Packard’s CMOSC Process
CMOSC Process Improvements
• Use of boron and phosphorus implants for defining p-transistors and n-
transistors respectively.
• Characterization of field oxide growth for low standby eakage current
• Improved control of implanted source/drain junction's lateral diffusion.
• Increased integrity of gate oxide edge.
• Thinning of field oxide during contact etch increases leakage currents.
• Inhibiting "bird's beak" effect improves leakage mechanism.

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 Bird’s Beak Effect

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 N-Well Process - Berkeley
• Previously, p-well processes were the most common CMOS forms.
• The n-well process can be fabricated on the same process line as
conventional nMOS, making it often "retrofitted" to existing nMOS processes.
• The n-well fabrication steps are similar to a p-well process, but with an n-well
used.
• The first masking step defines the n-well regions.
• A low-dose phosphorous implant is driven in by a high-temperature step for
the formation of the nwell.

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 Cross section view – n-Well based CMOS inverter

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 Berkeley N-Well Process –
Layout for n-well Inverter
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 Twin – Tub Process
• Provides basis for optimizing p-type and n-type transistors.
• Allows independent optimization of threshold voltage, body
effect, and gain.
• Starter material: either an n or p substrate with a lightly doped
epitaxial layer.
• Epitaxy aims to grow high purity silicon layers with
homogeneous dopant concentrations.

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Twin Tub Process Continue..

• Common P-wee & N-well Steps are followed

• Tub Formation
• Thin oxide etching
• Source and drain implantations
• Contact cut definition
• Metallization
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 Cross Section view – Twin Tub Process – CMOS inverter

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Silicon On Insulator (SOI)
• Silicon on insulator (SOI) refers to the use of a three layered substrate in place of
conventional bulk silicon substrates.

• A thin layer of silicon is placed on top of an insulator such as silicon dioxide

(SiO2) also known as a buried oxide layer. This layer lies upon the substrate and
isolates the body from the substrate.

• The transistors are then built upon the thin silicon layer. The full dielectric
isolation of the devices reduces parasitic capacitance, thereby improving
performance.

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What is need of SOI?

• For the continuation of Moore’s Law beyond 28 nm with an upgrade to

traditional planar bulk CMOS technology.

• Increased complexities in scaling of conventional bulk CMOS technology.

• To avoid interactions between the devices and the substrate which gives
rise to unwanted parasitic effects, mainly the parasitic capacitance
developed between diffused source and drain and the substrate.

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• To prevent latchup, which is the generation of a low impedance path
between the Vdd & Vss rails due to formation of parasitic pnp and npn
Bipolar Junction Transistors in a bulk CMOS process. These BJTs form a
pnpn structure with positive feedback and virtually short-circuit the
power rail to ground, thus causing excessive current flows and even
permanent device damage.

• The full dielectric isolation of the devices reduces parasitic

capacitance, thereby improving performance. To overcome short-channel
effects inherent to sub-micron devices.

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• As transistor shrinks, the length of the gate is reduced.

• The control of the gate over a channel region is also reduced, thus lowering

the transistor performance.

• SOI provides more control over channel using body biasing.

• To reduce the growing leakage power due to subthreshold leakage and

diode leakage currents.

• To reduce manufacturing complexity while continuing to deliver high

perfomance at lower cost and with lower power consumption.

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SOI Process Flow
• In the SOI process a thin layer of single crystal silicon film is
epitaxially grown on an insulator such as sapphire or magnesium
aluminate spinel.
• Various masking and doping techniques are then used to form p-
channel and n-channel devices. Unlike the more conventional CMOS

approaches

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SOI Process Flow Continue..

Thin file – 7 to 8um of very lightly doped n-type

(Commonly used Insulator)

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SOI Process Flow Continue..

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SOI Process Flow Continue..

Thin gate Oxide (500 – 600 Armstrong) is grown all over the Si structure using Thermal Oxidation

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SOI Process Flow Continue..

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SOI Process Flow Continue..

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Difference b/w Bulk CMOS & SOI Process

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How to Improvement of Yield?
• some processes use “preferential etch” in which the island edges are
tapered.
• Aluminum or poly runners can enter and leave the islands with a minimum
step height. This is contrasted to “fully anisotropic etch” in which the
undercut is brought to zero as shown in Figure.
• An “isotropic etch” is also shown in the same diagram for comparison.

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Classification of Etch Process

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Advantages of SOI Technology
• Better electrostatic control of the channel.

• Reduction of parasitic junction capacitances.

• Excellent latchup immunity because of buried oxide layer.

• Limited short channel effects compared to bulk CMOS technology.

• Reduced subthreshold leakage and diode leakage.

• Higher speed and lower power consumption.

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• Gives high-performance and cost-effective alternative to bulk CMOS
technology.
• Smaller transistor saves lot of area and provides higher packaging
density.
• Involves fewer manufacturing and processing steps than bulk CMOS
technology.
• Simpler technology with no wells and trenches.
• Substrate noise is reduced because the buried oxide layer acts as a
dielectric barrier.

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CMOS Process Enhancements

• To Enhance the CMOS Process

• Increase the routability of circuits
• Provide high quality capacitors for analog circuits & Memories
• Provide resistor of variable Characteristics
• Double or Triple Level Metal
• Double or Triple Level Poly
• Combinations of the above

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• For example, a second level of good quality interconnect is
almost mandatory in modern processes.
• One method that requires no extra mask levels is to reduce the
polysilicon resistance by combining it with a refractory metal

Approach - 1
• silicide (e.g., silicon and
tantalum) is used as the
gate material.
• Sheet resistances of the
order of 1-2 Ω/ may be
obtained.
• This is called the silicide
gate approach
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 Approach - 2
• It uses a sandwich of silicide upon
polysilicon, which is commonly called the
polycide approach

Approach - 3 • A molybdenum gate, capped with

silicide yields a metal/silicide sandwich
or heart of moly structure

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 Approach - 4
• Finally, the silicide/polysilicon approach may be
extended to include the formation of source and drain
regions using the silicide. This is called the salicide
process

The effect of all of these processes is to reduce the “second

layer” interconnect resistance, allowing the gate material
to be used as a reasonable long distance interconnect

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Layout Design Rules
• Layout rules, or design rules, are crucial for preparing photomasks
used in integrated circuit fabrication.
• They serve as a communication link between circuit designer and
process engineer during the manufacturing phase.
• The main objective is to achieve the circuit with optimum yield in
minimal geometry without compromising reliability.
• Design rules represent the best compromise between performance
and yield.
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• The design rules primarily address two issues:
• 1) the geometrical reproduction of features that can be
reproduced by the mask masking and lithographical
process,
• 2) the interactions between different layers

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Layout (or) Design Rule

Technology = lambda / 2

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 Derivation of lambda based rules from micron rules

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 Layout Representation of P-Well Process

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 Lambda Based layout Rules

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 Lambda Based layout Rules

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 Lambda Based layout Rules

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Issues in P-well Rule
• Well Spacing Separation Rule
• Transistor Rule
• Contacts
• Poly Doping
• P+ and Gate Edges
• Guard Rings

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 Lambda Based P-Well Rules
MASK -1 : THINOX

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 MASK 2: P - WELL

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 MASK 3: Polysilicon

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 MASK 4: P-Plus

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 MASK 5: Contact

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 MASK 5: Contact

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 MASK 6: Contact

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 Influence of Lateral Diffusion of P-Well

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 Influence of Lateral Diffusion of P-Well

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 Different Types of Contacts

• Metal to P—thinox (P-Diffussion)

• Metal to N- Thinox (N – Diffussion)
• Metal to Polysilicon
• VDD and VSS (Substrate Contacts)
• Spilit (Substrate Contacts)
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 Guard Rings
• Guard rings in analog design are
large taps that completely enclose a
group of devices.
• Guard rings more effectively isolate
devices from each other, by creating
a low resistance ring in the
well/substrate around the group.
• This prevents charge buildup by other
devices or fluctuating potential of
other devices from affecting the
operation of the guarded group.
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Two Input NAND Gate

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 Lambda Based Rule for SOI

Island

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 Implant

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 Polysilicon

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 Contact

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 Metal

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