Date:- 23/07/2025
CMOS PROCESSES
SRI VENKATA KASYAP CHALLAPALLI
CONTENT TABLE
S. No Topic
1. Basic N-Well CMOS Process
2 Basic P-Well CMOS Process
3 Duel Well or Twin Tub Process
4 Silicon on Insulator Process
5. Cleanliness and Yield
1. Basic N-Well CMOS
The first step of the process is the oxidation of the silicon substrate, which creates a relatively
thick silicon dioxide layer on the surface. This oxide layer is called field oxide. The field oxide
is then selectively etched to expose the silicon surface on which the transistor will be created.
After this the surface is covered with a thin, high-quality oxide layer. This oxide layer will
form the gate oxide of the MOS transistor. Then a polysilicon layer is deposited on the thin
oxide.
Polysilicon is used as both a gate electrode material for MOS transistors as well as an
interconnect medium in silicon integrated circuits. The resistivity of polysilicon, which is
usually high, is reduced by doping it with impurity atoms. Deposition is followed by
patterning and etching of polysilicon layer to form the interconnects and the MOS transistor
gates.
1. Basic N-Well CMOS
The thin gate oxide not masked by polysilicon is also etched away exposing the bare silicon
surface. The drain and source junctions are to be formed. Diffusion or ion implantation is
used to dope the entire silicon surface with a high concentration of impurities (in this case
donor atoms to produce n-type doping).Two n-type regions (source and drain junctions) in
the p-type substrate as doping penetrates the exposed areas of the silicon surface.
The penetration of impurity doping into the polysilicon reduces its resistivity. The polysilicon
gate is patterned before the doping and it precisely defines the location of the channel region
and hence, the location of the source and drain regions. Hence this process is called a self-
aligning process. The entire surface is again covered with an insulating layer of silicon dioxide
after the source and drain regions are completed.
1. Basic N-Well CMOS
Next contact windows for the source and drain are patterned into the oxide layer.
Interconnects are formed by evaporating aluminum on the surface, which is followed by
patterning and etching of the metal layer. A second or third layer of metallic interconnect can
also be added after adding another oxide layer, cutting (via) holes, depositing and patterning
the metal.
2. Basic P-Well CMOS
The fabrication steps of p well process are same as that of an n-well process except that
instead of n-well a p-well is implanted. The process starts with the n type substrate.
Step 1: A thin layer of SiO₂ is deposited which will serve as the pad oxide.
Step 2: A thicker sacrificial silicon nitride layer is deposited by chemical vapor deposition
(CVD).
Step 3: A plasma etching process is used to create trenches used for insulating the devices.
Step 4: The trenches are filled with SiO₂ which is called as the field oxide.
Step 5: To provide flat surface chemical mechanical planarization is performed and also
sacrificial nitride and pad oxide is removed.
Step 6: The p-well mask is used to expose only the p-well areas, after this implant and
annealing sequence is applied to adjust the well doping. This is followed by a second implant
step to adjust the threshold voltage of the NMOS transistor.
Step 7: Implant step is performed to adjust the threshold voltage of PMOS transistor.
Step 8: A thin layer of gate oxide and polysilicon is chemically deposited and patterned with
the help of polysilicon mask.
Step 9: Ion implantation to dope the source and drain regions of the PMOS (p) and NMOS
(n) transistors, this will also form n polysilicon gate and p polysilicon gate for NMOS and
PMOS transistors respectively. Hence this process is called as self-aligned process.
Step 10: Then the oxide and nitride spacers are formed by chemical vapor deposition.
Step 11: In this step contact or via holes are etched, metal is deposited and patterned. After
the deposition of last metal layer final passivation or over glass is deposited for protection.
3. Duel Well Process or Twin Tub
In Duel-well process both p-well and n-well for NMOS and PMOS transistors respectively
are formed on the same substrate. The main advantage of this process is that the threshold
voltage, body effect parameter and the transconductance can be optimized separately. The
starting material for this process is p+ substrate with epitaxially grown p-layer which is also
called as epilayer. The process starts with a p-substrate surfaced with a lightly doped p-
epitaxial layer.
Step 1: A thin layer of SiO₂ is deposited which will serve as the pad oxide.
Step 2: A thicker sacrificial silicon nitride layer is deposited by chemical vapor deposition.
Step 3: A plasma etching process is used to create trenches used for insulating the devices.
Step 4: The trenches are filled with SiO₂ which is called as the field oxide.
Step 5: To provide flat surface chemical mechanical planarization is performed and also
sacrificial nitride and pad oxide is removed.
Step 6: The p-well mask is used to expose only the p-well areas, after this implant and
annealing sequence is applied to adjust the well doping. This is followed by second implant
step to adjust the threshold NMOS transistor.
Step 7: The n-well mask is used to expose only the n-well areas, after this implant and
annealing sequence is applied to adjust the well doping. This is followed by a second implant
step to adjust the threshold voltage of PMOS transistor.
Step 8: A thin layer of gate oxide and polysilicon is chemically deposited and patterned with
the help of polysilicon mask.
Step 9: Ion implantation to dope the source and drain regions of the PMOS (p) and NMOS
(n) transistors is used this will also form n polysilicon gate and p polysilicon gate for NMOS
and PMOS transistors respectively.
Step 10: Then the oxide or nitride spacers are formed by chemical vapor deposition (CVD).
Step 11: In this step contact or holes are etched, metal is deposited and patterned. After the
deposition of last metal layer final passivation or over glass is deposited for protection.
3. Duel Well Process or Twin Tub
4. Silicon on Insulator Process (SOI)
Silicon-on-Insulator (SOI) has been under active consideration for the last many years. SOI
refers to placing a thin layer of silicon on top of an insulator such as silicon oxide or glass.
The transistors would then be built on top of this thin layer of SOI. The basic idea is that the
SOI layer will reduce the capacitance of the switch, so it will operate faster.
One of the areas that can store charge in a MOS switch is the silicon substrate itself. Since an
insulator act as a substrate, the junction capacitance will be eliminated and the MOS
transistor will operate faster. The body effect problems and latch up problems are eliminated
in SOI. One of the first early applications of SOI has been in memories for space application;
since the memories built on SOI were perceived to be more resistant to soft error rate. Soft
error rate refers to upset of data in the memory by cosmic rays and background radioactive
material. Due to the absence of wells, a closer transistor packing can be achieved in SOI. The
major disadvantages of SOI are that it presents lower gains and higher cost. Protecting
diodes at inputs cannot be realized in SOI due to absence of silicon substrates.
5. Cleanliness and Yield
During processing, ICs are very susceptible to any kind of small particle or defect landing on
the surface of the IC. ICs in wafer form are referred to as die. Experience has shown that
particles 1/2 to 1/3 the size of the smallest feature on an IC can "kill" the die - referred to as a
killer defect. For 65nm processing, particles as small as 22 to 33nm in size can kill the circuit,
and measurements of atmospheric air have found that there are millions of particles that size
or larger in a cubic foot of air. The mechanics of particle deposition from air are quite
complex but suffice it to say that with millions of particles floating around, the likelihood of
a killer defect landing on a given die is very high.
The number of killer defects is characterized by the defect density on the wafer surface given
in defects per unit area. The resulting yield depends on the size of the die and the defect
density. Actual yield calculations require yield probability models, but the basic concept is
illustrated in figure 15. On the left side of figure, a wafer is shown with a defect pattern of 20
defects and a relatively small die that results in 264 die per wafer. The number of die without
defects is 244 and the resulting yield is 92%. On the right side of the figure a wafer is shown
with the same defect pattern, but a larger die. There are 54 die per wafer of which 38 die have
no defect resulting in a 70% yield!
In order to meet the cleanliness requirements and manufacture ICs with high yield, clean-
rooms are used. Cleanrooms are rooms with continuous circulation of air out of the room,
through a high quality HEPA or ULPA filter and back into the room continuously sweeping
particles out of the room.
5. Cleanliness and Yield
Figure illustrates a simple cleanroom. Cleanrooms used for IC production have the filters
located in the ceiling and the air flows down the room to or near the floor before exiting the
room. The down flow or vertical style of cleanroom keeps the dirtiest air down near the floor
where no work is exposed and has the benefit of gravity aiding in particle removal. The
quality of clean-rooms is defined by federal standard 209E. Under 209E, a cleanroom with
less than 100 particles per cubic foot larger than 0.5µm is a Class 100 cleanroom, or less than
10 particles per cubic foot greater than 0.5µm is class 10, and so on. High yield on current
state-of-the-art ICs requires better than Class 1 clean rooms.
Water, chemicals and gases utilized in the manufacturing process must also be low in
particles and free of contaminants down to the parts-per-billion or even parts-per-trillion
range.
