MOORE’S LAW:

• Moore's Law states that the number of transistors on a microchip double

about every two years, though the cost of computers is halved.

• In 1965, Gordon E. Moore, the co-founder of Intel, made this observation

that became known as Moore's Law.

• Another tenet of Moore's Law says that the growth of microprocessors is

exponential.
CMOS Fabrication
For less power dissipation requirement CMOS technology is used for implementing
transistors. If we require a faster circuit then transistors are implemented over IC using BJT.
Fabrication of CMOS transistors as IC’s can be done in three different methods.
The N-well / P-well technology, where n-type diffusion is done over a p-type substrate or p-
type diffusion is done over n-type substrate respectively. The Twin well technology,
where NMOS and PMOS transistor are developed over the wafer by simultaneous diffusion
over an epitaxial growth base, rather than a substrate. The silicon On Insulator process, where
rather than using silicon as the substrate an insulator material is used to improve speed and
latch-up susceptibility.

N- well/ P- well Technology

CMOS can be obtained by integrating both NMOS and PMOS transistors over the same
silicon wafer. In N–well technology an n-type well is diffused on a p-type substrate whereas in
P- well it is vice- verse.
CMOS Fabrication Steps

The CMOS fabrication process flow is conducted using twenty basic fabrication steps while
manufactured using N- well/P-well technology.
Making of CMOS using N well

Step 1: First we choose a substrate as a base for fabrication. For N- well, a P-type silicon
substrate is selected.

Substrate

Step 2 – Oxidation: The selective diffusion of n-type impurities is accomplished using SiO2
as a barrier which protects portions of the wafer against contamination of the substrate. SiO 2 is
laid out by oxidation process done exposing the substrate to high-quality oxygen and hydrogen
in an oxidation chamber at approximately 10000c

Oxidation
Step 3 – Growing of Photoresist: At this stage to permit the selective etching, the SiO2 layer
is subjected to the photolithography process. In this process, the wafer is coated with a uniform
film of a photosensitive emulsion.

Growing of Photoresist

Step 4 – Masking: This step is the continuation of the photolithography process. In this step,
a desired pattern of openness is made using a stencil. This stencil is used as a mask over the
photoresist. The substrate is now exposed to UV rays the photoresist present under the exposed
regions of mask gets polymerized.

Masking of Photoresist

Step 5 – Removal of Unexposed Photoresist: The mask is removed and the unexposed region
of photoresist is dissolved by developing wafer using a chemical such as Trichloroethylene.

Removal of Photoresist
Step 6 – Etching: The wafer is immersed in an etching solution of hydrofluoric acid, which
removes the oxide from the areas through which dopants are to be diffused.

Etching of SiO2

Step 7 – Removal of Whole Photoresist Layer: During the etching process, those portions
of SiO2 which are protected by the photoresist layer are not affected. The photoresist mask is
now stripped off with a chemical solvent (hot H2SO4).

Removal of Photoresist Layer

Step 8 – Formation of N-well: The n-type impurities are diffused into the p-type substrate
through the exposed region thus forming an N- well.

Formation of N-well
Step 9 – Removal of SiO2: The layer of SiO2 is now removed by using hydrofluoric acid.

Removal of SiO2

Step 10 – Deposition of Polysilicon: The misalignment of the gate of a CMOS

transistor would lead to the unwanted capacitance which could harm circuit. So, to prevent
this “Self-aligned gate process” is preferred where gate regions are formed before the formation
of source and drain using ion implantation.

Deposition of Polysilicon

Polysilicon is used for formation of the gate because it can withstand the high temperature
greater than 80000c when a wafer is subjected to annealing methods for formation of source
and drain. Polysilicon is deposited by using Chemical Deposition Process over a thin layer of
gate oxide. This thin gate oxide under the Polysilicon layer prevents further doping under the
gate region.
Step 11 – Formation of Gate Region: Except the two regions required for formation of the
gate for NMOS and PMOS transistors the remaining portion of Polysilicon is stripped off.
 Formation of Gate Region

Step 12 – Oxidation Process: An oxidation layer is deposited over the wafer which acts as a
shield for further diffusion and metallization processes.

Oxidation Process

Step 13 – Masking and Diffusion: For making regions for diffusion of n-type impurities using
masking process small gaps are made.

Masking

Using diffusion process three n+ regions are developed for the formation of terminals of
NMOS.
 N-diffusion
Step 14 – Removal of Oxide: The oxide layer is stripped off.

Removal of Oxide
Step 15 – P-type Diffusion: Similar to the n-type diffusion for forming the terminals of
PMOS p-type diffusion are carried out.

P-Type Diffusion
Step 16 – Laying of Thick Field oxide: Before forming the metal terminals a thick field
oxide is laid out to form a protective layer for the regions of the wafer where no terminals are
required.

Thick Field oxide Layer

Step 17 – Metallization: This step is used for the formation of metal terminals which can
provide interconnections. Aluminum is spread on the whole wafer.

Metallization
Step 18 – Removal of Excess Metal: The excess metal is removed from the wafer.
Step 19 – Formation of Terminals: In the gaps formed after removal of excess metal
terminals are formed for the interconnections.

Formation of Terminals
Step 20 – Assigning the Terminal Names: Names are assigned to the terminals of NMOS
and PMOS transistors.
 BiCMOS Technology
This is one of the major semiconductor technologies and is a highly developed
technology, in 1990’s incorporating two separate technologies, namely bipolar junction
transistor and CMOS transistor in a single modern integrated circuit. So, for the better
indulgent of this technology, we can have glance at CMOS technology and Bipolar technology
in brief.
CMOS Technology

It is a complementary of MOS technology or CSG (Commodore Semiconductor Group)

which was started as source for manufacturing the electronic calculators. After that
complementary of MOS technology called CMOS technology is used for developing the
integrated circuits such as digital logic circuits along with microcontrollers and
microprocessors. CMOS technology affords benefit of less power dissipation and low noise
margin with high packing density.
The figure shows the utilization of CMOS technology in manufacturing the digital controlled
switch devices.

Bipolar Technology

Bipolar transistors are part of integrated circuits and their operation is based on two
types of semiconductor material or depends on both types of charge carriers holes and
electrons.These are generally classified into two types as PNP and NPN,classified based on
doping of its three terminals and their polarities. It affords high switching as well as
input/output speed with good noise performance.
BiCMOS Logic

It is a complex processing technology that provides NMOS and PMOS technologies

amalgamated each other with the advantages of having very low power consumption bipolar
technology and high speed over CMOS technology.MOSFETs grant high input impedance
logic gates and bipolar transistors provide high current gain.

14 Steps for BiCMOS Fabrication using n-well process:

The BiCMOS fabrication combines the process of fabrication of BJT and CMOS, but merely
variation is a realization of the base. The following steps show the BiCMOS fabrication
process.

Step1: P-Substrate is taken as shown in the below figure

P-substrate

Step2: The p-substrate is covered with the oxide layer

P-substrate with oxide layer

Step3: A small opening is made on the oxide layer

Opening is made on the oxide layer

Step4: N-type impurities are heavily doped through the opening

N-type impurities are heavily doped through the opening

Step5: The P – Epitaxy layer is grown on the entire surface

Epitaxy layer is grown on the entire surface

Step6: Again, entire layer is covered with the oxide layer and two openings are made through
this oxide layer.

two openings are made through the oxide layer

Step7: From the openings made through oxide layer n-type impurities are diffused to form n-
wells

n-type impurities are diffused to form n-wells

Step8: Three openings are made through the oxide layer to form three active devices.

Three openings are made through the oxide layer to form three active devices
 Step9: The gate terminals of NMOS and PMOS are formed by covering and patterning the
entire surface with Thinox and Polysilicon.

The gate terminals of NMOS and PMOS are formed with Thinox and Polysilicon

Step10: The P-impurities are added to form the base terminal of BJT and similar, N-type
impurities are heavily doped to form emitter terminal of BJT, source and drain of NMOS and
for contact purpose N-type impurities are doped into the N-well collector.

P-impurities are added to form the base terminal of BJT

Step11: To form source and drain regions of PMOS and to make contact in P-base region the
P-type impurities are heavily doped.

P-type impurities are heavily doped to form source and drain regions of PMOS

Step12: Then the entire surface is covered with the thick oxide layer.

Entire surface is covered with the thick oxide layer

Step13: Through the thick oxide layer the cuts are patterned to form the metal contacts.

The cuts are patterned to form the metal contacts

Step14: The metal contacts are made through the cuts made on oxide layer and the terminals
are named as shown in the below figure.
 Metal contacts are made through the cuts and terminals are named

The fabrication of BICMOS is shown in the above figure with a combination of NMOS,
PMOS and BJT. In the fabrication process some layers are used such as channel stop implant,
thick layer oxidation and guard rings. The fabrication will be theoretically difficult for
including both the technologies CMOS and bipolar. Parasitical bipolar transistors are produced
inadvertently is a problem of fabrication while processing p-well and n-well CMOS. For the
fabrication of BiCMOS many additional steps added for fine tuning of bipolar and CMOS
components. Hence, the cost of total fabrication increases. Channel stopper is implanted in
semiconductor devices as shown in the above figure by using implantation or diffusion or other
methods in order to limit the spreading of channel area or to avoid the formation of parasitic
channels. The high impedance nodes if any, may cause the surface leakage currents and to
avoid the flow of current in places where the current flow is restricted these guard rings are
used.