UNIT-I

Introduction: Basic steps of IC fabrication, PMOS, NMOS, CMOS

&BiCMOS, SOI process technologies, MOS transistors - MOS transistor
switches – Basic gate using switches, working polar transistor Resistors
and Capacitors.
Basic Electrical Properties of MOS and BiCMOS Circuits: Working
of MOS transistors – threshold voltage; MOS design equations: Ids–Vds
relationships, Threshold Voltage, Body effect, Channel length modulation
, gm, gds, figure of merit ω0; Pass transistor, NMOS Inverter, CMOS
Inverter analysis and design, Various pull ups loads, Bi-CMOS Inverters.
TEXT BOOKS:
1. Kamran Eshraghian, Eshraghian Douglas and A. Pucknell, “Essentials
of VLSI circuits andsystems”, PHI, 2013 Edition.
2. K.Lal Kishore and V.S.V. Prabhakar, “VLSI Design”, IK Publishers
What is IC ?
An integrated circuits (IC) sometimes called a chip or microchip is a
semiconductor wafer on which thousands or millions of tiny
resistor,capacitors and transistors are fabricated.

An IC can function as an oscillator ,amplifier,timers,

Computer memory or microprocessor.

An IC is categorized as either linear(analog) or discrete(digital)

Depending on its intended applications.
Why the Integrated circuit ?

• Integration improves
• size
• speed
• power
• Integration reduce manufacturing costs
 History

• The integrated circuit or IC was put forth by Jack Kilby

at Texas Instruments
 EVALUATION of IC’S

• SSI – Small Scale Integration( 1960)(10-100)

contained 1 – 10 ------- logic gates
• MSI – Medium Scale Integration (1970 )(100-1000)
logic functions, counters
• LSI – Large Scale Integration ( 1980 )(1000-10000)
first microprocessors on the chip
• VLSI – Very Large Scale Integration (1995) (10000-1000000)
• 64-bit microprocessors,
complete with cache memory
 Moore's law

• In the year 1965 Gordon Moore Intel Co-Founder and Chairman

predicted that transistors would continue to shrink , allowing :
Doubled transistors density every 18-24 months
Doubled performance every 18-24 months
The period often quoted as "18 months
 Power Dissipation
100

P6
Pentium ® proc

Power (Watts)
10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Lead Microprocessors power continues to increase

 IC -Technologies

• Bipolar technology
– TTL (transistor-transistor logic)

– ECL (emitter-coupled logic)

• MOS (Metal-oxide-silicon)

– nMOS (n-channel MOS)

– pMOS (p-channel MOS)
– CMOS
• Bi CMOS technology
• GaAs - Gallium Arsenide (for high speed)

• Si-Ge - Silicon Germanium (for RF)

Basic steps of IC fabrication
The manufacturing of Integrated Circuits(IC) consists of following steps
1.Wafer production
2.Expitaxial growth
3. Etching
4. Masking
5.Doping
6.Atomic diffusion
7.Ion implantation
8.Metallization
9.Assambely and packaging
Wafer production
• The first step is wafer production.
• The wafer is round slice of semiconductor material such as silicon. Silicon is preferred due to its
characteristics.it is more suitable for manufacturing IC.
• It is base or substrate to entire chip.
• First purified polycrystalline silicon is created from the sand. Then it is heated to produce molten liquid.
• A small piece of solid silicon is dipped on the molten liquid.
• Then the solid silicon (seed) is slowly pulled from the melt. The liquid cools to form single crystal ingot.
• A thin round wafer of silicon is cut using wafer slicer. Wafer slicer is a precise cutting machine and each
slice having thickness about 0.01 to 0.025inches.
• When wafer is sliced, the surface will be damaged. It can be smoothening by polishing. After polishing
the wafer, it must thoroughly clean and dried.
• The wafers are cleaned using high purity low particle chemicals .The silicon wafers are exposed to ultra
pure oxygen.
Epitaxial growth

• It means the growing of single silicon crystal upon original silicon

substrate.
• A uniform layer of silicon dioxide is formed on the surface of wafer.
Etching

• Selectively removing unwanted material from the surface of the

wafer.
• The pattern of the photo-resist is transferred to the wafer by means
of etching agents.
• The parts of material are protected by this etching mask.
Masking
• To protect some area of wafer when working on another area, a
process called photolithography is used.
• The process of photolithography includes masking with a
photographic mask and photo etching.
• A photoresist film is applied on the wafer.
• The wafer is aligned to a mask using photo aligner.
• Then it is exposed to ultraviolet light through mask.
• Before that the wafer must be aligned with the mask.
Doping
• To alter the electrical character of silicon, atom with one less electron
than silicon such as boron and atom with one electron greater then
silicon such as phosphorous are introduced into the area.
• The P-type (boron) and N-type (phosphorous) are created to reflect
their conducting characteristics.
Atomic diffusion

• Diffusion is defined as the movement of impurity atoms in

semiconductor material at high temperature.
• Then the wafers are heated at a temperature of about 1500-2200°F.
The inert gas carries the dopant chemical. The dopant and gas is
passed through the wafers and finally the dopant will get deposited
on the wafer.
• This method can only be used for large areas. For small areas it will be
difficult and it may not be accurate.
Ion implantation
• Ion implantation is a low-temperature process by which ions of one
element are accelerated into a solid target, thereby changing the
physical, chemical, or electrical properties of the target.
• Ion implantation is used in semiconductor device fabrication and in
metal finishing, as well as in materials science research.
• The ions can alter the elemental composition of the target (if the ions
differ in composition from the target) if they stop and remain in the
target.
• Ion implantation also causes chemical and physical changes when the
ions impinge on the target at high energy.
Metallization
• It is used to create contact with silicon and to make interconnections
on chip.
• A thin layer of aluminum is deposited over the whole wafer.
• Aluminium is selected because it is a good conductor, has good
mechanical bond with silicon, forms low resistance contact and it can
be applied and patterned with single deposition and etching process.
Assambely and packaging
• Each of the wafers contains hundreds of chips. These chips are
separated and packaged by a method called scribing and cleaving.
• The wafer is similar to a piece of glass. A diamond saw cut the wafer
into single chips.
• The diamond tipped tool is used to cut the lines through the
rectangular grid which separates the individual chips.
• The chips that are failed in electrical test are discarded.
• Before packaging, remaining chips are observed under microscope.
The good chip is then mounted into a package.
MOSFET
• The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a
semiconductor device which is widely used for switching and
amplifying electronic signals in the electronic devices.
• The MOSFET is a four terminal device with source(S), gate (G), drain
(D) and body (B) (or) Substrate(Su) terminals.
Types of MOSFET Devices

The MOSFET is classified into two types such as;

• Depletion mode MOSFET
• Enhancement mode MOSFET
Enhancement Mode:

• When there is no voltage on the gate terminal the device does not
conduct. More voltage applied on the gate terminal, the device has
good conductivity.
Depletion Mode:
• When there is zero voltage on the gate terminal, the channel shows
its maximum conductance. As the voltage on the gate is negative or
positive, then decreases the channel conductivity.
Symbols representing NMOS &
PMOS
NMOS FABRICATION
Representation of elements
NMOS Fabrication Steps
• There are a huge number of fundamental fabrication steps utilized as a part of the generation of
present-day MOS ICs.
• A similar procedure can be utilized for the planned of NMOS or PMOS or CMOS devices. The
most commonly used material could be either metal or poly-silicon.
STEP 1:-
• A thin layer of silicon wafer is convernted into p type material by doping with Boran material.
STEP 2:-
• A thick of layer of silicon dioxide(sio2) is grown on entire p-type
substrate
STEP 3:-
• The surface is now covered with a photoresist which is deposited over
the thick layer of sio2.
Step 4:-
• The photoresist layer is then exposed to ultraviolet light through a
mask which defines those regions into which diffusion is to take place
together with transistor channels.
Step 5:-
• These areas are etched away together with the underlying
silicondioxide so that the wafer surface is exposed in the window
defined by the mask.
 Step 6:-
• The remaining photoresist is removed and a thin layer of Si02 (0.1
micro meter typical) is grown over the entire chip surface and then
polysilicon is deposited on top of this to form the gate structure.
• A photoresist is deposited over the entire the polysilicon layer and
expose UV light through the mask2
Step 7:-
• Diffusionis achieved by heating the wafer to a high temperature and
passing a gas containing the desired n-type impurity (for example,
phosphorus)
Note: The polysilicon has an underlying thin oxide which acts as a
mask during diffusion. This is called self-aligning.
Step 8 :-
• A Thick oxide (Si02) of 1(micro meter) thickness is grown over all and
photoresist material is placed on it.
• Expose the UV light through mask-3 on the selected areas of the
polysilicon gate ,drain and source areas are etched to create the
contact cuts.
Step 9 :-
• Now a metal(aluminium) is deposited over its surface of 1(micro
meter) thickness.
• Again a photo resist material is grown all over the metal and Expose
the UV light through mask-4 are etched to from the required
interconnection pattern.
• The final NMOS structure is
PMOS FABRICATION
STEP 1:-
• A thin layer of silicon wafer is convernted into N-type material by doping with
Phosphorous material.
STEP 2:-
• A thick of layer of silicon dioxide(sio2) is grown on entire p-type substrate.
STEP 3:-
• The surface is now covered with a photoresist which is deposited over the thick
layer of sio2.
Step 4:-
• The photoresist layer is then exposed to ultraviolet light through a mask which
defines those regions into which diffusion is to take place together with transistor
channels.
Step 5:-
• These areas are etched away together with the underlying silicondioxide so that
the wafer surface is exposed in the window defined by the mask.
Step 6:-
• The remaining photoresist is removed and a thin layer of Si02 (0.1 micro meter
typical) is grown over the entire chip surface and then polysilicon is deposited on
top of this to form the gate structure.
• A photoresist is deposited over the entire the polysilicon layer and expose UV
light through the mask2
Step 7:-
• Diffusionis achieved by heating the wafer to a high temperature and passing a gas containing the
desired P-type impurity (for example, Boran).
Note: The polysilicon has an underlying thin oxide which acts as a mask during diffusion. This is
called self-aligning.
Step 8:-
• A Thick oxide (Si02) of 1(micro meter) thickness is grown over all and photoresist material is
placed on it.
• Expose the UV light through mask-3 on the selected areas of the polysilicon gate ,drain and
source areas are etched to create the contact cuts.
Step 9:-
• Now a metal(aluminium) is deposited over its surface of 1(micro meter) thickness.
• Again a photo resist material is grown all over the metal and Expose the UV light through mask-4
are etched to from the required interconnection pattern.
• The final structure of the PMOS
 CMOS FABRICATION
• CMOS is acronym as the COMPLEMENTARY METAL OXIDE SEMICONDUCTOR was first
proposed by wanlass and sah in 1963.
• CMOS process is more complex than the NMOS process , it provides both n-
channel (NMOS) and p-channel(PMOS) transistors on the same chip.
• CMOS circuits can achieve low power consumption and high noise immunity.
• The CMOS can be fabricated using different processes such as
1. P-well technologies
2. N-well technologies
3. Twin well / Tub technology
4. Silicon On Insulator (SOI)
P-WELL TECHNOLOGIES
Step1:-
Step2 :-
Step 3:-
Step 4:-
Final structure of the P-Well
N-WELL TECHNOLOGIES
Step1:-
Step 2:-
Step 3:-
Step 4:-
• The final structure of the N-WELL
Flow chart for N-WELL construction
Twin tub/well technology
• A logical extension of the p-well and n-well approaches is the twin-
tub fabrication process.
• Provide separate optimization of the n-type and p-type transistors.
• Making it possible for threshold voltage , body effect and the gain
associated with n and p devices to be independently optimized.
Steps:-
1. N or P type substrate is taken initially.
2. Lightly doped Epitaxial layer is deposited above N or P type substrate.
i. Electrical properties of these is fixed by dopant and its
concentration
ii. The main aim of these step is to deposit high purity silicon layer.
3.N-well formation.
i. A thick layer of sio2 is grown over the substrate and photo resist is
grown over it.
ii. Apply the masking procedure where the N - well is created
iii. And etching process is involved to remove a thick layer of sio2
where it requires the N- Well.
iv. And ion implantation is occurred with phosphorous element to
create the the N-Well.
4. P-Well Formation.
i. A thick layer of sio2 is grown over the substrate and photo resist is
grown over it.
ii. Apply the masking procedure where the P - well is created
iii. And etching process is involved to remove a thick layer of sio2
where it requires the P- Well.
iv. And ion implantation is occurred with Boran element to
create the the P-Well.
5. A thin layer of sio2 is deposited over it .
6. A polysilicon material is grown all over the surface.
7. Polysilicon gates are formed for N-well and P-well by using the
masking procedure.
8. N diffusion formed is formed in N-well and P diffusion is formed in P-
well
9. Metallization process is done to create the interconnection at
G,S,D,SUB, of P-well and N-well.
Note:-
1. Balanced performance of n and p devices can be constructed.
2. This is particularly important as far as latch-up is concerned.
BiCMOS:-
• BiCMOS technology is a combination of Bipolar and
CMOS technology.
• CMOStechnology offers less power dissipation, smaller noise
margins, and higher packing density.
• Bipolar technology, on the other hand, ensures high switching and
I/O speed
• The BiCMOS fabrication combines the process of fabrication of BJT
and CMOS.
Step1:
P-Substrate is taken as shown in the below figure
Step2: The p-substrate is covered with the oxide layer

Step3: A small opening is made on the oxide layer

Step4: N-type impurities are heavily doped through the opening

Step5: The P – Epitaxy layer is grown on the entire surface

Step6: Again, entire layer is covered with the oxide layer and two
openings are made through this oxide layer.
Step7: From the openings made through oxide layer n-type impurities
are diffused to form n-well.
Step8:
Third openings are made through the oxide layer to form three
active devices.
Step9:
The gate terminals of NMOS and PMOS are formed by covering and
patterning the entire surface with Thinox and Polysilicon.
Step10:
The P-impurities are added to form the base terminal of BJT and similar, N-type impurities are
heavily doped to form emitter terminal of BJT.
. source and drain of NMOS and for contact purpose N-type impurities are doped into the N-well
collector.
• Step11: To form source and drain regions of PMOS and to make
contact in P-base region the P-type impurities are heavily doped.
Step 12:-Then the entire surface is covered with the thick oxide layer.
Step13: Through the thick oxide layer the cuts are patterned to form
the metal contacts.
Step14: The metal contacts are made through the cuts made on oxide
layer and the terminals are named as shown in below figure.
Advantages of BiCMOS
technology
• It has the advantage of improved speed performance compared to
CMOS technology alone.
• It has low power dissipation than bipolar technology alone
• It is well appropriate for input/ouput intensive applications
Drawbacks of BiCMOS
technology
• The fabrication process of this technology is comprised of both the
CMOS and bipolar technologies increasing the complexity
• Due to increase in the complexity of the fabrication process, the cost
of fabrication also increases
BiCMOS technology and
Applications
• This technology is well suited for the intensive input/output
applications.
• This is also used in applications such as adders, mixers, ADC and DAC
• In some applications the BiCMOS speed performance is better than
the that of bipolar.
• This technology excels its applications, mainly in two areas of
microprocessors such as memory and input/output.
• The applications of BiCMOS were initially in RISC microprocessors
rather than traditional CISC microprocessors.
SOI process technologies
• Silicon-on-Insulator (SOI) has been under active consideration for the
last many years.
• SOI refers to placing a thin layer of silicon on top of an insulator such
as silicon oxide or glass.
• The transistors will be built on top of this thin layer of SOI.
• The first implementation of SOI was announced by IBM in August
1998. Rather than using silicon as the substrate, the technologies
have sought to use an insulating substrate to improve process
characteristics such as latchup and speed.
The steps used in typical SOI CMOS process are as follows
Step1:-
A thin film (7-8 µm) of very lightly –doped n-type Si is grown over an
insulator, Sapphire(Aluminium Oxide – AI2O3) or SiO2 is commonly
used insuator.
Step 2:-
• Etching technique is used to away the silicon except where a diffusion
area will be needed.
Step 3:-
• The p-islands are formed next by masking the n-islands with a
photoresist.
• A p-type dopant, boron, for example is then implanted. The p-islands
will serve as the n-channel devices.
Step 4:-
• The p-islands are then covered with a photoresist and an n-type
dopant phosphorus, for example is implanted to form the n-islands.
The n-islands will serve as the p-channel devices.
Step 5:-
• A thin gate oxide is grown over all of the Si- Substrate structure .This
is normally done by the thermal oxidation.
• Then Polysilicon film is deposited over the oxide.
Step 6:-
• The polysilicon is then patterned by photomasking and is etched. This
defines the polysilicon layer in the structure.
Step 7:-
• The next step is to form the n-doped source and drain of the n-
channel devices in the p-islands.
• The n-islands are covered with a photoresist and an n-type dopant,
normally phosphorus is implanted.
Step 8:-
• The p-channel devices are formed next by masking the p-islands and
implanting a p-type dopant such as boron.
Step 9:-
• A layer of phosphorus glass or some other insulator such as silicon dioxide is then deposited over
the entire structure.
• The glass is etched as contact –cut locations. The metallization layer is formed using aluminum
over the entire surface and etching it to leave only the desired metal wires.
• The aluminium will flow through the contact cuts to make contact with the diffusion or polysilicon
regions.
Advantages of SOI technology
• Due to absence of wells, transistor structures denser.
• Lower substrate capacitances provide the possibility for faster circuits
• There is no latch up problems.
• Because there is no conducting substrate, there are no body-effect
problems
Disadvantage of SOI technology
• Single crystal sapphire Al203, SiO2 are considerably more expensive
than silicon substrate and their processing techniques tend to be less
developed than bulk silicon techniques.
• Due to absence of substrate diodes, the inputs are somewhat more
difficult to protect.
S.no CMOS . technology Bipolar technology
1. Low static power dissipation High power dissipation
2 High input impedance Low input impedance
3 High packing density Low packing density
4 Low output drive current High output drive current
5 Bidirectional capability Essentially unidirectional
MOS Transistor

• MOS Transistor transistor is simple and best understood by looking at

its structure.
A MOS transistor is primarily a switch for digital devices. Ideally, it
works as follows:
If the voltage at the gate electrode is "on" , the transistor is "on", too,
and current flow between the source and drain electrodes is possible
(almost) without losses.
If the voltage at the gate electrode is "off", the transistor is "off", too,
and no current flows between the source and drain electrode.
• Metal Oxide Semiconductor Field Effect Transistors are Four terminal active devices made from
different semiconductor materials that can act as either an insulator or a conductor by the
application of a small signal voltage.
• The MOSFETs ability to change between these two states enables it to have two basic functions:
“switching” (digital electronics) or “amplification” (analog electronics). Then MOSFETs have the
ability to operate within three different regions:
1. Cut-off Region.
2. Linear Region
3. Saturation Region
1. Cut-off Region – with VGS < Vthreshold the gate-source voltage is much
lower than the transistors threshold voltage so the MOSFET transistor is
switched “fully-OFF” thus, ID = 0, with the transistor acting like an open
switch regardless of the value of VDS.
2. Linear (Ohmic) Region – with VGS > Vthreshold and VDS < VGS the transistor
is in its constant resistance region behaving as a voltage-controlled
resistance whose resistive value is determined by the gate voltage, VGS level.
3. Saturation Region – with VGS > Vthreshold and VDS > VGS the transistor is in
its constant current region and is therefore “fully-ON”. The Drain
current ID = Maximum with the transistor acting as a closed switch.
Types of MOSFETS
• n-channel Enhancement Mode (nMOSFET)
• p-channel Enhancement Mode (pMOSFET)
• n-channel Depletion Mode (nMOSFET)
• p-channel Depletion Mode (pMOSFET)
Enhancement mode:-
• Also known as Normally Off transistors.
• A voltage must be applied to the gate of the transistor, at least equal to the threshold voltage, to
create a conduction path between the source and the drain of the transistor before current can
flow between the source and drain.

Depletion mode :-
• Also known as Normally On transistors
• A voltage must be applied to the gate of the transistor, at least equal to the threshold voltage, to
destroy a conduction path between the source and the drain of the transistor to prevent current
from flowing between the source and drain.
NMOS Transistor
It is a Four terminals devices: gate, source, drain, body
• Gate and body are conductors – SiO2 (oxide) is a very good insulator
NMOS Operation
• Body is commonly tied to ground (0 V)
• When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
• When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from source through
channel to drain, transistor is ON
PMOS Transistor
• Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behaviour.
Power Supply Voltage
• GND = 0 V
• In 1980’s, VDD = 5V
• VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
• VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
MOS transistor switches
• We can view MOS transistors as electrically controlled switches.
• Voltage at gate controls path from source to drain.
NMOS SWITCH
PMOS SWITCH
Transmission Gates:-
Transmission gates can be constructed by parallel combination of PMOS
and NMOS.
• The common circuit symbol for a transmission gate as shown
Basic Operation of transmission
gates:-
When the voltage on node A is a Logic 1, the complementary Logic 0 is
applied to node active-low A, allowing both transistors to conduct and
pass the signal at IN to OUT.
When the voltage on node A is a Logic 0, the complementary Logic 1 is
applied to node active-low A, turning both transistors off and does not
pass the signal at IN to OUT.
Advantages and Disadvantages
of Transmission Gates
Advantages:
• Complex gates can be implemented using minimum number of
transistors, which also reduces parasitics
• The combination of both an PMOS and NMOS in Transmission Gate
arrangement avoids the problem of reduced noise margin.
Disadvantage:
• Time-skew problems can lead to short circuits paths.
• Slower speed.
Basic gates using Switches:-
• Implementation of Basic logic gates and other structures using
CMOS,NMOS & PMOS technology.
• The required Basic element is transistor to implenment the function
of the logic gates.
• And two types of transistors:
• n-channel (nMOS) and p-channel (pMOS)
• Use switches to create networks that represent CMOS logic circuits.
PULLUP & PULLDOWN:-
• Pullup - A network that provides a low resistance path to Vdd when
input is logic ‘0' and provides a high resistance to Vdd when input is
logic ‘1'.
• Pulldown - A network that provides a low resistance path to Gnd
when input is logic ‘1' and provides a high resistance to Gnd when
input is logic ‘0'.
• Two basic structures :
o Transistors in Series
o Transistors in Parallel
In general:
1. nMOS in series is used to implement AND logic
2. nMOS in parallel is used to implement OR logic
3. pMOS in series is used to implement NOR logic
4. pMOS in parallel is used to implement NAND logic
working polar transistor Resistors

• When the VGS < Vth then it is in a cut-off mode,It means that now
the MOSFET is acting as a open-load with infinite resistance.
• When you slowly increase the gate voltage the MOSFET slowly starts
conducting by entering the linear region where it starts developing
voltage across it which we call as VDS . In this region, the MOSFET
acts as a resistance of finite value.
• Now when the MOSFET enters the saturation region, the resistance of
the MOSFET is the least and is equal to the RDS(on) of the MOSFET.
 working polar transistor Capacitors
• An MOS capacitor is made of a semiconductor body or substrate, an
insulator film, such as SiO2, and a metal electrode called a gate.
• The structure looks like a parallel plate capacitor where one of the
plates is the semiconductor and the other is the gate metallization. The
insulator between the parallel plates is the oxide
• The parallel plate capacitor consists of two parallel metallic plates of
area A, separated by an insulator of thickness d and dielectric constant.
• If we place a charge Q on the upper plate, it attracts charges of
opposite sign in the bottom plate, while repelling charges of the same
sign. If the bottom plate is connected to ground, the repelled charge
flows to ground. Now the two capacitor plates hold equal and opposite
charge.
Threshold voltage:-

• The threshold voltage, commonly abbreviated as Vth i.e the

minimum gate-to-source voltage VGS is required to create a
conducting path between the source and drain terminals.
• The minimum voltage required to ON the transistor is
called Threshold voltage. It is observed as positive value for NMOS
transistor and negative value for PMOS transistor.
• The vGS required to accumulate sufficient numbers of mobile electrons
in the channel is called the threshold voltage Vt. For an n-channel
MOSFET, Vt ≈1 −3 V (note that this is a positive voltage).
• The threshold voltage V, may be expressed as:

where

QB = the charge per unit area in the depletion layer beneath the oxide
QSS = charge density at Si:Si02 interface
C0 = capacitance per unit gate area
= work function difference between gate and Si
= Fermi level potential between inverted surface and bulk Si.
• To evaluate Vt , each term is determined as follows:

VSB = substrate bias voltage (negative w.r.t. source for nMOS, positive for pMOS)
= relative permittivity of silicon
N = impurity concentration in the substrate
ni = intrinsic electron concentration
K = Boltzmenn’s constant
q = 1.6 x10-19 coulomb
Body Effect:-
• Body effect refers to the change in the transistor threshold voltage (Vth) resulting from a voltage
difference between the transistor source and body.
• Because the voltage difference between the source and body affects the VT, the body can be
thought of as a second gate that helps determine how the transistor turns on and off.
• It is also knows as Back gate effect.
Vt Vt 0    s  Vsb  s 
fs = surface potential at threshold

g = body effect coefficient

tox 2q si N A
  2q si N A 
 ox C ox
Channel Length Modulation:-
• Channel Length modulation can be defined as the reduction in the
length of the channel (L) due to increases in the drain to source
voltage (Vds) in the saturation region.
Transconductance

• Transconductance is the ratio of the change in drain to Source

current to the change in gate to source voltage over a small interval
on the drain-current-versus-gate-voltage curve.
• The symbol for transconductance is gm
• The unit is the siemens, Symbol: S (= Ω−1) mho
Outputconductance:- (gd)
• Outputconductance is the ratio of the change in drain to source
current to the change in drain to source voltage.
• The symbol for transconductance is gd. And it can be expressed as
Figure of merit :- ( ωo)
A figure of merit is a quantity used to characterize
the performance of a device ,system or method
relative to its alternatives.
An indication of frequency response may be
obtained from the parameter ωo where
• This shows that switching speed depends on
1. gate voltage above threshold
2.carrier mobility
3.inversely as the square of channel length

Note:-
A fast circuit requires that gm be as high as possible.
Pass Transistor
• MOSFETs can be used as switches in series with lines carrying logic
levels as in the case of relay contacts. Such kind of logic is known as
pass transistor.
• Pass transistor pass the signal between the drain and source
terminals.
• They require less area and wiring and cannot pass the entire voltage
range.
• NMOS is preferred for these application since the larger electron
mobility implies faster switching than the PMOS.
Logic gates using pass transistor logic :
NMOS INVERTER:-
• The basic inverter circuit requires a transistor with source connected
to ground and aload resistor of some sort connected from the drain to
the positive supply rail VDD· The output is taken from the drain and the
input applied between gate and ground.
• Resistors are not conveniently produced on the silicon substrate; even
modest values occupy excessively large areas so that some other form
of load resistance is required.
• A convenient way to solve this problem is to use a depletion mode
transistor as the load, as show in the figure
• In this configuration the depletion mode device is called the pull-up (p.u.) and the
enhancement mode device the pull-down (p.d.) transistor.
• When Vin = logic 0 the Pull Down transistor is off and VDD appears near the V
OUT i.e
Vout =Logic 1.
• When Vin = logic 1 the pull down transistor is ON and the Vout
=Logic 0.
• To obtain the inverter transfer characteristic we superimpose the Vgs
= 0 depletion mode characteristic curve on the family of curves for
the enhancement mode device, noting that maximum voltage across
the enhancement mode device corresponds to minimum voltage
across the depletion mode transistor.
 • The points of intersection of the curves as in give points on the
transfer characteristic, which is of the form shown

The point at which Vout = Vi;, is denoted as

Vinv and it will be noted that the transfer
characteristics and Vinv can be shifted by
variation of the ratio of pull-up to pulldown
resistances (denoted zp.u/Zp.d. where Z is
determined by the length to width ratio of
the transistor ).
Determination of Pull up to Pull Down
Ratio(Zpu/Zpd) for an NMOS inverter driven
by another invereter.
• Consider the arrangement in which an inverter is driven from the
output of another similar inverter.
• In order to cascade the inverter without degradation of the voltage
levels,the required conditions is
PULL-UP TO PULL-DOWN RATIO FOR AN nMOS
INVERTER
DRIVEN THROUGH ONE OR MORE PASS TRANSISTORS
• Now consider the arrangement in which the input to inverter 2 comes
from the output of inverter 1 but passes through one or more nMOS
transistors used as switches in series (called pass transistors).
• Consider inverter 2 when input = VDD- Vtp. As for inverter 1
• Note:-
• • An inverter driven directly from the output of another should have a
Zp.ulZp.d. Ratio of ≥4/1.
• An inverter driven through one or more pass transistors should have
a Zp.u./Zp.d. ratio of≥ 8/1.
BiCMOS Inverter
• As in nMOS and CMOS logic circuitry, the basic logic element is the
inverter circuit.
• When designing with BiCMOS in mind, the logical approach is to use

1.MOS switches to perform the logic function and

2.transistors to drive the output loads.
A simple BiCMOS inverter as shown in figure .
It consists of two bipolar transistors T1 and T2 with
one nMOS transistor T3, and one pMOS transistor T4.
If Vin =0 Volts
T3=OFF so T1 will be non-conducting
T4 = ON so supplies current to base of T2 which
will conduct and act as a current source to
charge the load CL towards +5 Volts.
If Vin =+5 Volts
T4=OFF so T2 will be non-conducting
T3= ON so supplies currewnt to base of T1 which
will conduct and act as current sink to the load
CL discharge it towards ‘0’.
• CL will be charged or discharged rapidly.
• The output logic levels will be good.
• The inverter has a high input impedance.
• The inverter has a low output impedance.
• The inverter has a high current drive capability
• The inverter has high noise margins.
Draw back:-
• There is a DC path between VDD and GND through T3 and T1. Due to
these there will significant static current flow when Vin = Logic 1.
• When Vin = VDD , T4= OFF and no conducting path to the base of T2
Vin= 0, T3=OFF and no conducting path to the base of T1
So it will slow down the action of the circuit.
 An improved version of
BiCMOS:-

An improved version of this circuit is

given in which the DC path through
T3 and T1 is eliminated, but the
output voltage swing is now
reduced, since the output cannot fall
below the base to emitter voltage
VBE of T1
An improved version of
BiCMOS:-
• An improved version arrangement is taken
by using resistors, is shown in Figure .
• In this circuit resistors provide the
improved swing of output voltage when
each bipolar transistor is off, and also
provide discharge paths for base current
during turn-off.
• Due to presence of the resistor in the
circuit it is inconvenient because it take
more amount of area.
 An improved version of
BiCMOS:-
In this circuit, the transistors T5 and T6 are
arranged to turn on when T2 and T1
respectively are being turned off.
In general, BiCMOS inverters offer many
advantages where high load current sinking and
sourcing is required. The arrangements lead on
to the BiCMOS gate circuits
 LATCH UP
Latch-up is a condition in which the
parasitic components give rise to the
establishment of low-resistance conducting
paths between VDD and VSS with disastrous
results. Careful control during fabrication is
necessary to avoid this problem.

One benefit of the BiCMOS process is that it

produces circuits which are less to suffer from
latch-up problems.
This is due to several factors:-
1.A reduction of substrate resistance Rs.
2. A reduction of n-well resistance Rw.
CMOS INVERTER
• An inverter circuit converts
a logic high-input such as
1 V to a low logic voltage of 0 V
and
a logic low-input such as
0 V to a high logic Voltage of 1 V
• The Boolean statement
Vout = Vin
• In CMOS technology, both N-type and P-type transistors are used to
design logic functions.
• In CMOS logic gates a collection of n-type MOSFETs is arranged in a
pull-down network between the output and the low voltage power
supply rail (Vss or quite often ground).
• CMOS logic gates have a collection of p-type MOSFETs in a pull-up
network between the output and the higher-voltage rail (often named
Vdd).
 In,p
V in = 0 Vin = 5

NMOS
PMOS

Vin = 4 Vin = 1 Vin = 4

Vin = 3 Vin = 2 Vin = 3 Vin = 2

Vin = 4 Vi n = 1
V in = 3 Vin = 2
Vin = 0
Vin = 5
Transfer Characteristics of CMOS
Inverter
Ids versus Vds RELATIONSHIPS

• The voltage on Gate induces a charge in the channel between Source

and Drain .Which is then moved from source to drain under the
influence of electric field created by voltage applied between Drain
and Source VDS . Hence the current IDS is given by
Let

L- is the channel length of the transistor.

W- is the width of the transistor.

D- is the thickness of the oxide layer.
ε - is the permittivity of the oxide layer.
IDS .- Drain to source current
VDS .- Drain to source voltage

Q – Charge induced in the channel

τ - the electron transit time

The expressions derived for Ids hold for both enhancement and
depletion mode devices, but it should be noted that the threshold
voltage for the nMOS depletion mode device (denoted as Vtd) is
negative.
Problems:-
1) An nMOS transistor is operates in the triode region with the
following parameters VGS= 4V, VTN= 1V , VDS=2V ,W/L=100,µnCox=90µA/V
find its drain current and drain source resistance.