5.

CMOS Gate Characteristics

Jacob Abraham

Department of Electrical and Computer Engineering

The University of Texas at Austin
VLSI Design
Fall 2020

September 10, 2020

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 1 / 39
 Topics

DC Response
Logic Levels and Noise Margins
Transient Response
Delay Estimation

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 1 / 39
 Review – Delay of an Inverter
Inverter is driving another identical inverter; delay is the time when
the input changes to when the output changes. Note that the
second inverter is just serving as a load for the first.
Simplifying assumptions
Resistance of a unit transistor = R
Gate capacitance of a unit transistor = C
Source/drain capaticance of a unit transistor = C

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 2 / 39
 Inverter Delay Estimate, Cont’d
Estimate the delay of an inverter driving 4 identical inverters –
Fanout-of-4 (FO4) delay
An important abstraction at higher levels of the design

d = 15RC
ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 3 / 39
 Transistor Behavior

Behavior in different situations (increase, decrease, or not

change).
1 If the width of a transistor increases, the current will
2 If the length of a transistor increases, the current will
3 If the supply voltage of a chip increases, the maximum
transistor current will
4 If the width of a transistor increases, its gate capacitance will
5 If the length of a transistor increases, its gate capacitance will
6 If the supply voltage of a chip increases, the gate capacitance
of each transistor will

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 4 / 39
 Transistor Behavior

Behavior in different situations (increase, decrease, or not

change).
1 If the width of a transistor increases, the current will increase
2 If the length of a transistor increases, the current will
decrease
3 If the supply voltage of a chip increases, the maximum
transistor current will increase
4 If the width of a transistor increases, its gate capacitance will
increase
5 If the length of a transistor increases, its gate capacitance will
increase
6 If the supply voltage of a chip increases, the gate capacitance
of each transistor will not change

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 5 / 39
 DC Response: Vout vs. Vin for a Gate

Study the response of Inverters

When Vin = 0 =⇒ Vout = VDD

When Vin = VDD =⇒ Vout = 0
In between, Vout depends on
transistor size and current
By KCL, current must be such that
Idsn = |Idsp |
We could solve equations, but
graphical solution gives more
insight

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 6 / 39
 Transistor Operation

Current through transistor depends on the region of operation

Need to identify for what Vin and Vout are nMOS and pMOS
in Cutoff, Linear or Saturation

nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn − Vtn Vdsn > Vgsn − Vtn
Vout < Vin − Vtn Vout > Vin − Vtn
Vgsn = Vin
Vdsn = Vout

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 7 / 39
 pMOS Operation

Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp − Vtp Vdsp < Vgsp − Vtp
Vout > Vin − Vtp Vout < Vin − Vtp

Vgsp = Vin − VDD

Vdsp = Vout − VDD
Vtp < 0

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 8 / 39
 I-V Characteristics
Make pMOS wider than nMOS such that βn = βp
β = µCox W
L

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 9 / 39
 Current vs. Vout , Vin

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 10 / 39
 Load Line Analysis

To find the Vout for a given Vin

For a given Vin , plot Idsn , Idsp vs. Vout
Vout must be where |currents| are equal in the graph below

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 11 / 39
 DC Transfer Curve

Transcribe points on to Vin vs. Vout plot

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 12 / 39
 Operating Regions

Revisit transistor operating regions

Region nMOS pMOS

A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 13 / 39
 Beta Ratio

If βp /βn 6= 1,
switching point will
move from VDD /2
Called skewed gate

Analysis of more complex gates

Collapse into equivalent inverter

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 14 / 39
 Noise Margins

How much noise can a gate input see before it does not recognize
the input?

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 Logic Levels
To maximize noise margins
Select logic levels at unity gain point of DC transfer
characteristic

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 16 / 39
 Transient Response

DC analysis gives the Vout if Vin is constant

Transient analysis tells us Vout as Vin changes
Input is usually considered to be a step or ramp (from 0 to
VDD or vice-versa)

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 17 / 39
 Inverter Step Response
Find the step response of an inverter driving a load capacitance

Vin (t) = u(t − t0 )VDD

Vout (t < t0 ) = VDD
dVout (t)
dt = − ICdsn (t)
load


 0 t ≤ t0
β

Idsn (t) =  2 (VDD − V )2 Vout > VDD − Vt
 β VDD − Vt − Vout (t)
Vout (t) Vout < VDD − Vt

2

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 18 / 39
 Delay Definitions
tpdr : rising propagation delay
From input to rising output crossing VDD /2
tpdf : falling propagation delay
From input to falling output crossing VDD /2
tpd : average propagation delay
tpd = (tpdr + tpdf )/2
tr : rise time
From output crossing 0.2 VDD to 0.8 VDD
tf : fall time
From output crossing 0.8 VDD to 0.2 VDD
tcdr : rising contamination delay
Minimum time from input to rising output crossing VDD /2
tcdf : falling contamination delay
Minimum time from input to falling output crossing VDD /2
tcd : average contamination delay
tcd = (tcdr + tcdf )/2
ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 19 / 39
 Simulated Inverter Delay

Solving differential equations by hand too hard

SPICE simulator solves equations numerically
Uses more accurate I-V models too!
But simulations take time to write

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 20 / 39
 Delay Estimation

We would like to be able to easily estimate delay

Not as accurate as simulation
But easier to ask “what if ...”?
The step response usually looks like a first order RC response
with a decaying exponential
Use RC delay models to estimate delay
C = total capacitance on output node
Use effective resistance R
So that tpd = RC
Characterize transistors by finding their effective R
Depends on average current as gate switches

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 21 / 39
 Example: Sizing 3-Input NAND Gate for Equal Rise and
Fall Times

Determine the transistor widths to achieve effective rise and fall

resistances (times) equal to that of a unit inverter R
Annotate the 3-input NAND gate with gate and diffusion
capacitances
ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 22 / 39
 Example 3-Input NAND Gate

Determine the transistor widths to achieve effective rise and fall

resistances (times) equal to that of a unit inverter R
Annotate the 3-input NAND gate with gate and diffusion
capacitances
ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 23 / 39
 Example: Sizing Complex Gate
Size the transistors in the cir-
cuit below so that it has the
same drive strength, in the
worst case, as an inverter that
has PW = 5 and NW = 3.
Use the smallest widths possi-
ble to achieve this ratio.

Note: if there are multiple

paths through a transistor, use
the size for the “worst-case” in-
put combination.

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 24 / 39
 Example: Sizing Complex Gate
Size the transistors in the
circuit below so that it has
the same drive strength, in the
worst case, as an inverter that
has PW = 5 and NW = 3.
Use the smallest widths possi-
ble to achieve this ratio.

This solution does NOT use the

smallest widths
Note: if there are multiple
paths through a transistor, use
the size for the “worst-case” in-
put combination.

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 25 / 39
 Example: Sizing of Complex Gate – Better Solution
Size the transistors in the
circuit below so that it has
the same drive strength, in the
worst case, as an inverter that
has PW = 5 and NW = 3.
Use the smallest widths possi-
ble to achieve this ratio.

Note: if there are multiple

paths through a transistor, use
the size for the “worst-case” in-
put combination.

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 26 / 39
 Elmore Delay
Finding the delay of ladder networks
ON transistors look like resistors
Pullup or pulldown network modeled as RC ladder
Elmore delay of RC ladder
X
tpd = Ri−to−source Ci
nodes i
= R1 C1 + (R1 + R2 )C2 + . . . + (R1 + R2 + . . . + RN )CN

NOTE: Ci includes all the “off-path” capacitance on nodes that

are connected to node i
ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 27 / 39
 Example: Elmore Delay Calculation

Delay from A to X:

Delay from A to Y:

Delay from A to Z:
ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 28 / 39
 Example: Elmore Delay Calculation, Cont’d

Delay from A to X: 40RC

Delay from A to Y: 38RC

Delay from A to Z: 35RC

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 29 / 39
 Example: Delay of 2-Input NAND Using Elmore
Formulation

Estimate rising and falling propagation delays of a 2-input NAND

driving h identical gates

tpdr = (6 + 4h)RC
ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 30 / 39
 Example: Delay of 2-Input NAND Using Elmore
Formulation

Estimate rising and falling propagation delays of a 2-input NAND

driving h identical gates

  
R R R
tpdf = (2C) + (6 + 4h)C +
2 2 2
= (7 + 4h)RC

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 31 / 39
 Example of Elmore Delay Calculation

Calculate the Elmore delay from C to F in the circuit. The widths

of the pass transistors are shown, and the inverters have
minimum-sized transistors

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 32 / 39
 Example of Elmore Delay Calculation
Calculate the Elmore delay from C to F in the circuit. The widths
of the pass transistors are shown, and the inverters have
minimum-sized transistors

 
R R R R
Delay = 9C + 5C + + 7C + 3RC = 12.33RC
3 3 3 3
ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 33 / 39
 Another Example: Elmore Delay Calculation
Use the Elmore delay approximation to find the worst-case rise and fall
delays at output F for the following circuit. The gate sizes of the
transistors are shown in the figure. Assume NO sharing of diffusion
regions, and the worst-case conditions for the initial charge on a node.

Input for worst-case rise delay =

Worst-case rise delay =

Input for worst-case fall delay =

Worst-case fall delay =

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 34 / 39
 Delay with Different Input Sequences
Find the delays for the given input
transitions (gate sizes shown in figure)

Assumptions: diffusion capacitance is

equal to the gate capacitance, the
resistance of an nMOS transistor with
unit width is R and the resistance of a
pMOS transistor with width 2 is also R,
and NO sharing of diffusion regions

Off-path capacitances can contribute to

delay, and if a node does not need to be
charged (or discharged), its capacitance
can be ignored

ABCD = 0101 → ABCD = 1101

ABCD = 1111 → ABCD = 0111
ABCD = 1010 → ABCD = 1101
ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 35 / 39
 Delay with Different Input Sequence, Cont’d
Look at the charges on the nodes
at the end of the first input of the
sequence; only the capacitances
of the nodes which would change
with the second vector need to be
considered

ABCD = 0101 →
ABCD = 1101;
Delay = 36RC

ABCD = 1111 →
ABCD = 0111;
Delay = 16RC

ABCD = 1010 →
ABCD = 1101;
Delay = 43RC

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 36 / 39
 Delay Components

Delay has two parts

Parasitic Delay
6 or 7 RC
Independent of Load

Effort Delay
4h RC
Proportional to load capacitance

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 37 / 39
 Contamination Delay

Minimum (Contamination) Delay

Best-case (contamination) delay can be substantially less than
propagation delay
Example, If both inputs fall simultaneously
Important for “hold time” (will see later in the course)

tcdr =
(3 + 2h)RC
ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics Jacob Abraham, September 10, 2020 38 / 39
 Diffusion Capacitance
We assumed contacted diffusion on every source/drain
Good layout minimizes diffusion area
Example, NAND3 layout shares one diffusion contact
Reduces output capacitance by 2C
Merged uncontacted diffusion might help too

These general observations can be used for initial estimates of area

and performance – using tools to extract parasitics will provide
more accurate results for a particular technology
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