VERIFICATION and IMPLEMENTATION OF BASIC LOGIC GATES
AIM:
To implement all the basic logic gates using Verilog simulator.
a) AND
b) OR
c) NOT
d) NOR
e) XOR
f) XNOR
g) NAND
PROGRAM PROPERTIES:
a) Modelsim
b) Laptop / Computer with Windows OS
c) Verilog Program, Logic Diagram, Truth Table
PROCEDURE:
1. Open modelsim
2. File - New - project
3. Give the project name (same name for module)
4. Ensure project location in work folder.
5. Create new file
6. Filename same name
7. File type - verilog
8. Right click filename.v - edit or double click
9. Enter coding
10. Save the file
11. Right click Filename.v
12. Compile - compile all
13. Simulate - start simulation
14. Design tab
15. Work folder
16. Select filename
17. In objects
18. Right click input - add - wave - signals in design
19. In wave - clock
20. Run
LOGIC GATE SYMBOLS TRUTH TABLES
VERILOG CODE
AND GATE OR GATE
module and12(a,b,c); module or12(a,b,d);
input a; input a;
input b; input b;
output c; output d;
assign c = a & b; assign d = a | b;
Endmodule Endmodule
NAND GATE XOR GATE
module nand12(a,b,e); module xor12(a,b,h);
input a; input a;
input b; input b;
output e; output h;
assign e = ~(a & b); assign h = a ^ b;
Endmodule Endmodule
XNOR GATE NOR GATE
module xnor12(a,b,i); module nor12(a,b,f);
input a; input a;
input b; input b;
output i; output f;
assign i = ~(a ^ b); assign f = ~(a | b);
Endmodule Endmodule
NOT GATE
module not12(a,g);
input a;
output g;
assign g = ~a;
Endmodule
AND GATE
OUTPUT WAVEFORM:
OR GATE
OUTPUT WAVEFORM:
NOT GATE
OUTPUT WAVEFORM:
EX-OR GATE
OUTPUT WAVEFORM:
NAND GATE
OUTPUT WAVEFORM
NOR GATE
OUTPUT WAVEFORM
XNOR GATE
OUTPUT WAVEFORM
RESULT:
Thus all the basic logic gates are implemented and verified using Verilog simulator.
