Degree Engineering

A Laboratory Manual for

Digital Fundamentals
(3130704)

[B.E. (Computer Engineering): Semester - 3]

Enrolment No 230180107054
Name NISHIT SAVALIYA
Branch COMPUTER
Academic Term 2023-24
Institute Name GOVERNMENT ENGINERRING
COLLEGE , DAHOD

Directorate of Technical Education, Gandhinagar,

Gujarat
 Government Engineering College Dahod.
Department of Computer Engineering

CERTIFICATE

This is to certify that Mr. NISHIT R. SAVALIYA

Enrollment no. 230180107054 of B.E. Semester - III from Computer

Engineering Department of this Institute (GTU Code: 018) has satisfactorily
completed the Practical / Tutorial work for the subject Digital Fundamentals
(3130704)
for the academic year 2023-24.

Place: ___________

Date: ___________

Signature of Course Faculty

Head of the Department

 Digital Fundamentals (3130704) Sem 3

Rubrics Need
Criteria Marks Good(2) Satisfactory(1)
ID Improvement(0)

Moderate(50-
RB1 Regularity 05 High(>75%) Poor(<50%)
75%)
Problem Apt & Full Limited
Understanding Identification of Identification Very Less
& the of the Identification of the
RB2 05 Problem Problem / Problem /
Implementatio
& Complete Incomplete Very Less
n of the
Solution for Solution for
Solution in Solution for the
the Problem the Problem
Simulator Problem

Correct Partially Correct

Testing of the Incorrect
RB3 05 Solution as Solution for solution for the
Solution
required the Problem problem

RB4 Documentation 03
Excellent Above Average Below Average
Delayed Very few
All questions & questions
RB5 Mock viva test 02
responded answered
partially
correctly
Correctly correct
response

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 Digital Fundamentals (3130704) Sem 3
INDEX

Sr.
Practical Date Grade Sign
no.

1 To implement all basic logic gate and

derived gates in Logisim Simulator.
Solve the given function using appropriate postulate
2 rules
Toand draw logic
implement 8 Xcircuit diagram in
1 Multiplexer of Logisim
each in
15 Logisim Simulator.
Simulator.
a) To
Solve theimplement Boolean
given function usingfunction
K-map F(a,b,c,d) =
and draw logic
3
circuit∑(0,2,5,8,10,14)
diagram of eachwith a multiplexer.
in Logisim Simulator.
16 b) To implement Boolean function F(a,b,c,d) = π
Solve (2,6,11)
the givenwith
function using
a multiplexer.Tabulation
4 MethodTo and draw logic
implement circuit function
Boolean diagram F(a,b,c,d)
of =
each in∑(1,3,4,11,12,13,14,15)
Logisim Simulator. with a multiplexer.

5 17 To Design
implement
5 toBCD to decoder
32 line Excess-3using
Codebasic decoders 9 (as
Convertor in Logisim Simulator.
asked in examination).

6 18 To Design
implement BCDadder
parallel to Gray Code
circuit Convertor
which in
can decrement
Logisim Simulator.
given input value (as asked in examination).

7 To implement Full Adder and Half Adder

Design the
in Logisim
19 circuit diagram which can explain
Simulator
the cascading concept in De-multiplexer.
8 To implement Full Subtractor and Half
Design the
20 Subtractor circuit diagram
in Logisim which can explain the
Simulator.
cascading concept in Multiplexer.
9
21 To Design
implementthe circuit
four bitdiagram
by threewhich can explain
bit binary multiplier.
the utility of MUX-DEMUX.
10
22 To Design
implementthe circuit diagram
BCD Adder to show Simulator.
in Logisim a common
addercum-subtraction.
11 ToExplain
implement Magnitude
the working Comparator
of all in flip flop in
the following
Logisim
LogisimSimulator.
simulator.
a. S-R flip flop
23
12 b. D flip flop
To implement 3 X 8 decoder in Logisim Simulator.
c. J-K flip flop
a. T flip flop
13 To implement 4 X 16 decoder with the help of 3 X
24 8 decoder.
Design master slave flip flop (using every flip flops).
14 Draw Combinational circuit diagram for Full Adder
25 and Full Subtractor using decoder.
Prepare J-K, D and T flip flop using S-R Flip flop.

26
Prepare S-R, D and T flip flop using J-K Flip flop.
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Prepare J-K, S-R and T flip flop using D Flip flop.

28 Prepare J-K, D and S-R flip flop using T Flip flop.

 Digital Fundamentals (3130704) Sem 3
Prepare a sequential circuit diagram to explore
the functionality of given state diagram.

29

Prepare a sequential circuit diagram using D flip flop

of the given state diagram.

30

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 Digital Fundamentals (3130704) Sem 3

Practical 1
AIM: To implement all the basic and derived gates in Logisim
Simulator
Theory:-

Logic Gates

The building blocks of a digital circuit are logic gates, which execute numerous
logical operations that are required by any digital circuit. These can take two or
more inputs but only produce one output. The mix of inputs applied across a logic
gate determines its output. Logic gates use Boolean algebra to execute logical
processes. Logic gates are found in nearly every digital gadget we use on a
regular basis.

Types of Logic Gates

A logic gate is a digital gate that allows data to be transferred. Logic gates, use
logic to determine whether or not to pass a signal. Logic gates, on the other hand,
govern the flow of information based on a set of rules. The following types of
logic gates are commonly used:

1. AND

2. OR

3. NOT

4. NOR

5. NAND

6. XOR

7. XNOR

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Implementation:-

AND Gate
 An AND gate has a single output and two or more inputs.
1. Whenalloftheinputsare1,the output of this gate is 1.
2. The AND gate’s Boolean logic is Y=A.B if there are two inputs A and B.

 An AND gate’s symbol and truth table are as follows:

OR Gate
 Two or more inputs and one output can be used in an OR gate.
1. Thelogicofthisgateisthatifatleastoneoftheinputsis1,the output will be 1.
2. The OR gate’s output will be given by the following
mathematical Procedure if there are two inputs A and B:Y=A+B
 An OR gate’s symbol and truth table are as follows:

NOT Gate
 The NOT gate is a basic one-input, one-output gate.
1. When the input is 1, the output is 0,and vice versa. A NOT gate is
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sometimes called an inverter because of its feature.
2. If there is only one input A, the output may be calculated using
the Boolean equation Y=A’.
 A NOT gate’s symbol and truth table are as follows:

NOR Gate
 A NOR gate, sometimes known as a “NOT-OR” gate, consists of an OR gate
followed by a NOT gate.

1. This gate’s output is 1 only when all of its inputs are 0. Alternatively, when all
of the inputs are low, the output is high.
2. The Boolean statement for the NOR gate is Y=(A+B)’ if there are two inputs A
and B.

 A NOR gate’s symbol and truth table are as follows:

NAND Gate
 A NAND gate, sometimes known as a ‘NOT-AND’ gate, is essentially a Not
gate followed by an AND gate.

1. This gate’s output is 0 only if none of the inputs is 0. Alternatively, when all of the
inputs are not high and at least one is low, the output is high.
2. If there are two inputs A and B, the Boolean expression for the NAND gate is

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Y=(A.B)’

 A NAND gate’s symbol and truth table are as follows:

XOR Gate
1. The Exclusive-OR or ‘Ex-OR’ gate is a digital logic gate that accepts more than
two inputs but only outputs one value.

2. If any of the inputs is ‘High,’ the output of the XOR Gate is ‘High.’ If both inputs
are ‘High,’ the output is ‘Low.’ If both inputs are ‘Low,’ the output is ‘Low.’
3. The Boolean equation for the XOR gate is Y=A’.B+A.B’ if there are two inputs A
and B.

 XOR gate’s symbol and truth table are as follows:

XNOR Gate

 The Exclusive-NOR or ‘EX-NOR’ gate is a digital logic gate that accepts more
than two inputs but only outputs one.

1. If both inputs are ‘High,’ the output of the XNOR Gate is ‘High.’ If both inputs are
‘Low,’ the output is ‘High.’ If one of the inputs is ‘Low,’ the output is ‘Low.’
2. If there are two inputs A and B, then the XNOR gate’s Boolean equation is:
Y=A.B+A’B’.

 A XNOR gate’s symbol and truth table are as follows:

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Conclusion:
We learned how to create and simulate basic logic gates (AND, OR, NOT) and derived
gates (NAND, NOR, XOR) in Logisim. These gates form the building blocks for more
complex digital circuits.

Faculty Signature

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Practical 2
AIM: To Implement the given Sum-of-product and Product-of-
sum Boolean function in Logisim Simulator.(Using boleanAlgebra)
Theory:-
 SOP(SUMOFPRODUCT)
1. AB+AB’+A’B’
2. ABC+ABC’+AB’C+A’BC

 POS(PRODUCTOFSUM)
1.(A’+B’+C)(A’+B’+C’)(A+B+C)(A’+B+C)
2.(A+B+C)(A+B+C’)(A+B’+C’)

Implementation:-

Sum of product

AB+AB’+A’B’ ABC+ABC’+AB’C+A’BC

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Product of sum

(A’+B’+C)(A’+B’+C’)(A+B+C)(A’+B+C)

(A+B+C)(A+B+C’)(A+B’+C’)

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Conclusion:
By applying Boolean algebra postulate rules, we simplified logic functions and
implemented their circuits in Logisim. This showed us how to minimize logic circuits
efficiently.

Faculty Signature

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Practical 3
AIM: Solve the given function using K-MAP Method and draw
logic circuit diagram of each in Logisim Simulator
Theory:-
1.F(A,B,C,D)=m(1,3,4,5,10,11,12,13,14,15)
2.F(A,B,C,D)=m(1,3,4,5,10,11,12,13,14,15)
3.F(A,B,C,D)=m(1,3,4,5,10,11,12,13,14,15)

Implementation:-

Circuit:

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Conclusion:
Karnaugh maps (K-maps) helped us simplify complex Boolean functions by grouping
similar terms. This led to simpler and more efficient logic circuits in Logisim.

Faculty Signature

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Practical 4
AIM: Solve the given function using Tabulation Method and
draw logic circuit diagram of each in Logisim Simulator
Theory:-
1.F(A,B,C,D)=m(1,3,4,5,10,11,12,13,14,15)
2.F(A,B,C,D)=m(1,3,4,5,10,11,12,13,14,15)
3.F(A,B,C,D)=m(1,3,4,5,10,11,12,13,14,15)

Implementation:-

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 Digital Fundamentals (3130704) Sem 3

Extracted essential prime implicants: -10,1-1-,00-1

Expression: bc’ + ac + a’b’d

Circuit:

Conclusion:
The Tabulation Method (also known as the Quine-McCluskey method) allowed us to
systematically minimize Boolean functions. We implemented the minimized circuits in
Logisim for further analysis.

Faculty Signature

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 Digital Fundamentals (3130704) Sem 3

Practical 5
AIM: To implement BCD to Excess-3 Code Convertor in Logisim
Simulator.
Theory:-
BCD to Excess-3 conversion

To understand the process of converting BCD to Excess-3, it is required to have knowledge

of Number System and Number Base Conversion.

The Excess-3 binary code is an example of a self-complementary BCD code. A self-

complementary binary code is a code which is always complimented in itself. By replacing
the bit 0 to 1 and 1 to 0 of a number, we find the 1's complement of the number. The sum of
the 1'st complement and the binary number of a decimal is equal to the binary number of
decimal 9.

The process of converting BCD to Excess-3 is quite simple from other conversions. The
Excess-3 code can be calculated by adding 3, i.e., 0011 to each four-digit BCD code. Below
is the truth table for the conversion of BCD to Excess-3 code. In the below table, the
variables A, B, C, and D represent the bits of the binary numbers. The variable 'D' represents
the LSB, and the variable 'A' represents the MSB. In the same way, the variables w, x, y, and
z represent the bits of the Excess-3 code. The variable 'z' represents the LSB, and the variable
'w' represents the MSB. The 'don't care conditions' is expressed by the variable 'X'.

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 Digital Fundamentals (3130704) Sem 3
Implementation:

we will use the K-map method to design the logical circuit for the
conversion of BCD to Excess-3 code

w=A+BC+BD
x=B'C+B'D+BC'D'
y=CD+C'D'
z=D'

Conclusion:
We successfully designed a circuit to convert Binary-Coded Decimal (BCD) to
Excess-3 code, demonstrating the usefulness of code conversion in digital systems.

Faculty Signature

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 Digital Fundamentals (3130704) Sem 3

Practical 6
AIM: To implement BCD to Gray Code Convertor in Logisim
Simulator
Theory:-
Binary to Gray code conversion

The Binary to Gray code converter is a logical circuit that is used to convert the binary code
into its equivalent Gray code. By putting the MSB of 1 below the axis and the MSB of 1
above the axis and reflecting the (n-1) bit code about an axis after 2 n-1 rows, we can obtain the
n-bit gray code.

The 4-bit binary to gray code conversion table is as follows:

Implementation:

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 Digital Fundamentals (3130704) Sem 3

Conclusion:
The BCD to Gray Code converter circuit was implemented, showing how Gray code
reduces the chances of errors during transitions between binary states.

Faculty Signature

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 Digital Fundamentals (3130704) Sem 3

Practical 7
AIM: To implement Full Adder and Half Adder in Logisim
Simulator.
Theory:-

 HALFADDER
A combinational logic circuit which is designed to add two binary digitsis
known as half adder. The half adder provides the output along with acarry
value (if any). The half adder circuit is designed by connecting anEX-OR
gate and one AND gate. It has two input terminals and two output terminals
for sum and carry.

In case of half adder, the output of the EX-OR gate is the sum of two bits
while the output of the AND gate is the carry. However, the carry obtained
is one addition will not be forwarded in the next addition, so itis called
half adder.

o Sum, S = A ⊕ B
The output equations of the half adder are −

o Carry, C = A.B

 FULLADDER
 A combinational circuit which is designed to add three binary digits and
produce two outputs is known as full adder. The full adder circuit
addsthree binary digits, where two are the inputs and one is the carry
forwarded from the previous addition.
 The circuit of the full adder consists of two EX-OR gates, two AND gates and
one OR gate, which are connected together as shown in thefull adder circuit.

 Sum, S = A ⊕ B ⊕ Cin
 The output equations of the full adder are −

 Carry, C = AB + BCin + ACin

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 Digital Fundamentals (3130704) Sem 3

Implementation:

HALFADDER

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 Digital Fundamentals (3130704) Sem 3
FULLADDER

Conclusion:
We created circuits for both the Half Adder and Full Adder, which are essential in
performing binary addition. The Full Adder is an important component in multi-bit
addition.

Faculty Signature

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 Digital Fundamentals (3130704) Sem 3

Practical 8
AIM: To implement Full Subtractor and Half Subtractor in
Logisim Simulator.

Half Subtractor

● A half subtractor is a digital logic circuit that performs binary

subtraction of two single-bit binary numbers. It has two inputs, A
and B, and two outputs, DIFFERENCE and BORROW. The
DIFFERENCE output is the difference between the two input bits,
while the BORROW output indicates whether borrowing was
necessary during the subtraction.

● The half subtractor can be implemented using basic gates such as

XOR and NOT gates. The DIFFERENCE output is the XOR of the
two inputs A and B, while the BORROW output is the NOT of input
A and the AND of inputs A and B.

● Half subtractor is a combination circuit with two inputs and two

outputs that are different and borrow. It produces the difference
between the two binary bits at the input and also produces an output
(Borrow) to indicate if a 1 has been borrowed. In the subtraction (A-
B), A is called a Minuend bit and B is called a Subtrahend bit.

Truth Table:

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 Digital Fundamentals (3130704) Sem 3

Full Subtractor

A full subtractor is a combinational circuit that performs subtraction of two

bits, one is minuend and other is subtrahend, taking into account borrow of the
previous adjacent lower minuend bit.

This circuit has three inputs and two outputs. The three inputs A, B and Bin,
denote the minuend, subtrahend, and previous borrow, respectively. The two
outputs, D and Bout represent the difference and output borrow, respectively.

The two outputs, D and Bout represent the difference and output borrow,
respectively. Although subtraction is usually achieved by adding the
complement of subtrahend to the minuend, it is of academic interest Full
Subtractor

A full subtractor is a combinational circuit that performs subtraction of two bits,

one is minuend and other is subtrahend, taking into account borrow of the
previous adjacent lower minuend bit.
input borrow; D is the difference; and B denotes the output borrow.

Truth Table:

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 Digital Fundamentals (3130704) Sem 3
Implementation:

Half Subtractor

Full Subtractor

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 Digital Fundamentals (3130704) Sem 3

Conclusion:
The Half Subtractor and Full Subtractor circuits were implemented to understand how
binary subtraction is performed, which is key in arithmetic operations.

Faculty Signature

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 Digital Fundamentals (3130704) Sem 3

Practical 9
AIM: To implement four bit by three-bit binary multiplier

Theory:

Implementation:

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 Digital Fundamentals (3130704) Sem 3

Conclusion:
We built a binary multiplier that could multiply a 4-bit number by a 3-bit number. This
experiment demonstrated how binary multiplication works at the hardware level.

Faculty Signature

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 Digital Fundamentals (3130704) Sem 3

Practical 10
AIM: To implement BCD adder in Logisim
simulator

Theory:

BCD stands for binary coded decimal. It is used to perform the addition of BCD
numbers. A BCD digit can have any of ten possible four-bit representations.
Suppose, we have two 4-bit numbers A and B. The value of A and B can vary
from 0(0000 in binary) to 9(1001 in binary) because we are considering decimal
numbers.

The output will vary from 0 to 18 if we are not considering the carry from the
previous sum. But if we are considering the carry, then the maximum value of
output will be 19 (i.e. 9+9+1 = 19). When we are simply adding A and B, then
we get the binary sum. Here, to get the output in BCD form, we will use BCD
Adder.

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 Digital Fundamentals (3130704) Sem 3
Implementation:

Conclusion:
We implemented a BCD Adder that adds Binary-Coded Decimal numbers. This was
useful for understanding how decimal arithmetic is handled in digital systems.

Faculty Signature

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 Digital Fundamentals (3130704) Sem 3

Practical 11
AIM: To implement Magnitude Comparator in Logisim Simulator

Theory:

A magnitude digital Comparator is a combinational circuit that compares two digital

or binary numbers in order to find out whether one binary number is equal, less than,
or greater than the other binary number. We logically design a circuit for which we
will have two inputs one for A and the other for B and have three output terminals,
one for A > B condition, one for A = B condition, and one for A < B condition.

The circuit works by comparing the bits of the two numbers starting from the most
significant bit (MSB) and moving toward the least significant bit (LSB). At each bit
position, the two corresponding bits of the numbers are compared. If the bit in the first
number is greater than the corresponding bit in the second number, the A>B output is
set to 1, and the circuit immediately determines that the first number is greater than
the second. Similarly, if the bit in the second number is greater than the corresponding
bit in the first number, the A<B output is set to 1, and the circuit immediately
determines that the first number is less than the second.

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 Digital Fundamentals (3130704) Sem 3
Implementation:

Conclusion:
The Magnitude Comparator circuit was created to compare two binary numbers and
determine their relationship (greater, less, or equal), which is used in many digital
applications.

Faculty Signature
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 Digital Fundamentals (3130704) Sem 3

Practical 12
AIM: To implement 3 X 8 decoder in Logisim Simulator

Theory:

The combinational circuit that change the binary information into 2N output
lines is known as Decoders. The binary information is passed in the form of N
input lines. The output lines define the 2N-bit code for the binary information.
In simple words, the Decoder performs the reverse operation of the Encoder.
At a time, only one input line is activated for simplicity. The produced 2N-bit
output code is equivalent to the binary information.

The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8

line decoder, there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6,
and Y7 and three outputs, i.e., A0, A1, and A2. This circuit has an enable input
'E'. Just like 2 to 4 line decoder, when enable 'E' is set to 1, one of these four
outputs will be 1. The block diagram and the truth table of the 3 to 8 line
encoder are given below.

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 Digital Fundamentals (3130704) Sem 3
Implementation:

Conclusion:
A 3x8 Decoder was implemented, which decodes a 3-bit input into one of eight possible
outputs, helping us understand decoding logic in digital systems.

Faculty Signature

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 Digital Fundamentals (3130704) Sem 3

Practical 13
AIM: To implement 4 X 16 decoder with the help of 3 X 8
decoder

Theory:

A decoder is a combinational circuit constructed with logic gates. It is the

reverse of the encoder. A decoder circuit is used to transform a set of digital
input signals into an equivalent decimal code of its output. For ‘n’ inputs a
decoder gives 2^n outputs. In this article, we will discuss on 4 to 16 decoder
circuit design using 3 to 8 decoder.

A decoder of the higher combination is obtained by adding two or more lower

combinational circuits. 4 to 16 decoder circuit is obtained from two 3 to 8
decoder circuits or three 2 to 4 decoder circuits.
When two 3 to 8 Decoder circuits are combined the enable pin acts as the input
for both the decoders. When enable pin is high at one 3 to 8 decoder circuits
then it is low at another 3 to 8 decoder circuit.

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 Digital Fundamentals (3130704) Sem 3
Implementation:

Conclusion:
We successfully implemented a 4x16 Decoder by cascading two 3x8 Decoders. This
showed how larger decoders can be built using smaller ones.

Faculty Signature
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 Digital Fundamentals (3130704) Sem 3

Practical 14
AIM: Draw Combinational circuit diagram for Full Adder and
Full Subtractor using decoder
 FULLADDERUSING3X8 DECODER

 FULLSUBTRACTORUSING 3X8DECODER

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 Digital Fundamentals (3130704) Sem 3
Implementation

Full Adder using 3 X 8 Decoder Full Subtractor using 3 X 8 Decoder

Conclusion:
We used decoders to design combinational circuits for both Full Adder and Full Subtractor,
demonstrating how decoders can be used in arithmetic operations.

Faculty Signature

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 Digital Fundamentals (3130704) Sem 3

Practical 15
AIM: To implement 8 X 1 Multiplexer in Logisim Simulator

Theory:

A multiplexer is a combinational circuit that has 2n input lines and a single

output line. Simply, the multiplexer is a multi-input and single-output
combinational circuit. The binary information is received from the input lines
and directed to the output line. On the basis of the values of the selection lines,
one of these data inputs will be connected to the output.

Unlike encoder and decoder, there are n selection lines and 2n input lines. So,
there is a total of 2N possible combinations of inputs. A multiplexer is also
treated as Mux.

In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4,
A5, A6, and A7, 3 selection lines, i.e., S0, S1and S2 and single output, i.e., Y.
On the basis of the combination of inputs that are present at the selection
lines S0, S1, and S2, one of these 8 inputs are connected to the output.

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 Digital Fundamentals (3130704) Sem 3
Implementation

Conclusion:
The 8x1 multiplexer was successfully implemented, allowing us to select one output from eight input
signals. Multiplexers are crucial in optimizing the use of data lines.

Faculty Signature

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 Digital Fundamentals (3130704) Sem 3

Practical 16
AIM: To implement Boolean function.

Theory:
a) F(a, b, c, d)=Σ(0,2,5,8,10,14) with a multiplexer

b) F(a, b, c, d) =π(2,6,11) with a multiplexer

c) F (a, b, c, d) = Σ(1,3,4,11,12,13,14,15) with a multiplexer

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 Digital Fundamentals (3130704) Sem 3

Implementation: -

a) F(a, b, c, d)=Σ(0,2,5,8,10,14)

b) F(a, b, c, d) =π(2,6,11) with a multiplexer

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c) F (a, b, c, d) = Σ(1,3,4,11,12,13,14,15)

Conclusion:
- a) The Boolean function F(a,b,c,d) = ∑(0,2,5,8,10,14) was implemented using a multiplexer,
demonstrating how multiplexers can simplify Boolean logic circuits.
- b) F(a,b,c,d) = π(2,6,11) was implemented with a multiplexer, showing the versatility of
multiplexers in handling product-of-sum forms.
- c) F(a,b,c,d) = ∑(1,3,4,11,12,13,14,15) was also implemented with a multiplexer, reinforcing how
multiplexers can represent any Boolean function.

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Practical 17
AIM: Design 5 to32 line decoder using basic decoders.
Theory:
 Divide the 5-bit input of the 5x32 decoder into two parts: a 3-bit part and
a 2-bit part.
 Use the 3-bit part to select one of the 2x4 decoders. Use the 2-bit part to
provide the input to the selected 2x4 decoder. Set up 10 separate 2x4
decoders. Each of these decoders will have a 2-bit input and produce 4
outputs.
 Connect the 3-bit part of the 5-bit input to the select lines of these 10
decoders. This will determine which decoder is active based on the 3-
bit input.
 Set up a 1x2 decoder with a single input and two outputs. Connect the 2-
bit part of the 5-bit input to the input of this 1x2 decoder. Connect the
outputs of the 10 2x4 decoders to the inputs of the 1x2 decoder. The 1x2
decoder will use the 2-bit input to select one of its two outputs.
 The 1x2 decoder's selected output will represent one of the 32 output
lines of the 5x32 decoder. Repeat this process for all 32 output lines
of the 5x32 decoder, connecting each output of the 1x2 decoder to the
corresponding output line.
Implementation:

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Conclusion:
A 5-to-32 line decoder was designed by combining smaller decoders, showcasing how complex
decoders can be built by cascading simpler ones.

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Practical 18
AIM: Design parallel adder circuit which can decrement given
input value.
Theory:

 The addition and subtraction operations are combined into one

circuit with one common binary adder is done by including an X-OR
gate with each full-adder.
 The mode input M controls the operation.
 When M = 0, the circuit is an adder, and when M = 1, the circuit
becomes a subtractor. Each X-OR gate receives input M and one
of the inputs of B.
 When M = 0, we have B0 = B. The full-adder receives the value of B,
the input carry is 0 and the circuit performs A + B.
 When M = 1, we have B1 = B' and C₁ = 1. The B inputs
are complemented and a 1 is added through the input carry.
 The circuit performs the operation A + B' + 1 (i.e. A - B).

Implementation

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Conclusion:
The parallel adder circuit was designed to decrement a given input value, which helped us understand
the dual functionality of adders for both addition and subtraction.

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Practical 19
AIM: Design the circuit diagram which can explain the cascading concept in
De-multiplexer

Theory:

Cascading of Demultiplexers
Cascading refers to a process where large Demuxes can be
designed and implemented using smaller Demuxes.

Implementation

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Conclusion:
The cascading concept in a de-multiplexer was demonstrated, showing how multiple de-multiplexers
can be linked to handle more outputs

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Practical 20
AIM: Design the circuit diagram which can explain the
cascading concept in Multiplexer.
Theory:

Cascading of Multiplexers
Cascading refers to a process where large Multiplexers can be
designed and implemented using smaller Multiplexers.

Implementation

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Conclusion:
The cascading of multiplexers was successfully designed, explaining how multiplexers can be
combined to handle more inputs while maintaining efficiency.

Faculty Signature

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Practical 21
AIM: Design the circuit diagram which can explain the utility of
MUX-DEMUX.
Theory:
A MUX (multiplexer) and DEMUX (demultiplexer) are devices used in
telecommunications and digital electronics to manage multiple signals on a single
channel. Here's a brief overview of their utility:

MUX (Multiplexer):

Combines Signals: MUX takes multiple input signals and combines them into a single
output signal. This is useful when you want to transmit multiple data streams over a
shared medium, such as a communication channel or a network link.
Bandwidth Efficiency: MUX helps in efficient utilization of bandwidth by allowing
multiple signals to share the same communication channel. This is essential in scenarios
where bandwidth is limited or expensive.

DEMUX (Demultiplexer):
Separates Signals: DEMUX performs the opposite function of a MUX. It takes a single
input signal that contains multiple data streams and separates them into individual
output signals.
Signal Routing: DEMUX is used to direct each separated signal to its intended
destination or recipient. This is crucial in scenarios where different data streams need to
be sent to different devices or locations.

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Implementation

Conclusion:
A circuit combining MUX and DEMUX was designed, illustrating how they can work together to
route data between different sources and destinations.

Faculty Signature

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Practical 22
AIM: Design the circuit diagram to show a common adder –cum-
subtraction.

Theory:
In Digital Circuits, A Binary Adder-Subtractor is capable of both the addition and
subtraction of binary numbers in one circuit itself. The operation is performed
depending on the binary value the control signal holds. It is one of the components of
the ALU (Arithmetic Logic Unit).

This Circuit Requires prerequisite knowledge of Exor Gate, Binary Addition and
Subtraction, and Full Adder.

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Implementation

Conclusion:
We implemented a common circuit capable of both addition and subtraction, using the same
hardware, showing the flexibility of arithmetic circuits.

Faculty Signature

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Practical 23
AIM: Explain the working of all the following flip flop in Logisim
simulator a) S-R flipflop b) D flipflop c) J-K flipflop d) T flipflop
 S-RFlipFlop
Theory :
It is a Flip Flop with two inputs, one is S and other is R. S here stands for
Set and R here stands for Reset. Set basically indicates set the flip flop
which means output 1 and reset indicates resetting the flip flop which
means output 0. Here clock pulse is supplied to operate this flop flop,
hence it is clocked flip flop.
Truth Table :

Circuit Diagram :

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 DFLIPFLOP
Theory :
D flip flop is an electronic devices that is known as “delay flip flop” or
“data flip flop” which is used to store single bit of data .D flip flops are
synchronous or asynchronous. The clock single required for the
synchronous version of D flip flops but not for the asynchronous one. The
D flip flop has two inputs, data and clock input which controls the flip
flop. when clock input is high, the data is transferred to the output of the
flip flop and when the clock input is low, the output of the flip flop is
held in its previous state.
Truth Table :

Circuit Diagram :

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 J-K flipflop
Theory :
It is one kind of sequential logic circuit which stores binary information
in bitwise manner. It consists of two inputs and two outputs. Inputs are J
& K and their corresponding outputs are Q and Q’. JK flipflop has two
modes of operation which are synchronous mode and asynchronous
mode. In synchronous mode, the state will be changed with the clock(clk)
signal, and in asynchronous mode, the change of state is independent
from its clock signal.
Truth Table :

Circuit Diagram :

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 T flip flop

Theory :
A T flip-flop, or Toggle flip-flop, is a basic sequential logic circuit with a
single input, T (Toggle), and two outputs, Q and Q' (the inverse of Q).
When a pulse is applied to the T input, if T = 1, the flip-flop changes its
state: if Q is 0, it becomes 1, and if Q is 1, it becomes 0, effectively
toggling or flipping its output. When T = 0, the flip-flop maintains its
current state, making it a versatile element for frequency division,
counters, and control circuits due to its ability to alternate between states
with each input pulse, simplifying certain sequential logic operations.
Truth Table :

Circuit Diagram :

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Conclusion:
- a) S-R Flip-flop: Demonstrated basic set-reset functionality, useful for memory storage.

- b) D Flip-flop: Showed how data is transferred at the clock pulse, important for data synchronization

- c) J-K Flip-flop: More flexible than S-R, avoiding invalid states.

- d) T Flip-flop: Toggled states with each clock pulse, simplifying counter designs.

Faculty Signature

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Practical 24
AIM: Design master slave flipflop (using every flipflops)
 SR-MASTERSLAVE

Theory :
A Set-Reset (SR) master-slave flip-flop consists of two interconnected flip-
flops: the master and the slave. In this configuration, the SR latch's inputs (S
for Set and R for Reset) control the flip-flop's behavior. During the active edge
of the clock signal, the master latch captures the input states and temporarily
holds them. The slave latch mirrors the state of the master latch but only
updates its output during the opposite clock edge. When Set (S) is activated, the
flip-flop's output becomes '1,' while activating Reset (R) results in an output of
'0.' However, the illegal or forbidden state of S = R = 1 is avoided, typically by
designing the flip-flop to prioritize Reset when both inputs are active
simultaneously.
Truth Table :

Circuit Diagram :

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 JK-MASTERSLAVE
Working
1. When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the
state of the system. The slave flip-flop is isolated until the CP goes to 0. When the
CP goes back to 0, information is passed from the master flip-flop to the slave and
output is obtained.
2. Firstly the master flip flop is positive level triggered and the slave flip flop is
negative level triggered, so the master responds before the slave.
3. If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave
and the clock forces the slave to reset, thus the slave copies the master.
4. If J=1 and K=0, the high Q output of the master goes to the J input of the slave
and the Negative transition of the clock sets the slave, copying the master.
5. If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave
toggles on the negative transition of the clock.
6. If J=0 and K=0, the flip flop is disabled and Q remains unchanged.

Truth Table :

Circuit Diagram :

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 D-MASTERSLAVE

Theory :
A master-slave D flip-flop works by capturing input data during one
clock edge (in the master stage) and transferring this data to the
output during the opposite clock edge (in the slave stage), ensuring
synchronized and stable output changes while preventing glitches.
Truth Table :

Circuit Diagram :

 T-MASTERSLAVE
Theory :
A T flip-flop, or Toggle flip-flop, is a basic sequential logic circuit with a
single input, T (Toggle), and two outputs, Q and Q' (the inverse of Q).
When a pulse is applied to the T input, if T = 1, the flip-flop changes its
state: if Q is 0, it becomes 1, and if Q is 1, it becomes 0, effectively
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 Digital Fundamentals (3130704) Sem 3
toggling or flipping its output. When T = 0, the flip-flop maintains its
current state,

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 Digital Fundamentals (3130704) Sem 3
making it a versatile element for frequency division, counters, and control
circuits due to its ability to alternate between states with each input pulse,
simplifying certain sequential logic operations.
Truth Table :

Circuit Diagram :

Conclusion:
The master-slave flip-flop was implemented, showing how two flip-flops can be combined to avoid
timing issues and ensure stable output.

Faculty Signature

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Practical 25
AIM: Prepare J-K, Dand T flipflop using S-R Flipflop.
Implementation:-

 Jk flip flop using SR flip flop

 D flip flop using SR flip flop

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 T flip flop using SR flip flop

Conclusion:
We successfully created J-K, D, and T flip-flops using the basic S-R flip-flop as a building block.
This experiment showed how S-R flip-flops can be modified with additional logic to achieve the
functionality of other flip-flops, showcasing their versatility.

Faculty Signature
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Practical 26
AIM: Prepare S-R, D and T flip flop using J-K Flip flop.
Theory:-

SR Flip flop using JK flip flop

Circuit
Diagram :

Truth
Table :

S R Q(n+1)
0 0 Qn
0 1 0
1 0 1
1 1 indeterminate
 D Flip flop using JK flip flop
Circuit Diagram :

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Truth Table :

D Q Q(n+1)
0 0 0
1 0 1
0 1 0
1 1 1

 T Flip flop using JK flip flop

Circuit Diagram :

Truth Table :

T Q Q(n+1)
0 0 0
1 0 1
0 1 1
1 1 0

Conclusion:
The experiment demonstrated that J-K flip-flops can be configured to function as S-R, D, and T flip-
flops by altering their inputs. This reinforced the idea that J-K flip-flops are the most flexible type
due to their ability to avoid invalid states.

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Practical 27
AIM: Prepare J-K, S-R and T flipflop using D Flipflop.
Theory:-

In this conversion, D is the actual input to the flip flop and J and K are
the external inputs. J, K and Qp make eight possible combinations, as
shown in the conversion table below. D is expressed in terms of J, K
and Qp.The conversion table, the K-map for D in terms of J, K and Qp
and the logic diagram showing the conversion from D to JK are given
in the figure below

Step 1: Write the conversion table The conversion table, which is a

combination of truth table and excitation table, to implement a JK flip-
flop using D flip-flop is as follows

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Step 2: Find the Boolean expressions for the inputs of the given flip-flop.

Expression for D would be

D = K’QN + JQN’

Implementation

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D flip flop to SR flip flop

Step 1 : For conversion of D Flip flop to SR Flip flop at first

we have to make combine truth table for SR flip flop
andexcitation table ofD Flip Flop. In bellow see the combine
truth table of SR flip flop and D Flip Flop.

Step 2: Find the Boolean expressions for the inputs of the given flip-flop.

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Implementation

D flip flop to T flip flop

Step 1: Write the conversion table with combination of Truth

table of D flip flop and T flip flop’s excitation table

Step 2: Find the Boolean expressions for the inputs of the given

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 Digital Fundamentals (3130704) Sem 3
flip-flop
Expression for D would be
D = T’QN + TQN’

Implementation

Conclusion:
By manipulating the D flip-flop's input logic, we were able to create J-K, S-R, and T flip-flops. This
showed how the D flip-flop, which is simple and efficient, can still be used to replicate the behavior
of more complex flip-flops.

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Practical 28
AIM; Prepare J-K, D and S-R flipflop using T Flipflop.
Theory
1) JK flip-flop using T flipflop.
Step 1: Create combination table of Truth table of JK and
excitation table of T flip-flop.

Step 2 : : Find the Boolean expressions for T = f(J,K,Qn)

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Expression for T would be
T = KQn+JQn’

Implementation

2) D using T flipflop.
Step 1: Create combination table of Truth table of D and excitation
table of T flip-flop.

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 Digital Fundamentals (3130704) Sem 3
Step 2: Find the Boolean expressions for the inputs of the given flip-
flop

Expression for T would be

T = DQn’ + D’Qn
= D XOR Qn

Implementation

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3) SR using T flipflop.
Step 1: Create combination table of Truth table of SR and
excitation table of T flip-flop.

Step 2: Find the Boolean expressions for the inputs of the given

flip-flop

Expression for T would be

T = SQn’ + RQn

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Implementation

Conclusion:
We successfully implemented J-K, D, and S-R flip-flops using the T flip-flop. This experiment
highlighted how T flip-flops, which toggle on clock pulses, can be transformed into other types of
flip-flops with the right input logic, further demonstrating the interconnected nature of these circuits.

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Practical 29
AIM: Prepare a sequential circuit diagram to explore the
functionality of given state diagram.

Theory:-

Implementation

Boolean expression for A2

T2=A1A0

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Boolean expression for A1

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 Digital Fundamentals (3130704) Sem 3

T1=A0

Boolean expression for A0

T0=1

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 Digital Fundamentals (3130704) Sem 3
Diagram

Conclusion:
We designed a sequential circuit based on a state diagram, allowing us to explore how the circuit
transitions between different states. This helped in understanding how sequential circuits operate over
time, driven by input signals and clock pulses.

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Faculty Signature

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Practical30
AIM: Prepare a sequential circuit diagram using D flipflop of the
given state diagram.

Implementation

Step 1 create truth table of state diagram.

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 Digital Fundamentals (3130704) Sem 3
Step 2: Create combination table of Truth table and excitation
table of T flip-flop.

Boolean expression for D

D=X’Y’Qn+X’YQn’+XYQn+XY’Qn’
= X xor Y xor Qn

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Conclusion:
A sequential circuit was implemented using D flip-flops based on the given state diagram. This
demonstrated how D flip-flops are ideal for sequential circuits as they reliably store and transfer data
on clock edges, maintaining the correct state transitions.

Faculty Signature

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