American International University - Bangladesh

Welcome to the first class of

EEE 3101: Digital Logic and Circuits
 EEE 3101: Digital Logic and Circuits

Course Teacher: Nafiz Ahmed Chisty

Associate Professor and Head (UG)

Department of EEE
Faculty of Engineering, AIUB
Room# DNG03, Ground Floor, D Building
Email: [email protected]
Website: http://engg.aiub.edu/
Website: www.nachisty.com
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Teaching and Consulting Schedule

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Academic Calendar* Spring 2023-2024

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

2024 Day
Jan 22 (Mon) Freshman Students’ orientation**
21-27: Week 1 23 (Tue) First Day of Classes
25 & 28 Adding/ Dropping**
Feb 4-10: Week 3 8 Automatic conversion of UW, I, blank grades of
Fall 2023-24 Semester to F
8 (Thu) Makeup of Sunday Class (Online – MS Teams)
10 (Sat) Makeup of Monday Class (Online – MS Teams)
11 – 17 Week 4
18 – 24 Week 5
25 - Mar 2 Week 6
March 3-9 Week 7: Laboratory Midterm exams
10 - 16 Week 8: Midterm exams **
17 – 23: Week 9 23 Submission of midterm grades
24 – 30: Week TPE
10 30 Midterm grades locked
31 - Apr 6 Week 11: Pre-registration for Summer 23-24 **
April 7 - 13 Week 12
14 – 20 Week 13
21 – 27 Week 14
28 - May 4 Week 15: Laboratory Final exams
May 5 – 11 Week 16: Final Exam **
12 – 18: Week Set B exams
17 18 Submission of Final Grades
25 Final Grades Locked
19 - June 1 Semester break
Release of grades
Final Registration for Summer 2023-24**
June 20 Automatic conversion of UW, I grade of this semester to F

*AIUB reserves the right to change the academic calendar.

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

COURSE OUTLINE

I. Course Core and Title: EEE 3101: Digital Logic and Circuits
II. Credit: 3 credit hours (3 hours of theory per week)
III. Nature: Core Course for EEE
IV. Prerequisite: EEE 2103: Electronic Devices

Objectives:

The objectives of the course can be grouped into two categories.

The first one relates to understanding the basics of Boolean algebra and the
operation of logic components, combinational, and sequential circuits.
The second set of objectives relates to the design of digital circuits and
systems.
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Course Description:
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

This is core course of Electrical and Electronic Engineering & Computer Engineering program that
presents basic tools for the design of digital circuits. It serves as a building block in many disciplines
that utilize data of digital nature like digital control, data communication, digital computers etc.

This course is designed to:

Manipulate Boolean algebraic structures, Implement the Boolean Functions using NAND and NOR
gates, Simplify the Boolean expressions using Karnaugh Map, Analyze and design various
combinational logic circuits, Study of Storage Elements: Introduction to the behavior and structure
of latches, flip-flops, and registers, Understand the importance of state diagram representation of
sequential circuits, Study Sequential Circuits: Analyze and design clocked sequential circuits,
Perform Timing Analysis: Introduction to timing analysis of combinational and sequential circuits.
Special characteristics of Digital logic families and their comparative discussion. Definition and
Problem solving on Fan out, Noise Margin, Propagation Delay, Power Dissipation, Duty Cycle and
Speed Power Product. Diode Logic Gates. Basic Diode Transistor Logic Gates: RTL, DTL, Modified
DTL and HTL with operational detail.

MOS and CMOS Logic with operational detail. Basic memory units and operations. Memory system:
RAM Family. Memory System: ROM Family. Memory System: Flash Memory, Magnetic storage, USB
Flash Drive, SSD hard drive. DSP basics: Sample and Hold circuits. Digital to Analog Conversion with
application. Analog to Digital Conversion with application. Operation and Mathematical operation
of 555 integrated timer circuit: Monostable, Astable multi-vibrator. Charge Coupled Device
(CCD)and LCD. Introduction to Programmable Logic Devices (PLDs): Advantages & disadvantages
over discrete logic gates, Implementation of digital circuits using PLDs (using PAL and PLA).
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Course Outcomes
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

Assessed
COs/ Teaching-
Program BNQF Assessment
CLOs COs/CLOs Statements K P A Learning
Outcome Indicato Strategy
Number Strategy
Indicator r
Apply laws of Boolean Algebra
for implementing combinational
digital logic circuits (gate and
transistor level) and for the
calculation of performance Quiz 1, 2, 3,
parameters (Fan-out, Fan-in, Assignment,
1 Power dissipation, Speed power 2 P.a.2.C3 FS.2 Midterm
products, Noise margin) along Exam
with along with Adders,
Magnitude Comparators, Encoder,
Decoder, Multiplexer and
Demultiplexer with the familiarity
of issues.
Develop a system in context of
Digital logic circuits with 555 P1, OBE
2 timer and transistors for 3 P2 P.a.3.C3 FS.1 Assignment
conflicting requirements of P6 (Final Term)
complex engineering problem.
Apply basic digital signal
techniques, latches and flip-flops Quiz 4, 5,6,
3 with the familiarity of issues for 1 P.a.1.C3 FS.1 Final term
different signal converter and Exam
sequential logic circuits.
Demonstrate individual skills as a
Project
4 leader in solving combinational P.i.2.A5 FS.5
Presentation
or sequential digital circuits.
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Topics to be covered*:
Time
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

Frame Topics*
(Week) *
• Mission & Vision of AIUB, Dept. of EEE, Digital Logic and Circuits meaning and objectives of this
Week 1 course.
• Introduction to Integrated Circuit (IC), Special Characteristics of digital logic families
• Binary Logic, Logic gates and their truth table
• Diode Logic gates Basics of semiconductor memory
• Logic Gates: using RTL, DTL and Modified DTL.
Week 2
• MOS and CMOS logic with operation detail.
• Negative temperature co-efficient
• Design CMOS logic circuits from equation
• Boolean algebra, Simplification of logic function using Boolean Algebra, Implementing circuit from
Boolean expressions.
Week 3
• De-Morgan’s law
• Universal gates and Implementation of Basic Combinational Logic Circuits using Universal Gates only
• Simplifying Boolean Expression using algebraic manipulation
Week 4 • Boolean expression in Sum of Product (SOP) and Product of Sum (POS) form, Canonical forms
• Standardization of SOP/POS expressions and conversions between them
• Simplifying Boolean Expressions using K – map
Week 5 • Adder: Half adder, Full adder, 2’s complement
• Magnitude Comparators
Week 6 • Decoders, Encoders, Priority Encoders, Cascading of Decoders,
• Multiplexers, De-Multiplexer Boolean Function implementation using Multiplexers, Cascading of
Week 7
Multiplexers, De-Multiplexers
Week 8 MID-TERM EXAM WEEK
* The faculty reserves the right to change, amend, add or delete any of the contents.
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Sequential Logic Circuit:

Week 9 • Different types of Flip – flop (S-R, J-K, D and T), Timing Diagram
• Different types of Flip – flop (S-R, J-K, D and T), Timing Diagram

Week 10 Counters: Asynchronous (Modulus Counter)

Week 11 Counters: Synchronous [ State Diagram, Table, Equation]

Week 12 Designing Irregular Counters using State Diagram and State Equation

• Shift registers: Basic Shift Register Functions, Different types of Shift

Week 13 Registers
• Shift register Counters: Johnson counter, Ring counter
• Operation of 555 integrated timer circuit: Monostable, A stable multivibrator
Week 14
Special OBE Assignment for assessing P.a.3.C3
• Digital Signal Processing Basics, Sample and Hold Circuits
Week 15 • Different types of A/D Converter with application
• Different types D/A converter with application.
Week 16 FINAL-TERM EXAM WEEK

* The faculty reserves the right to change, amend, add or delete any of the contents.
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Textbooks/ References
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

Textbooks:
[1] Thomas L. Floyd, “Digital Fundamentals” 11th edition, Prentice Hall.
[2] M. Morris Mano, “Digital Logic & Computer Design” Prentice Hall.

References:
[1] Ronald J. Tocci & Neal S. Widmer, “Digital Systems” 7th edition, Prentice Hall.
[2] Digital design – Karim and Johnson
[3] Brian Holdsworth and Clive Woods, “Digital Logic Design”-Fourth Edition.
[4] Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with VHDL
Design with CD-ROM”
[5] William J. Dally and R. Curtis Harting, “Digital Design: A Systems Approach”
[6] Victor P. Nelson, H. Troy Nagle, Bill D. Carroll and David Irwin, “Digital Logic Circuit
Analysis and Design”
[7] John P. Hayes, “Introduction to Digital Logic Design”
[8] Norman Balabanian and Bradley Carlson, “Digital Logic Design Principles”
[9] Enoch O. Hwang, “Digital Logic and Microprocessor Design with VHDL”
[10] Joseph Cavanagh, “Digital Computer Arithmetic: Design and Implementation
(Computer Science)”
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Course Requirements
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

At least 80% class attendance and submission of ALL assignment/homework

within the deadline decided by the course teacher is necessary.

Evaluation
Marking system For Theory Classes (Midterm)
Attendance and Performance 10%
Midterm: Assignment (Not OBE) 10%
Quiz (Best 2 out of 3) 40%
Midterm: Written 40%
Total 100%

Marking system For Theory Classes (Final term)

Attendance and Performance 10%
Final term: OBE assessed assignment 30%
Quiz (Best 1 out of 2) 10%
Final term: Written 40%
Project presentation + Viva (max. 5 members) 10%
Total 100%

Final Grade/ Grand Total: - - - - - - - 40% of Midterm + 60% of Final Term

 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

COs and POs Assessment

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

Assessment Strategy:

CO/CLO 1 CO/CLO 2 CO/CLO 3 CO/CLO 4 Marks for

(marks) (marks) (marks) (marks) Grading
Quiz (Mid) Q1(20)
Q2(20)
Mid Assignment 10
Quiz (Final) Q3(5)
Q4(5)
OBE Assignment Q1(15)
(Final) Q2(15)
Presentation & 10
Viva
(Final)
Total 50 30 10 10
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Table of Specification (TOS)

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

Mid-Term Exam
Level of Bloom’s Taxonomy
Remember Understand Apply Analyze Evaluate Create

No. of Items
No. of Days

No. of COs
CO No.
Topics

Test Type

Test Type

Test Type

Test Type

Test Type

Test Type

POI
Item No.

Item No.

Item No.

Item No.

Item No.

Item No.
Marks

Marks

Marks

Marks

Marks

Marks
Special
Characteristics 1.a PS 5
of digital logic
families, Binary
CO1 P.a.2
Logic, Logic 3 5
.C3
gates, their
truth table and 4.b PS 5
design of logic
circuit
Boolean CO1 P.a.2
algebra, .C3
Simplification, 2 3 2.a PS 5
Circuit
implementation
SOP, POS, CO1 2.b PS 5 P.a.2
KMAP, 3 4 3.a PS 5 .C3
Universal gates 5.b PS 5
Adder, 2’s CO1 1.b PS 5 P.a.2
complement, .C3
Comparator, 3.b PS 5
6 8 4.a PS 5
Encoder,
Decoder, MUX, 5.a PS 5
DeMUX
Total 14 20 50
Test Type Legend: AS: Assignment; BQ: Broad question; SQ: Short question; D: Derivation; ES: Essay; EX: Exercise; GE: Group Exercise; ID: Identification; MC: Multiple Choice; MT: Matching Type; OB:
Observation; PS: Problem Solving; SA: Short Answer; TF: True or False; VV: Viva Voce; Other please specify:
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Final Exam
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

Level of Bloom’s Taxonomy

Remembe Understa Evalua
Apply Analyze Create

No. of Items
No. of Days

No. of COs
CO No. r nd te
Topics

POI
Test Type

Test Type

Test Type

Test Type

Test Type

Test Type
Item No.

Item No.

Item No.

Item No.

Item No.

Item No.
Marks

Marks

Marks

Marks

Marks

Marks
Flip- flops, P.a.
Timing CO3 2 2 3.b PS 5 1.C
diagram 3
1.b PS 5
Counters P.a.
2.a PS 5
and Shift CO3 6 6 1.C
3.a PS 5
register 3
4.a PS 5
2.b PS 5 P.a.
Timer CO2 4 2 1.C
5.b PS 5
3
Digital CO3 1.a PS 5 P.a.
Signal 4 4 4.b PS 5 1.C
Processing 5.a PS 5 3
Total 16 14 50
Test Type Legend: AS: Assignment; BQ: Broad question; SQ: Short question; D: Derivation; ES: Essay; EX: Exercise; GE: Group Exercise; ID: Identification; MC: Multiple Choice; MT: Matching Type; OB:
Observation; PS: Problem Solving; SA: Short Answer; TF: True or False; VV: Viva Voce; Other please specify:
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Assessment rationale:
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

The examinations will consist of questions regarding topics mentioned in the

class schedule.
Quiz
• Each quiz mark is 20.
• No makeup quiz will be taken. (You have to be serious from first to last)
• Quiz script will be cancelled, if students do any cheating and if students do not
write his/her name and ID on the top of quiz paper.

Attendance
• At least 80% presence is necessary.
• Late in Class:10 minutes from the time of start of the class, full attendance.
Otherwise late marking. (2 late is equal to one absent).
• Students must inform the course teacher regarding his/her absence before class
through e-mail, MS Teams, or via guardian/friend/family to the course teacher.
• If your attendance is very poor, it will be informed to OSA and they will
contact with your guardian.

Assignment and VIVA

• There might be 2/3 assignments (OBE/non-OBE) and Viva.
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Teaching Method
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• Maximum topics will be covered from the textbook. For the rest of the topics,
reference books will be followed. Some Class notes will be uploaded on the web.
• Students must study up to the last lecture before coming to the class and it is
suggested that they should go through the relevant chapter before coming to the
class. Just being present in the class is not enough- students must participate in
classroom discussions.
• Formal lectures will provide the theoretical base for the subject as well as
covering its practical application.
• A set of lecture notes, tutorial examples, with subsequent discussion and
explanation, together with suggested reading will support and direct the students
in their own personal study.
• Few assignments will be given to the students based on that class to test their
class performance.
Teaching Materials

• Teacher would post the syllabus and the lecture notes on the course webpage in
VUES.
• Students must store the teaching materials and the course outline/syllabus, as
these might be required in future, especially for admission for higher studies.
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Missing Evaluations
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• Makeup for missing Quiz/Assignment/ etc… will be considered only through valid
application procedures with pure evidence of reasoning.
• Student missing less than 40% of the total evaluation for each term (mid/final)
will be given ‘I’ (incomplete) grade along with a strict deadline to complete the
missing evaluations by the course teacher.
• Student missing more than 40% of the total evaluation for each term (mid/final),
will be given ‘UW’ (Unofficial Withdraw) grade. Students must go through valid
application procedures with pure evidence of reasoning to change ‘UW’ to ‘I’.
• Except extreme cases (accident/hospitalized etc.), marks for attendance will not
be considered. On extreme cases, partial/full marks (judged by the course teacher)
may be given to the student.

During Class
• Students are encouraged to ask question at any moment during the lecture,
• The teacher might ask question to students,
• Students must have active headphone or mic/speaker,
• Teachers will randomly ask the students to share the desktop for checking
student activity/ question’s answer.
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Consultation
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• Students are Encouraged to use e-mail/ MS Teams to communicate with the

teacher for Consultation.
• You may communicate during the consulting hours of the teacher or at any time
you feel comfortable. The teacher will revert back at his earliest possible time.
• Group/one-to-one consultation both are allowed.
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Important Dates: Midterm

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

For Sections: M & E (Sunday-Tuesday class)

Syllabus*
Book Chapter
Quiz No.* Date*
Uploaded Slide No. (Floyd
9th Edition)
Quiz 1 February 18, 2024 3_Logic_Gates Chapters 3,15

Quiz 2 February 27, 2024 4a_Boolean Algebra Chapters 3, 5, 6

5_Universal Gates,
Quiz 3 March 03, 2024 6_Adders, & Chapters 4
7_Magnitude Comparator
Assignment March 07, 2024 All Chapters 2,3,4,5 & 6,15
* Faculty reserves the right to change with/ without prior notice.

For Sections: D & C (Monday-Wednesday class)

Syllabus*
Book Chapter
Quiz No.* Date*
Uploaded Slide No. (Floyd
9th Edition)
Quiz 1 February 19, 2024 3_Logic_Gates Chapters 3,15

Quiz 2 February 28, 2024 4a_Boolean Algebra Chapters 3, 5, 6

5_Universal Gates,
Quiz 3 March 04, 2024 6_Adders, & Chapters 4
7_Magnitude Comparator
Assignment March 07, 2024 All Chapters 2,3,4,5 & 6,15
* Faculty reserves the right to change with/ without prior notice.
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Important Dates: Final term

For Sections: M & E (Sunday-Tuesday class)
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

Quiz No.* Date* Book Chapter Details

Uploaded Slide No. (Floyd
11th Edition)
Quiz 1 April 02, 2024 2_Counters Chapter 7 & 9 Offline mode
3_Shift Registers
Quiz 2 April 23, 2024 Chapter 8 & 12 Offline mode
5_DSP
VUES
OBE Assignment May 02, 2024 4_555Timer Chapter 7
(valid till 11:45PM)
Link:
Project Presentation Slide https://forms.office.com/r/BaW0
April 25, 2024
submission Chapter 7, 8, 9, 10, 11 FWeWdi
All
& 12 (valid till 11:45PM)
Project Presentation &
April 28, 2024 Offline mode
VIVA
* Faculty reserves the right to change with/ without prior notice.

For Sections: D & C (Monday-Wednesday class)

Quiz No.* Date* Book Chapter Details

Uploaded Slide No. (Floyd
11th Edition)
Quiz 1 April 03, 2024 2_Counters Chapter 7 & 9 Offline mode
3_Shift Registers
Quiz 2 April 24, 2024 Chapter 8 & 12 Offline mode
5_DSP
VUES
OBE Assignment May 02, 2024 4_555Timer Chapter 7
(valid till 11:45PM)
Link:
Project Presentation Slide https://forms.office.com/r/BaW0
April 25, 2024
submission Chapter 7, 8, 9, 10, 11 FWeWdi
All
& 12 (valid till 11:45PM)
Project Presentation &
April 29, 2024 Offline mode
VIVA
* Faculty reserves the right to change with/ without prior notice.
Thanks