Low power design techniques and check

during Implementation

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 Outline

• Sources of power dissipation

• Power management techniques
• Low power RTL to GDSII using CPF
• Low power infrastructure
• Conformal Low power checks

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 Low power Design

❖ Source of power dissipation

P = P switching + P short-circuit + P leakage

• Switching power P = CV2fα

• Short circuit power P = IscV
• Leakage power P=Ileakage V
α : switching activity factor

❖ Low power design would look at the trade-offs of the above issues

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 Switching Power Dissipation

❖ Caused by the charging and discharging of the node capacitance

❖ Ps/w= 0.5 *  * CL* Vdd2 * fclk

Depends on:
▪ Supply voltage
▪ Physical Capacitance
▪ Switching activity

Figure 1: Switching power dissipation [1].

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 Short circuit power dissipation

❖ Caused by simultaneous conduction of n and p blocks

❖ Depends on:
▪ The input ramp
▪ Supply voltage
▪ Load
▪ The transistor size of the gate
▪ Frequency
▪ Threshold voltage.

Figure 2: Short circuit current [2]

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 Leakage power dissipation

❖ Six short-channel leakage mechanisms are there:

• I1 Reverse-bias p-n junction leakage
• I2 Sub threshold leakage
• I3 Oxide tunneling current
• I4 Gate current due to hot-carrier injection
• I5 GIDL (Gate Induced Drain Leakage)
• I6 Channel punch through current

❖ I1 and I2 are the dominant leakage mechanisms

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Leakage power dissipation (Cont’d)

Figure 3: Summary of leakage current mechanism [2]

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 Power management techniques

❖ Low Power Techniques for reducing switching & leakage power

• Clock tree optimization and clock gating

• Operand isolation
• Logic restructuring
• Logic resizing
• Transition rate buffering
• Pin Swapping
• Multi Vth
• Multi supply voltage
• DVS (Dynamic Voltage scaling)
• DVFS (Dynamic voltage and frequency scaling)
• Adaptive voltage and frequency scaling (AVFS)
• Power shut-off (PSO) [or power gating]
• Substrate biasing (body biasing or back-biasing)

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Low power RTL to GDS-II using CPF

Design

Quality Checks

Common Power format

Low power verification

Synthesis

Netlist checks

Equivalency checks

Design for Test

Physical Design Implementation

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Low power RTL to GDS-II using CPF

Floor planning

Placement

Low Power Checks

Clock tree Synthesis

Routing/
Signal Integrity Analysis

Signoff Analysis and Verification

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 Power management techniques
❖ Low Power Techniques that have high impact on implementation complexity
• Gate level optimizations-logic restructuring, resizing and pin Swapping
• Clock gating
• Multi Vth optimization
• Multi supply voltage
- creation of power domains, Placement and optimization and level shifter handling
• Power shut-off (PSO) [or power gating]
• DVFS (Dynamic voltage and frequency scaling)
• Substrate biasing (body biasing or back-biasing)

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 Power gating

❖ Low Power Techniques for reducing switching & leakage power

Vdd

Logic
Cell

Virtual
Ground

sleep Switch
Cell

Figure 5: Fine grain power gating Figure 6: coarse grain power gating

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 Performing power optimization
Dynamic Power:
• The tool supports low-power placement and power-aware clock tree synthesis
set_scenario_options –dynamic_power true
Read the switching activity file using the read_saif

Static (leakage power):

• The tools performs adaptive leakage power optimization which uses high-threshold-voltage cells during
the initial stages of optimization and gradually increases the use of low-threshold-voltage cells during
the later stages.
set_scenario_options –leakage_power true
set_multi_vth_constraint
• Low Vt cells are used on timing critical paths to help setup timing
• High vt cells are used on non critical timing paths to save leakage power.

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 Performing power optimization
Dynamic Power:
• The tool supports low-power placement and power-aware clock tree synthesis
set_scenario_options –dynamic_power true
Read the switching activity file using the read_saif
set_optimize_pre_cts_power_options –low_power_placement true
Perform placement and optimization by using the place_opt

Static (leakage power):

• The tools performs adaptive leakage power optimization.
set_scenario_options –leakage_power true
set_multi_vth_constraint

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 Performing power optimization
Perform leakage-power optimization by using one of the following commands
place_opt –power
clock_opt –power
psynopt –power

Performing total power optimization:

set_total_power_strategy –effort none | medium | high
place_opt –power
psynopt –power
psynopt –only_power

Optimizing clock gating logic:

place_opt –optimize_icgs

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 Low-power Infrastructure

❖ Low power cells:

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 Conformal Low power checks

❖ Low Power Check

• Is the power intent correct for the RTL design
• Does the deign netlist still comply to the same power intent

❖ What CLP do ?

• Incorrect power and ground connectivity

• Instances with undefined power domains or mixed power domains
• Missing, redundant, and incorrect power connection and wrong level shifter types
• Missing, redundant, and incorrect isolation cell power connectivity
• Power control signals to power switches, isolation cells, and state retention registers that are not
powered
• Incorrect power connection to state retention registers

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 References

1. L. Wei, K. Roy, and V. De, “Low-voltage low-power CMOS design techniques for deep submicron
ICs,” in Int. Conf. VLSI Design, Jan. 2000, pp. 24-29.
2. https://www.si2.org/?page=1061

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THANK YOU

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