Design & Verification

of
Low Power SoCs

Need for Low Power

High power density causes cooling and packaging
challenges

Cost of cooling solution is comparable to the

cost of system.

Reliability issues mean time to failure

decreases exponentially with temperature

Timing degradation and leakage current issues

are more pronounced

Lower the feature size, more prominent is the

leakage current.

It is nearly as large as dynamic current.

Potential failure to meet the expected life of a

battery

Power Vs Energy
For battery operated devices, the distinction between power and energy is critical

Power

Time
Energy determines the life of a battery
Example :
Battery Capacity
=
Rated output voltage =
Average power
=
Standby time
=
=

1.7 Ah
3.7 V
0.5 W
1.7 * 3.7 / 0.5
12.58 hours

Energy
Batteries have finite amounts of energy stored in
them
Voltage
Reduce
Reduce
Running fast and then idling wastes energy
Voltage
Voltage

Reduce
Reduce
Voltage
Voltage

Reduce
Reduce
Voltage
Voltage

Energy
Energy
Saved
Energy

Run
RunTask
Task in
in
Available
Time
Available Time

Run
Run Task
Task Slow
Slow
as
Possible
as Possible
Time
Task 1

Idle

Task 2

Task 3

Only
Onlyneed
needto
torun
runjust
justfast
fastenough
enoughto
tomeet
meetthe
theapplication
applicationdeadlines
deadlines

Components of
Power
Power
Static

Dynamic
Switching

ISUB

ISUB
IGATE
IGIDL
IREV

IGATE

=
=
=
=

IGIDL

IREV

Sub-threshold leakage
Gate leakage
Gate Induced Drain Leakage
Reverse bias junction leakage

Internal

ICROWBAR

ICHARGING

Trends In Power Dissipation

Static power dissipation can no longer be ignored

It became significant at 90nm and dominant at 65nm

Leakage currents are rising fast

Must be controlled by circuit design and optimization tools
Slide 97 (of 118)

Low Power Challenges:

Manage power in all modes in which a design operates

Dynamic power during device operation including active leakage
Static power dissipation during standby

Maintain device performance while minimizing power consumption

Meet most aggressive performance targets while minimizing power
Aggressive power optimization when running at reduced performance levels
Minimize impact to performance by employing aggressive low power
techniques
Employ a number of low power techniques in a single processor
implementation

Aggressive techniques for power management

Dynamic power minimized through OS directed performance scaling

Dynamic power minimized through use of Multi-Vt and Multi-L libraries
Standby power minimized through power gating with state retention
Additional standby power savings through use of threshold scaling (bias)

Slide 106 (of 118)

A UPF Example

Power management Structures: The Data Objects

Power Domain

Power States

Controlled by Switches
Memories may require
Retention
States may require
sequencing info
States will effect
simulation

Relations & Connections

between Domains

The collection of design

objects that share
common power attributes

Level shifters
Isolation logic
Gas Stations
alternate supply

Identify elements
Manage
Implement
Analyze
Reuse

Divide the design into

different power domains

Successive Refinement of Low Power Intent

IP Creation

RTL
RTL

Soft IP

Constraint
Constraint
UPF
UPF

IP Configuration
RTL
RTL
Constraint
Constraint
UPF
UPF

Golden Source

Configuration
Configuration
UPF
UPF

IP Implementation
RTL
RTL
Constrnt
ConstrntUPF
UPF
Confign
ConfignUPF
UPF

+
Impltion
ImpltionUPF
UPF

IP Provider:

Synthesis

Impltion
ImpltionUPF
UPF

Creates IP source
Creates low power
implementation
constraints

Netlist
Netlist

IP Licensee/User:

Configures IP for context

Validates configuration
Freezes Golden Source
Implements configuration
Verifies implementation
against Golden Source

P&R

Impltion
ImpltionUPF
UPF
Netlist
Netlist

Slide 109 (of 118)

Simulation, Logical
LogicalEquivalence
Equivalence Checking,
Checking,

Simulation,

Basics about Power Intent

Specification
Objects in a power domain to be
supplied:
Isolation

Power domain
Level
shifter

Retention

Other
Elements

Requirements for XML specification of power intent:

Identifier for objects to be supplied by power
Power supplies
Explicit supply net names must be avoided
Relation of states for power supplies
Power State Table (PST)
With legality: ok, never, unspecified

Transition between power states

UPF domain creation

Logical Electrical Physical
UPF Commands
Domain1
constant
u0

u1

u2

Diagram from Andrew

create_power_domain top -include_scope

create_power_domain SUB0 -elements {u0}
create_power_domain SUB1 -elements {u1}
create_power_domain SUB2 -elements {u2}

UPF supply network creation

Logical Electrical Physical
UPF Commands
Domain1
constant

Diagram from Andrew

#Supply net creation for domain top

create_supply_net VDD
-domain top
create_supply_net VDD_SUB1
-domain top
create_supply_net VDD_SUB2
-domain top
create_supply_net GND
-domain top
#Supply net creation for domain SUB0
create_supply_net VDD
-domain SUB0 -reuse
create_supply_net VDD_SUB0_SW
-domain SUB0
create_supply_net GND
-domain SUB0 -reuse
#Supply net creation for domain SUB1
create_supply_net VDD_SUB1 -domain SUB1 -reuse
create_supply_net GND
-domain SUB1 -reuse
#Supply net creation for domain SUB2
create_supply_net VDD_SUB2 -domain SUB2 -reuse
create_supply_net GND
-domain SUB2 -reuse

UPF supply network creation

cont
UPF Commands
Domain1
constant

Diagram from Andrew

create_supply_port
create_supply_port
create_supply_port
create_supply_port

VDD
-domain top
VDD_SUB1 -domain top
GND
-domain top
VDD_SUB2 -domain top

connect supply_net VDD ports VDD

connect supply_net VDD_SUB1 ports VDD_SUB1
connect supply_net VDD_SUB2 ports VDD_SUB2
connect supply_net GND ports GND
set_domain_supply_net top \
-primary_power_net VDD \
-primary_ground_net GND
set_domain_supply_net SUB0 \
-primary_power_net VDD_SUB0_SW \
-primary_ground_net GND
set_domain_supply_net SUB1 \
-primary_power_net VDD_SUB1 \
-primary_ground_net GND
set_domain_supply_net SUB2 \
-primary_power_net VDD_SUB2 \
-primary_ground_net GND

UPF levelshifter strategy

Domain1
constant

Diagram from Andrew

Level shifter
considerations
Pick a power domain
or a set of elements
Select input ports,
output ports, or both
Tolerate a voltage
difference threshold
UP shift or down SHIFT
rule
Location (self, parent,
sibling, fanout, auto)
Insert or not insert

UPF levelshifter strategy

UPF Commands
Domain1
constant

Diagram from Andrew

set_level_shifter SUB1_to_TOP \
-domain SUB1 \
-applies_to outputs \
-rule low_to_high \
-location parent
set_level_shifter TOP_to_SUB1 \
-domain SUB1 \
-applies_to inputs \
-rule high_to_low \
-location self
set_level_shifter SUB2_to_TOP \
-domain SUB2 \
-applies_to outputs \
-rule low_to_high \
-location parent
set_level_shifter TOP_to_SUB2 \
-domain SUB2 \
-applies_to inputs \
-rule high_to_low \
-location self

UPF isolation cell strategy

UPF Commands
set_isolation ISO_STRAT \
-domain SUB0 \
-isolation_power_net VDD \
-isolation_ground_net GND \
-clamp_value 0

Domain1
constant

PM ctrl
logic

Diagram from Andrew

ISO

VDD

GND

set_isolation_control ISO_STRAT \
-domain SUB0 \
-isolation_signal reg_out[25] \
-isolation_sense high \
-location parent

UPF - retention cell strategy

UPF Commands
set_retention key_desIn \
-domain SUB0 \
-retention_power_net VDD \
-elements {u0/uk/ret_key_sel u0/ret_des_key_r \
u0/ret_desIn_r}

Domain1
constant

PM ctrl
logic

Diagram from Andrew

ISO

VDD

GND

set_retention_control key_desIn \
-domain SUB0 \
-save_signal {key_b_r_reg[16][27]/pin:Q high} \
-restore_signal {key_b_r_reg[16][26]/pin:Q low}

UPF - switch cell creation

UPF Commands
Domain1
constant

PM ctrl
logic

Diagram from Andrew

ISO

VDD

GND

create_power_switch SUB0_SW \
-domain SUB0 \
-input_supply_port {TVDD VDD} \
-output_supply_port {VDD VDD_SUB0_SW} \
-control_port
{NSLEEPIN1 SE_ME_on_1 } \
-control_port
{NSLEEPIN2 SE_ME_on_2 } \
-ack_port
{NSLEEPOUT1 SE_ME_on_ack_1}
\
-ack_port
{NSLEEPOUT2 SE_ME_on_ack_2}
\
-on_state {SW_on TVDD {NSLEEPIN2 &
NSLEEPIN1} } \
-off_state {SW_off {!NSLEEPIN2 & !NSLEEPIN1}}
VDD
TVDD
NSLEEPIN1

NSLEEPOUT1

NSLEEPIN2

NSLEEPINOUT2
VDD

VDD_SUB0_SW

UPF power states

Domain1
constant

PM ctrl
logic

Diagram from Andrew

ISO

VDD

GND

A power state table defines

the legal combinations of
states for different domains
The create_pst command
creates a PST, using a
specific order of supply
nets during operation of
the design
Each row defines a valid
combination of supply
states
Power states enable
optimization and
verification
Infer of verify level shifters and
isolation gates

UPF power states

UPF Commands
create_pst PM_pst supplies\
{ VDD
u0/VDD_SUB0_SW VDD_SUB1 VDD_SUB2 }

Domain1
constant

PM ctrl
logic

Diagram from Andrew

ISO

VDD

GND

add_pst_state pst0 pst PM_pst state \

{ VDD_N SW_on
SUB1_H

SUB2_H}

add_pst_state pst1 pst PM_pst state \

{ VDD_N SW_off
SUB1_L

SUB2_L}

VDD

VDD_SUB0_S
W

VDD_SUB
1

VDD_SUB
2

pst0

VDD_N

SW_on

SUB1_H

SUB1_H

ps1

VDD_N

SW_off

SUB1_L

SUB1_L

Defining a Power State

Same command for both supply sets and domains

add_power_state object_name
-state state_name
-supply_expr {boolean_expr}
-logic_expr {boolean_expr}
[-simstate simstate]
-legal | -illegal
-update

Can be refined (-update) over time as design evolves

-supply_expr is the golden specification of the power state used by

synthesis and LEC
-logic_expr initial, approximation of the power state definition (in the
absence of a supply_expr)

-logic_expr becomes an assertion check when supply_expr is specified

-supply_expr and logic_expr state definitions can be refined
supply_expr = old_supply_expr && new_supply_subexpr

Legality

The default for a user-defined power state is legal

Specify illegal to override default; -legal to be explicit

By default, undefined power states are illegal

Override default legality of undefined power states for an object:

add_power_state my_power_domain -legal

Power Portion of Robust

Interface
Designing within a context

G1

G2

B1

B2

B3

M1

M2

Green

mod

Blue

Supply sets and set_port_attributes

UPF Commands: mod_if

Create_power_domain
mod_PD
-include_scope
Create_power_domain G
Create_power_domain B
Set_port_attributes
-ports {G1, G2}
-supply_set G.primary
Set_port_attributes
-ports {B1, B2, B3}
-supply_set B.primary
<Set_port_attributes
-ports {M1, M2}
-supply_set
mod_pd.primary>
mod_details:
Create_power_domain G
-update
-elements {Green}
Create_power_domain Bupdate

Use Components in an
Design
G1 G2 B1 B2 B3 M1 M2

G1 G2 B1 B2 B3 M1 M2

Green

Green

mod

Blue

G1 G2 B1 B2 B3 M1 M2

Green
mod

Blue

mod

Blue

UPF Commands: top

create_power_domain top_PD
-include_scope
create_power_domain pd_G
-elements {Y}
create_power_domain pd_B
-elements {Z}
set base set_scope
foreach {el} {I1 I2 I3} {
set_scope $base/$el
load_upf mod_if.upf
}
set_scope $base
create_composite_domain topc_PD
subdomains {top_PD
U1/mod_PD U2/mod_PD
U3/mod_PD}
create_composite_domain pdc_G
subdomains {pd_G U1/G U2/G
U3/G}
create_composite_domain pdc_B
subdomains {pd_B U1/B U2/B
U3/B}

Power Tasks on both sides of

the
Abstraction
Back End:
Front end:

Functional specification
Checking the specification
Corruption recognized
Srikanth will provide more detail

Inserts corruption based on

power
Specify and validate Isolation

Structural specification
Correlation to structural
No new corruption

Specify allowed and forbidden

power states and transitions
Ensure forbidden states and
transitions never present
Electrical safety

Electrical protection (level

shifting) for all possible states
(or specified requirements)
Implementation is conservative
compared to specification

Logical protection - Isolation

Structural checks all supplies
that affect the behavior are
accounted for in the front end.

Simulate and Implement same the Design

Verification of Power
Managed Designs

Range of Voltage-Control
Techniques
1.2V
1.2V

1.0V
1.0V

1.2V
OFF
1.2V

0.9V
0.9V

Multi-Vdd (MV)

PWR
PWR
CTRL
CTRL

1.0V
1.0V

0.9V
0.9V

MTCMOS power gating

(shut down)

0.9-1.2V
0.9-1.2V

VDDB
A

1.0V
1.0V

1.2V
RET
1.2V

0.9V
0.9V

Power gating with

State Retention

1.2V
0.6V
1.2V

0.9V
0.9V
VSSB

Dynamic or Adaptive
Voltage Frequency Scaling
(DVS, DVFS, AVS, AVFS)

1.0V
1.0V

Variable VTH
(Back Bias P/N)

1.0V
1.0V

0.9V
0.9V

Low-VDD Standby

Power Management increases verification

complexity enormously
V1

Display
Display
in in
Display in
OFF Mode
Normal
HP Mode
Standby
Mode with
Power Switches

CPU in
CPU in
Normal
Standby
HP
Mode
Mode

Tx/Rx
Tx/Rx in
in
Normal
Standby
Mode

Level Shifters
Isolation Cells

V2

V3

Audio in
OFF Mode
Audio
in
with
Normal
Power
Mode
Switches

PMU

Video in
Video
OFFinMode
Normal
with
Mode
Power Switches

Correct
Multiple
implementation
power
states,
of transitions
LP specific
and
design
Verification
must now
understand
voltage
elements
must
mustbe
happen
verifiedStandby
values
Phone Call sequences
PDA

Power Management brings

new bug types!

Isolation/Level Shifting Bugs

Control Sequencing bugs
Retention scheme/control errors
Retention selection errors
Electrical Problems like memory corruption
Power Sequencing/Voltage Scheduling errors
Hardware-Software deadlock
Power Gating collapse/dysfunction
Power On Reset/bring up problems
Thermal runaway/ Overheating
These are not traditional functional bugs!

Bug Classification
Structural Errors
Missing Isolation, Level Shifters
Devices in wrong domains
Wrong Rail connections

Control Errors
Mistimed Control signals
Incorrect control activation sequence
Incorrect gating/ungating in off/low power
states

Architectural Errors
Incorrect partitions, policies

Structural Errors
PMIC/PMU
ISO-Enable

Domain 1
ON(1.2V)/OFF

Domain 2
0.9-1.2

Isolation

Domain 3
ON (1.2V)

Level Shifters

Structure needs to be checked constantly

through out the implementation flow

Incorrect Isolation
Sequence
Control Error
Intended
Intended
Behavior
Behavior

Output HighZ based

on sleep signal

1.
1.Gate
Gatethe
theclk
clk
2.
2.Assert
Assertiso
isoto
to
00
3.
Assert
sleep
3.
Assert
sleep
Actual
Behavior
Actual
Behavior
to
to00
1.
1.Gate
Gatethe
theclk
clk
2.
2.Assert
Assertsleep
sleep
to
to00
3.
3.Assert
Assertiso
isoto
to
00

X is observed due
to incorrect iso timing

Registers initialized to X
after power restoration

Control signal
sequence error is
discovered due to X
propagation

Voltage Scheduling Error

Control/Architecture Error
Top
1.2V
0.9V
Island 1

A[63:0]

1.1V
0.8V
Island 2

1.2V
1.1V

Logic Simulator cannot

distinguish between voltage
values - All treated as 1

0.9V
0.8V

1.2V
1.1V
0.9V
0.8V

Need Level
Shifter

Verification must be aware of the waveform nature of voltage

Voltage-Aware Simulation is
now necessary!
0.7 V
1

1.0 V
1

0.7 V
1

Traditional Simulators are

not voltage aware

1.0 V
1

Voltage-Aware Simulators
are Electrically Accurate

Modeling
True Voltage Aware
Simulation
Parameterized
Parameterized source
source
code
code provided
provided

Real
Real Voltage
Voltage
Voltage
Voltage Ramp
Ramp

function real vrm();

The rise of Retention

State loss from Power Shut Off may not be OK
Performance hit with cache misses
Or Latency impact for Cold Start
Traditionally, Low Vdd Stby was used to retain state
As Vtn, Vtp ->0, Vstby becomes impractical
Retention flops: Shadow the main element with high Vt
Cut off Vdd, but hold on to Shadow element power
Restore from Shadow to main element after powerup
Many Flavors of Retention exist
Languages dont model them well!
Retention is a huge verification challenge

Retention stretches
language
semantics
Retention : A balloon latch is used to retain state when power is
turned off

Wait, we lack semantics for shutdown, how do we deal with

this?
always @ (posedge clk or
always @ (posedge clk or
negedge
reset_n)
if (!reset_n) q <= 0;
else
q <= d;

Need to
simulate and
verify this!

negedge reset_n or
posedge save or
posedge restore)
if (!vdd)
q
<=
1bx;
else if (!reset_n) q
<= 0;
else if (save)
q_s <= q;
else if (restore) q
<= q_s;
else
q
<= d;

Retention is a huge verification

challenge
Slide 67 (of 118)

Verifying Retention
Complete power Sequence
CLK
CLK -EN

Enable
Clock

Disable
Clock

SAVE
ISO
PWR EN
VDD
PWR RDY
RESTORE

Save
Enable
Isolation
Disable
Power
Ramp
Voltage
Disable
Ready

Disable
Isolation
Enable
Power
Ramp
Voltage
Enable
Ready
Restore

Verifying Retention
Corner Cases Can Be Tricky
PWR GATED DMA

PREMATURE
RESTORE SIGNAL

SAVE
ACTUAL
RESTORE
REG A

aa

EXPECTED
RESTORE
REG B

bb

bb

Low Power Testbenches

Elements of a Low Power

Testbench

Coding Guidelines
1b0 and 1b1 no single supply1 or supply0
Use tie_hi_<name> or tie_lo_<name>

Initial blocks dont get retriggered again

Be careful with readmem and other initializations in
on/off

Asynch reset doesnt get activated again

Could be design or testbench issue

X-detection monitors can go crazy

Avoid stopping the test on x in an on/off block!

Assertions need to account for off state!

Dont use XMR force statements!

Redefining Coverage
CORE (ON)

LP0

LP1

AllOn

LP2

AllOff

AllOn

CORE
AllOn

DOMAIN
DOMAIN11

DOMAIN
DOMAIN22

ON/OFF
ON/OFF

ON/OFF
ON/OFF
CORE

Domain1

Domain2

AllOff

OFF

OFF

OFF

LP0

ON

OFF

OFF

LP1

ON

OFF

ON

LP2

ON

ON

OFF

AllOn

ON

ON

ON

ON

Power Intent elements, Power States, Transitions and Sequences need a

Coverage strategy

Source vs. Leaf level

assertions
Power
switch
ON/OFF

PS_ENABLE

PMU

Absence of one
leaf-level assertion
will cause failure of
design

Source Assertion:
When PS_ENABLE =1,
ISO_ENABLE = 0

Source level
assertions cannot
be relied upon to
ensure correct
operation of design

ISO_ENABLE

RTL
Lines
6099

Voltage Power
Islands States
4

RTL
Assertions

Gate Level
Assertions

685

1891
Slide 79 (of 118)

Source assertions may not

propagate to all leaves

Low Power Intent

An IP Providers
Perspective

Soft IP Providers Low Power

Intent
A Soft IP provider need only declare four things:
1. The "atomic" power domains in the design

these can be merged but not split during implementation

2. The state that needs to be retained during

shutdown

with out prescribing how retention is controlled

3. The signals that need isolating high/low

with out prescribing how isolation is controlled

4. The legal power states and sequencing between

them

with out prescribing absolute voltages

Successive Refinement
Example
1.

UPF Constraints

IP provider needs to "identify" what is to be isolated with out

prescribing how:
set_isolation my_iso -domain my_pd \
-clamp_value 0

2.

UPF Configuration

System Level simulation guy needs to configure the logical power

controls with out having to specify the power supplies:
set_isolation -update my_iso -domain my_pd \
-isolation_signal CLAMP -isolation_sense high

3.

UPF Implementation

Finally the details of power supplies are then added during

implementation
set_isolation -update my_iso -domain my_pd \
-isolation_power_net VDDG -location parent

Or specify it all at the same time:

set_isolation my_iso -domain my_pd \
-clamp_value 0 \
-isolation_signal CLAMP -isolation_sense high \
Slide 110 (of 118)
-isolation_power_net VDDG -location parent

Controlling Clocks, Resets

and Power
VDD ( always on)

VDD (always on)

nPWR

WAKE- UP REQ
SLEEP REQ

VDD_SW

CLOCK ACK
( CLAMP _ACK)
(N _ RETAIN _ACK)

Power -Gated
Region PD

CLOCK
ENABLE

(N _ RESET _ACK)
N_ START _ACK

nRESET

N_ PWR_ACK

nCLAMP

S
y
n
c
h
r
o
n
i
z
e
r
s

CLOCK _REQ

Power Gating
Controller
State Machine

CLAMP _REQ
N _RETAIN_REQ
N _ RESET _REQ
N _ START _REQ
N_ PWR_REQ

SYSTEM CLOCK
VSS

Can use UPF inferred clamps to stop clocks and assert reset
Needs care to avoid timing issues

Better to use handshaking controlled by a simple state

machine
Facilitates design reuse and technology portability
Slide 113 (of 118)

Sequencing Clocks, Resets

and Power
Power down sequence:
Power up sequence:
1.
2.
3.
4.
5.

Stop the clocks

Apply isolation
Optionally save state
Assert reset
Remove power

CLOCK
N_CLAMP
SAVE
RESTORE

N_RESET
N_PWR

Slide 114 (of 118)

1.
2.
3.
4.
5.

Apply power
Remove reset
Optionally restore state
Remove isolation
Start the clocks

A Few Best Practices

Top

A1

Avoid non-contiguous power domains

B1

A2

B2

B3

Can lead to unwanted isolation cells

If in doubt, align power domains with logic hierarchy

Avoid using clock gating on both edges of the

clock
Need for specialised ICGs may limit choice of
implementation libraries

Avoid partial retention within a power domain

Unless the IP has been explicitly designed to support it.
User defined partial state retention will require complete
re-verification
No support for set_retention no retention in UPF-1.0
Slide 115 (of 118)

B4

Conclusion:

Power dissipation is the #1 limiter of design performance

Can be mitigated with advanced circuit design and optimization tools

Power management is a system problem

Power management strategy must be carefully considered from
architecture to silicon

Need to ease adoption of advanced low power techniques

Develop low power IP, tools & techniques (ARMs IEM & PMK)

UPF enables portability of low power intent

Provides ability to to compare and contrast a variety of implemention
Transistors
(and
strategies
Transistors
(andsilicon)
silicon)are
arefree.
free.Power
Poweris
isthe
theonly
onlyreal
reallimiter.
limiter.
Optimizing
for
frequency
and/or
may
neither.
Portable
across
EDA tools
andarea
supported
by commercial
Optimizing
for
frequency
and/or
area
mayachieve
achieve
neither.low power
Pat
libraries
PatGelsinger,
Gelsinger,Intel
Intel(DAC2004
(DAC2004Keynote)
Keynote)
Low power overlay to existing processor IP from ARM
Slide 116 (of 118)

References
Accellera
http://www.lpmm-book.org

Thank You!