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Subsystem Design Guide

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Subsystem Design Guide

Pcie

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Tejas CM

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AMBA based System for High Speed IP Validation

Hardware & Software Application Design Guide

AMBA based System for High Speed IP Validation

Hardware & Software Application Design Guide

Cadence Design Systems Page 1

Revision History
Version Date Author Remarks
th
0.1 7 Oct 2013 Yash Kothari 1. First Draft
th
0.2 18 Nov 2013 Yash Kothari 1. Added instructions on how-to-create
the system
th
1.0 15 Dec 2013 Yash Kothari 1. submitted
th
1.1 20 Feb Surabhi 1. converted to Cadence format

Cadence Design Systems Page 2

Table of Contents
Overview .....................................................................................................................................................................6
1 Introduction ........................................................................................................................................................7
2 Advanced Microcontroller Bus Architecture (AMBA) .........................................................................................8
2.1 History .......................................................................................................................................................8
2.2 Objectives and Features of AMBA Architecture ........................................................................................8
2.3 Various types of AMBA Protocols .............................................................................................................8
2.3.1 AXI Coherency Extensions (ACE) ........................................................................................................9
2.3.2 Advanced eXtensible Interface (AXI) ....................................................................................................9
2.3.3 Advanced High-performance Bus (AHB) ..............................................................................................9
2.3.4 Advanced Peripheral Bus (APB) ...........................................................................................................9
3 Soft Systems ................................................................................................................................................... 10
3.1 MicroBlaze .............................................................................................................................................. 11
3.2 Soft IP Cores .......................................................................................................................................... 11
4 Environment Development Kit (EDK) ............................................................................................................. 13
5 Xilinx Platform Studio (XPS) ........................................................................................................................... 15
5.1 Getting Started ................................................................................................................................................ 15
5.1.1 Base System Builder (BSB) ............................................................................................................... 15
5.1.2 XPS Graphical User Interface (GUI) .................................................................................................. 19
5.2 Generating and Implementing the System Design ......................................................................................... 23
5.2.1 Defining the Ports and UCF ............................................................................................................... 23
5.2.2 Adding IP Cores from IP Catalog ....................................................................................................... 24
5.2.3 Deleting an IP Core ............................................................................................................................ 24
5.2.4 Creating a Custom IP Peripheral ....................................................................................................... 24
5.3 XPS References ..................................................................................................................................... 25
6 Software Development Kit (SDK).................................................................................................................... 26
6.1 Some Important SDK Terminologies ...................................................................................................... 26
6.1.1 Workspace ......................................................................................................................................... 26
6.2 Working with SDK .................................................................................................................................. 27
6.2.1 SDK Graphical User Interface (GUI) .................................................................................................. 27
6.2.2 Creating a Workspace ....................................................................................................................... 28
6.2.3 Creating Projects in SDK ................................................................................................................... 29
6.2.4 Using XMD Console ........................................................................................................................... 29
6.2.5 GNU Debugger .................................................................................................................................. 30
6.3 References ............................................................................................................................................. 31
7 Generation of Sub-System Hardware - Design using XPS ............................................................................ 32
7.1 Creating base System using BSB .......................................................................................................... 32
7.2 Adding various Modules to the System Design ..................................................................................... 33
7.2.1 UART ................................................................................................................................................. 33
7.2.2 GPIO – LED ....................................................................................................................................... 34
7.2.3 GPIO – Switch ................................................................................................................................... 35
7.2.4 GPIO - Push Button ........................................................................................................................... 35
7.2.5 GPIO - Generic Bus ........................................................................................................................... 36
7.2.6 IIC/I2C ................................................................................................................................................ 37
Cadence Design Systems Page 3
© 2013 Cadence Design Systems Inc. All rights reserved. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems Inc. All others
are properties of their respective holders. Cadence Design Systems products are subject to continuous development and the Company reserves the right to
change, delete, or modify specifications and features without notice
AMBA based System for High Speed IP Validation
Hardware & Software Application Design Guide
7.2.7 Timer .................................................................................................................................................. 39
7.2.8 Interrupt Controller (INTRC)............................................................................................................... 39
7.2.9 BRAM and BRAM Controller.............................................................................................................. 40
7.2.10 DMA Controller .............................................................................................................................. 40
7.2.11 DDR2 Controller ............................................................................................................................ 41
7.2.12 PCIe Controller .............................................................................................................................. 42
8 Compiling Sub-System Design generated using XPS .................................................................................... 43
9 Appendices ..................................................................................................................................................... 47
9.1 Appendix A - Pin Map for Zeus Board.................................................................................................... 47
9.2 Appendix B - Pin Map for HTG Board .................................................................................................... 50
10 References ...................................................................................................................................................... 53

Cadence Design Systems Page 4

List of Figures

Figure 2.1.1: IP Test Setup ........................................................................................ Error! Bookmark not defined.

Figure 4.1.1: Termination Enable During Prepare at G1B Rate ................................ Error! Bookmark not defined.
Figure 4.1.2: Termination Disable after Burst at G1B Rate ...................................... Error! Bookmark not defined.
Figure 4.1.3: Termination Enable During Prepare at G2B Rate ................................ Error! Bookmark not defined.
Figure 4.1.4: Termination Disable after Burst at G2B Rate ....................................... Error! Bookmark not defined.
Figure 4.2.1.1: Calibrated EYE at RX pad for V DIF_ACC_TEST_G1A ................................ Error! Bookmark not defined.
Figure 4.2.2.1: Total Jitter Mask-Mode G1A ............................................................. Error! Bookmark not defined.
Figure 4.3.1.1: Calibrated EYE at RX pad for V DIF_ACC_TEST_G2A ................................ Error! Bookmark not defined.
Figure 4.3.2.1: Total Jitter Mask-Mode G2B ............................................................. Error! Bookmark not defined.
Figure 4.3.1.1: Calibrated EYE at RX pad for V DIF_ACC_TEST_G3B ................................ Error! Bookmark not defined.
Figure 4.4.2.1: Total Jitter Mask-Mode G3A ............................................................. Error! Bookmark not defined.
Figure 5.2.1: Package Drawing ................................................................................. Error! Bookmark not defined.
Figure 5.2.2: Package Footprint ................................................................................ Error! Bookmark not defined.

Cadence Design Systems Page 5

Overview
The ARM Advanced Microcontroller Bus Architecture (AMBA) is a widely used interconnection bus standard for SoC
(Silicon on Chip) Design. AMBA supports a rich set of bus protocols like AXI, APB, AHB, etc. which is used to facilitate
high-speed pipelined data transfers within a SoC. AMBA Architecture has gone far beyond microcontroller devices, and
is now widely used on a range of ASIC and SoC parts including application processors used in modern portable mobile
devices like smart phones. The primary reason for this is it is targeted at high performance; high clock frequency system
designs and includes features like:
• Separate address/control and data phases
• Support for unaligned data transfers using byte strobes
• Burst based transactions with only start address issued
• Issuing of multiple outstanding addresses with out of order responses
• Easy addition of register stages to provide timing closure
which make it suitable for high speed sub-micrometer interconnect.
MicroBlaze is a soft processor core from Xilinx and is designed so as to be implemented on a FPGA and replicate all the
functionalities of a system processor. Many aspects of the MicroBlaze are user configurable; cache size, pipeline depth
(3-stage or 5-stage), embedded peripherals, memory management unit, and bus-interfaces can be customized.
MicroBlaze uses the AMBA AXI4 protocol for communication with various devices connected to it.
This document describes in detail about the designing of “AMBA based Systems for High Speed IP Validation” and their
Application. These systems are soft-systems meaning that the system design is programmed on to a FPGA, which acts
as a pseudo embedded system for the validation of various AMBA compliant IP. These IP’s are integrated to the SoC
and the interconnect bus signals (AMBA bus signals) are used to facilitate data and command signals to and from the IP.
Also, key processor instructions which are rarely used but more expensive to implement in hardware can be selectively
added/removed to such systems (i.e. multiply, divide, and floating-point ops.) This customization enables a developer to
make the appropriate design tradeoffs for a specific set of host hardware and application software requirements.
Xilinx's EDK (Embedded Development Kit) is the development package for building MicroBlaze based embedded
processor systems on Xilinx FPGAs.

This document is divided into five main sections -

• Section A: describes the concept of AMBA based Systems, highlights on the key features of such a system and in
brief elaborates on some of the key terminologies.
• Section B: describes about the various EDK softwares used for generating such a system. It also describes about
the softwares required to make use of such a System.
• Section C: describes in detail about the steps to generate an “AMBA Based System/Sub-system”. It also mentions in
detail about the various modules which are commonly used in a Sub-system.
Towards the end the Appendix mentions about the key terminologies used throughout the document and supporting
information like the “pin map” and Hardware connections to be made for implementing the System Design on Zeus
Board.

Cadence Design Systems Page 6

1 Introduction
The evolution and up gradation of Digital Electronics has led FPGA based validation of Controller IP’s. Most of the Post
Silicon Validation’s are performed using FPGA’s, which have become an integral part of the Silicon Validation Systems.
The popularity in the use of such PFGA based Validation technologies has resulted in development of Standard Logical
Functions termed as “Soft IPs”. These soft IP blocks are designed for replicating the functionality and achieve results
similar to those of actual IP’s/ embedded systems.

The terminology “Soft System” refers to systems whose design can be programmed on to a FPGA and the FPGA can be
made to replicate the behavior of an actual System. Soft System’s comprise of soft Processors, soft IP cores and other
Logical blocks. Such soft systems can be used for validating other Hard IP’s by generating an appropriate environment
for it.

This document presents the approach required to generate such a soft system. It also highlights on some of the
important blocks - their functionality and the method by which they can be instantiated while creating the soft system.
Here after “Soft Systems” will be referred to by the generic term “Systems” in the remaining document unless
otherwise needed to be specified.

These systems can be modified to have input/output test interface for IP Validation. The major category of IP’s which can
be verified by such systems include Controller IP’s mainly because they are digital IP’s and can be instantiated along
with the System on the FPGA itself. Hard IP cores can also be checked by appropriately mapping the signals from FPGA
pins to the input/output signals of the IP.

Xilinx’s Environment Development Kit (EDK) provides two platforms - Xilinx Platform Studio (XPS) and Xilinx Software
Development Kit (SDK). The former can be used to create the Hardware Design to be ported on to the FPGA, while the
later is used to create the software application for System. XPS comes with a list of soft IP cores which can be used as
logical blocks to provide functionality to the system. SDK helps in sending commands to the processor for performing
various functions - like data read/write to the IO’s, adding delays before the data is transferred, processing interrupts, etc.
It provides a simple user friendly interface to create and develop a simple C code containing the processor commands
which can be programmed to the Boot RAM for system operation.

Cadence Design Systems Page 7

2 Advanced Microcontroller Bus Architecture (AMBA)

The Advanced Microcontroller Bus Architecture (AMBA) is used as the on-chip bus in system-on-a-chip (SoC) designs.
Since its inception, the scope of AMBA has gone far beyond microcontroller devices, and is now widely used on a range
of ASIC and SoC parts including applications processors used in modern portable mobile devices like smart phones.

AMBA is a registered trademark of ARM Limited, and is an open standard, on-chip interconnect specification for the
connection and management of functional blocks in a System-on-Chip (SoC). It facilitates right-first-time development of
multi-processor designs with large numbers of controllers and peripherals.

2.1 History
AMBA was introduced by ARM in 1996. The first AMBA buses were Advanced System Bus (ASB) and Advanced
Peripheral Bus (APB). In its 2nd version, AMBA 2, ARM added AMBA High-performance Bus (AHB) that is a single
clock-edge protocol. In 2003, ARM introduced the 3rd generation, AMBA 3, including AXI to reach even higher
performance inter-connect and the Advanced Trace Bus (ATB) as part of the CoreSight on-chip debug and trace
solution. In 2010 the AMBA 4 specifications were introduced starting with AMBA 4 AXI4, then in 2011 extending system
wide coherency with AMBA 4 ACE. In 2013 the AMBA 5 CHI (Coherent Hub Interface) specification was introduced, with
a re-designed high-speed transport layer and features designed to reduce congestion. These protocols are today the de
facto standard for 32-bit embedded processors because they are well documented and can be used without royalties.

2.2 Objectives and Features of AMBA Architecture

The important aspect of a SoC is not only which components or blocks it houses, but also how they interconnect. AMBA
is a solution for the blocks to interface with each other.

The objective of the AMBA specification is to:

• Facilitate right-first-time development of embedded microcontroller products with one or more CPUs, GPUs or
signal processors,
• Be technology independent, to allow reuse of IP cores, peripheral and system macro cells across diverse IC
processes,
• Encourage modular system design to improve processor independence, and the development of reusable
peripheral and system IP libraries
• Minimize silicon infrastructure while supporting high performance and low power on-chip communication.

2.3 Various types of AMBA Protocols

The AMBA specification defines an on-chip communications standard for designing high-performance embedded
microcontrollers.

The AMBA 4 specification defines following buses/interfaces:

• AXI Coherency Extensions (ACE)
• AXI Coherency Extensions Lite (ACE-Lite)
• Advanced eXtensible Interface 4 (AXI4)
• Advanced eXtensible Interface 4 Lite (AXI4-Lite)
• Advanced eXtensible Interface 4 Stream (AXI4-Stream v1.0)
• Advanced Trace Bus (ATB v1.1)
• Advanced Peripheral Bus (APB4 v2.0)

AMBA 3 specification defines four buses/interfaces:

• Advanced eXtensible Interface (AXI3 or AXI v1.0)
• Advanced High-performance Bus Lite (AHB-Lite v1.0)
• Advanced Peripheral Bus (APB3 v1.0)
• Advanced Trace Bus (ATB v1.0)
Cadence Design Systems Page 8
© 2013 Cadence Design Systems Inc. All rights reserved. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems Inc. All others
are properties of their respective holders. Cadence Design Systems products are subject to continuous development and the Company reserves the right to
change, delete, or modify specifications and features without notice
AMBA based System for High Speed IP Validation
Hardware & Software Application Design Guide
AMBA 2 specification defines three buses/interfaces:
• Advanced High-performance Bus (AHB)
• Advanced System Bus (ASB)
• Advanced Peripheral Bus (APB2 or APB)

AMBA specification (First version) defines two buses/interfaces:

• Advanced System Bus (ASB)
• Advanced Peripheral Bus (APB)

The timing aspects and the voltage levels on the bus are not dictated by the specifications.

2.3.1 AXI Coherency Extensions (ACE)

ACE, defined as part of the AMBA 4 specification, extends AXI with additional signaling introducing system wide
coherency. This system coherency allows different processor clusters to share memory and enables technology like
ARM's big LITTLE processing

2.3.2 Advanced eXtensible Interface (AXI)

AXI, the third generation of AMBA interface defined in the AMBA 3 specification, is targeted at high performance, high
clock frequency system designs and includes features that make it suitable for high speed sub-micrometer interconnect:

• separate address/control and data phases

• support for unaligned data transfers using byte strobes
• burst based transactions with only start address issued
• issuing of multiple outstanding addresses with out of order responses
• easy addition of register stages to provide timing closure.

2.3.3 Advanced High-performance Bus (AHB)

AHB is a bus protocol introduced in Advanced Microcontroller Bus Architecture version 2 published by ARM. In addition
to previous release, it has the following features:

• single edge clock protocol

• split transactions
• several bus masters
• burst transfers
• pipelined operations
• single-cycle bus master handover
• non-tristate implementation
• large bus-widths (64/128 bit)

A simple transaction on the AHB consists of an address phase and a subsequent data phase (without wait states: only
two bus-cycles). Access to the target device is controlled through a MUX (non-tristate), thereby admitting bus-access to
one bus-master at a time.

AHB-Lite is a subset of AHB formally defined in the AMBA 3 standard. This subset simplifies the design for a bus with a
single master.

2.3.4 Advanced Peripheral Bus (APB)

APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals. This bus has
an address and data phase similar to AHB, but a much reduced, low complexity signal list (for example no bursts). It has
to support 32bit and 66 MHz signals.

Cadence Design Systems Page 9

3 Soft Systems
System on a chip or system on chip (SoC or SOC) is an integrated circuit (IC) that integrates all components of a
computer or other electronic system into a single chip. A typical application is in the area of embedded systems. SoC’s
can be implemented as an application-specific integrated circuit (ASIC) or using a field-programmable gate array
(FPGA). A System on Chip (SoC) design when implemented on a FPGA is referred to as a Soft System.

A Soft system generally comprises of soft processors and soft IP cores which are used to generate a fully functional
Embedded System/ SoC design. The design is either generated by using the standard Soft IP Cores available or by
writing a custom RTL. The essential components of a Soft System are –

• Soft processor
• Inter-connect Bus
• Memory Blocks
• Timer/ Interrupt Controller

Depending on the functionality required from the system, other soft IP cores which perform the dedicated task are added
to the system. Figure 1 shows the block diagram of a basic MicroBlaze based System.

Figure 1: Block Diagram of a Basic MB based System Design

Cadence Design Systems Page 10

3.1 MicroBlaze
A soft microprocessor (also called softcore microprocessor or a soft processor) is a microprocessor core that can be
wholly implemented using logic synthesis. It can be implemented via different semiconductor devices containing
programmable logic (e.g., ASIC, FPGA, CPLD), including both high-end and commodity variations.

The MicroBlaze is a soft processor core designed for Xilinx FPGAs from Xilinx. As a soft-core processor, MicroBlaze is
implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs. Most systems, if they use a soft
processor at all, only use a single soft processor. The MicroBlaze has a versatile interconnect system to support a
variety of embedded applications. MicroBlaze's primary I/O bus, the CoreConnect PLB bus, is a traditional system-
memory mapped transaction bus with master/slave capability. A newer version of the MicroBlaze, supported in both
Spartan-6 and Virtex-6 implementations, as well as the 7-Series, supports the AXI specification. Xilinx's EDK (Embedded
Development Kit) is the development package for building MicroBlaze embedded processor systems in Xilinx FPGAs.

In the document, MB is used as the abbreviation for MicroBlaze. Please note that this is not an industrially accepted
(standard) abbreviation.

3.2 Soft IP Cores

A semiconductor intellectual property core, IP core, or IP block is a reusable unit of logic, cell, or chip layout design that
is the intellectual property of one party. IP cores can be used as building blocks within ASIC chip designs or FPGA logic
designs. IP cores can be of two types - Soft IP Core or Hard IP Core.

Soft IP Cores are IP cores that are typically offered as synthesizable RTL. Synthesizable cores are delivered in a
hardware description language such as Verilog or VHDL. Generally, IP cores are delivered to chip makers as RTL permit
chip designers to modify designs (at the functional level). IP cores are also sometimes offered as generic gate-level
netlists. An IP core implemented as generic gates is portable to any process technology. Both netlist and synthesizable
cores are called "soft cores", as both allow a synthesis, placement and route (SPR) design flow.

Xilinx provides a wide range of Soft IP Cores along with its Environment Development Kit. These IP cores are designed
in a way to be compatible with MicroBlaze processor and can be directly used in the system design. They are compatible
in the sense that they also support AXI specifications like MicroBlaze and thus can be directly connected to the
processor by the inter-connect Bus.

Cadence Design Systems Page 11

Some examples of Soft IP Cores available by Xilinx for use in its EDK environment are –

• AXI to PCIe Bridge

• DDR Controller
• DMA Controller
• Timer
• Interrupt Controller
• GPIO’s
• UART

The user can make use of the various IP’s available to design a complex and a fully functional SoC. Figure 2 gives the
Block Diagram of AMBA based System.

Figure 2: Block Diagram of an AMBA based System for High Speed IP Validation

Cadence Design Systems Page 12

4 Environment Development Kit (EDK)

The Xilinx Embedded Development Kit (EDK) is a suite of tools and Intellectual Property (IP) that enables you to design a
complete embedded processor system for implementation in a Xilinx Field Programmable Gate Array (FPGA) device.

Embedded systems are complex. Getting the hardware and software portions of an embedded design to work are
projects in themselves. Merging the two design components so they function as one system creates additional
challenges. Add an FPGA design project to the mix, and the situation has the potential to become very complicated
indeed. Xilinx EDK environment helps the user create custom designs without putting any extra efforts. It takes care of
the basic connections between various IP cores and provides the user with an interactive GUI to make the design
process easy and reduce it complicacy.

The Embedded Development Kit (EDK) is a suite of tools and IP that you can use to design a complete embedded
processor system for implementation in a Xilinx FPGA device. The various tools which come in the EDK package are –

i. Xilinx Platform Studio (XPS):

Xilinx Platform Studio (XPS) is the development environment used for designing the hardware portion of your
embedded processor system. You can run XPS in batch mode or using the GUI. XPS is used for embedded
processor hardware system development. Specification of the microprocessor, peripherals, and the
interconnection of these components, along with their respective detailed configuration, takes place in XPS.

ii. Software Development Kit (SDK):

The Software Development Kit (SDK) is an integrated development environment, complementary to XPS, that is
used for C/C++ embedded software application creation and verification. SDK is built on the Eclipse open-source
framework.

Other EDK components include:

• Hardware IP for the Xilinx embedded processors
• Drivers and libraries for the embedded software development
• GNU compiler and debugger for C/C++ software development targeting the MicroBlaze™ and PowerPC®
processors
• Documentation
• Sample projects

EDK is designed to assist in all phases of the embedded design process.

Cadence Design Systems Page 13

1
Figure 3: Basic Embedded System Design Process Flow

Figure 3 shows the simplified flow for an embedded system design.

Typically, the ISE development software is used to add an Embedded Processor source, which is then created in XPS
using the Base System Builder -
1. XPS is used for embedded processor hardware system development. Specification of the microprocessor,
peripherals, and the interconnection of these components, along with their respective detailed configuration.
2. SDK is mainly used for the purpose of Embedded System Software development. SDK is also available as a
standalone application.
3. The correct functionality of the hardware platform can be verified by running the design through a Hardware
Description Language (HDL) simulator. Xilinx simulator ISim can also be used to simulate embedded designs. It
supports three types of simulations for embedded systems - Behavioral, Structural and Timing-accurate. The
design can be simulated either through XPS or ISE Project Navigator.

After configuring the bitstream with the embedded design, the Executable and Linkable Format (ELF) file can be
downloaded and debugged from the software project from within SDK.

1. The image is taken from EDK Concepts, Tools and Techniques, Xilinx - UG683 (v13.4), 2012

Cadence Design Systems Page 14

5 Xilinx Platform Studio (XPS)

As mentioned From the XPS software, you can design a complete embedded processor system for implementation within a
Xilinx FPGA device. The chapter presents the various functionalities of XPS and the ways in which it can be used to create
such a system design.

5.1 Getting Started

5.1.1 Base System Builder (BSB)

The Base System Builder (BSB) is a wizard in the XPS software that quickly and efficiently establishes a working design.
The BSB wizard should be used to appropriately configure the processor, insatiate the desired number of processors, IO
interfaces and to add internal peripherals and blocks like Memory, Timer, etc. The Base System configures the system
according to the FPGA selected.

Figure 4: XPS Welcome Screen

Figure 4 shows the XPS welcome screen. To begin with the System design, the BSB wizard can be used to generate a
Base System. Once the Base system is generated various available IP cores or even User generated IP can be added to
the System design.

Cadence Design Systems Page 15

1. Open XPS  On the Welcome Screen select “Create New Project using BSB Wizard”

It opens a sub - window as shown in Figure 5.

Figure 5: BSB Wizard - Browse Project Folder

Cadence Design Systems Page 16

NOTES:
1. BSB Wizard creates all the Files in the Folder selected, like ISE it doesn’t create another folder to store XPS files.
2. Selecting BSB settings file or Project Peripheral Repository is not necessary and can be left blank.

Figure 6: BSB Wizard - Select Evaluation Platform

3. Select “Create a System for a Custom Board”  In Board Configuration specify Architecture, Device,
Package, Speed Grade, Reference Clock Frequency and Reset Polarity.

NOTES:
1. Be careful while selecting Reset Polarity as it can result in MB reset errors while using SDK.
2. Figure indicates the settings for Zeus Board.

Cadence Design Systems Page 17

Figure 7: BSB Wizard - IO and Peripheral Configuration Window

5. Set Processor Frequency  50 MHz (for nominal operation), Select processor Memory size  64 kB (depends
on application software code & system peripherals)
6. Add Peripherals to the System  Add Device  Configure the values of peripheral in the “Included Peripherals for
microblaze_0” section (Eg: Data Width, baud Rate, INTR enable, Parity, etc.). Timer and BRAM block can be added
from Internal Peripherals Section  Click Finish (Opens XPS Main Window with the Base System Design shown in
Figure 8)

NOTES:
1. There are only a limited no of peripherals specified here. Once this base system is developed, advanced & complex IP
cores (like DMA Controller, DDR2 Controller, etc.) and User IP’s can be added from XPS.
2. One device can be instantiated only once in the BSB wizard.
For Eg: If 2 IIC Controllers are required then only one can be added from BSB wizard, the other can be added using the IP
Catalog available in the XPS window.
2. Click on “More Info” to get more information about the details about various options and device configurations.
3. Figure indicates the settings for Zeus Board.

Cadence Design Systems Page 18

5.1.2 XPS Graphical User Interface (GUI)

Figure 8 represents the XPS main window. This is the Graphical User Interface (GUI) to help the user generate the
system design easily and conveniently. XPS can also be used in Batch Mode in which the required files are to be given
to it to generate the required Embedded System design. The various Panels and Tabs visible in XPS GUI are explained
in detail below.

Figure 8: XPS - Main Window

Cadence Design Systems Page 19

1. XPS Toolbar: Contains various dropdown menus for changing various settings/ options related to the XPS
embedded System Design.

2. System Assembly View: Displays the information regarding the various blocks instantiated in the Embedded
System Design.

The System Assembly View Tab comprises of three sub-tabs –

3. Bus Interface: List the various IP blocks instantiated in the system design and their bus connections (sometimes
when adding blocks from the IP catalog, connections to the various interconnects are not done by the software
and might have to be manually assigned)

4. Ports: Lists all the IO ports of the IP blocks instantiated in the system design

5. Addresses: List the Base Address and High Address for each IP block (these addresses are used by the
processor to send commands to the individual IP block).

The other two tabs besides the System Assembly View Tab are –

6. Design Summary: Displays the System Design Summary like Warning and Errors occurred at various phases of
the system design implantation, timing violations and other reports generated during system implementation.
Figure 9 shows the design summary tab.

Figure 9: XPS - Design Summary Tab

Cadence Design Systems Page 20
© 2013 Cadence Design Systems Inc. All rights reserved. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems Inc. All others
are properties of their respective holders. Cadence Design Systems products are subject to continuous development and the Company reserves the right to
change, delete, or modify specifications and features without notice
AMBA based System for High Speed IP Validation
Hardware & Software Application Design Guide

7. Graphical Design View: Displays the Graphical View of the various modules instantiated in the system design.
Figure 10 shows the Graphical Design View Tab.

Figure 10: XPS - Graphical Design View Tab

8. Project: It displays the information related to project like project mhs files, ucf file, board options, etc. (Figure 11
gives a snapshot of the Project Tab)

9. IP Catalog: It contains an entire catalogue of the IP Soft cores available by Xilinx for creating Embedded System
Design. It also includes the list of Custom User IP’s created at the bottom. (Figure 12 gives a snapshot of the IP
Catalog Tab)

Cadence Design Systems Page 21

Figure 11: XPS - Project Tab Figure 12: XPS - IP Catalog Tab

Apart from these there are two more panels which are important while using the XPS GUI-

Navigation Panel: It is situated at the extreme left of the XPS GUI. It contains the various steps to be followed while
generating and implementing the system design. It contains tabs like Run DRC, Generate Netlist, Generate
Bitstream, etc. which can be directly used to perform that particular task.

Console Panel: It is situated at the bottom of the XPS GUI. It displays the various commands being executed by the
GUI to generate and implement the system design. Warnings and Errors display only the warning and errors obtained
during system generation.

NOTES:
1. Clicking on Generate Bitstream automatically follows the previous two steps of Running DRC and generating the Netlist,
so the intermediate steps can be avoided.

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5.2 Generating and Implementing the System Design

5.2.1 Defining the Ports and UCF

After generating a Base System Design using BSB Wizard, the ports are to be defined as either input or output and the
internal connections between various modules of the system are also to be done. The steps below indicate how to define
the ports and apply the user constraints to the system inputs and outputs.

1. Go to System Assembly View  Bus Interfaces  Connect AXI Interconnect Bus to various modules using
the AXI bus

NOTE: The modules added by the BSB wizard are by default connected to the AXI interconnect.

2. Go to System Assembly View  Ports  Connect the various ports of each module to their appropriate signal,
if a signal is input/output for the system then make it External (like Clock, Reset)

NOTE: Make the following changes in the External Ports for single ended system (input) clock –

a) Delete the CLK_N & CLK_P port.

b) Select “clock_generator module”  Click on “CLK_IN” port  From Drop down menu choose “Make port External”
 Give an appropriate Name (Eg. CLK)
c) “CLK_IN” (CLK) port appears in the External Ports  Enter frequency as 100,000,000 (100 MHz)
d) Change the names of other external ports depending on their names in the ucf file.
e) Check for little and big endiannes of vector signals.

3. Go to Project Tab  Open *.ucf file  Add user constraints, timing constraints and FPGA Board pin map to this
ucf file

NOTE: By default the clock period constraint is added by the software

4. Verify the design in the Graphical Design View Tab

5. In Navigation Panel  Click on “Generate Bitstream” to obtain the bit file which can be used to program the
FPGA with the system design.

6. In Toolbar go to Project  Project Options  Design Flow 

a. HDL  Select Verilog
b. Simulation Test Bench  Generate Testbench Template
c. If External Memory present  Enable External Memory Simulation

7. Click on Export Design to SDK

8. Click on Generate HDL files (these files are required to work with ISIM)

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5.2.2 Adding IP Cores from IP Catalog

The IP catalog provides a wide range of IP soft cores to choose from for system design. The following steps indicate the
process to add a an IP –

1. Go to IP Catalog Panel  Choose/ Search required IP core  Right click: Add IP (or double click on the IP)

2. Notification pops up: Add IP instance to design  Click Yes

3. Opens the IP core configuration window  Customize the IP core according to the requirements  Click Ok

4. Notification pops up: Instantiate and Connect IP  Select processor instance Select MicroBlaze (If you
want to connect your IP to microblaze or select the other option of connection by user)  Ok

5.2.3 Deleting an IP Core

To delete an IP core from the system design -

Right Click on IP core to delete in the System Assembly View  Delete Instance  Delete IP and all its Connections

5.2.4 Creating a Custom IP Peripheral

XPS also provides the user with the option to generate a custom user IP and connect it to the system design. The user
can add the IP in the form of an RTL. He steps indicate the procedure to generate a custom IP -
1. In XPS Toolbar  Hardware  Create or Import Peripheral (A existing Custom generated IP core can also be
imported to XPS)

2. Create Template of a New peripheral  Next  To an EDK Repository  Browse to the XPS working
directory  Next  Specify the Name and Version  Next  Select the Type of Bus Protocol for the User IP
to follow  Next  IPIF Services  Select Master or Slave depending on the requirement (No need to include
data phase timer or user logic soft register unless needed)  Next

3. IP Interconnect  Select all BUS2IP ports  Next  Peripheral Simulation Support  Select if you want BFM
simulation platform (generally not required)  Next  Peripheral Implementation Support  Select whatever is
necessary  Next  Review the IP details  Finish

After generation of the IP core, modifications are required in its MPD file and VHD file according to the changes required
for the User IP. Some example for each is given below 

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Eg: PORT DUT_AXI_AWREADY = “ “, DIR = I, IO_IF = axi_slave_dut, IO_IS =axi_awready

Syntax:
PORT <PortName> = “ “, DIR = <I/ O>, IO_IF = <Specify IO_IF Name>, IO_IS = <Specify what IO is>

2. Specify the IO Interface at the beginning of the MPD document as shown below –
3.
Eg: IO_INTERFACE IO_IF = axi_slave_dut, IO_TYPE = XIL_AXI_SLAVE_V1

Syntax:
IO_INTERFACE IO_IF = <Specify IO_IF Name>, IO_TYPE = XIL_<Specify some IO type name>_V1

NOTE:
1. Any IO_IF name used in the Port description should be explicitly initialized in the beginning of the MPD File.
2. If MPD File is not edited the Custom User Interface Ports are not displayed when the IP is added to the System
design.

VHD Files modifications

1. Open the generated IP VHD file. Make necessary changes as per the IP and save them.

2. After making the Customizations to User IP (both VHD and MPD)  Go to Toolbar  Project  Rescan user
Repositories

To add the custom User IP core –

3. Go to project Tab  Project Local Pcores  User Pcores Repositories  Add the Custom IP core

NOTE:
1. Ports added in MPD should also be added to the VHD file.

2. Before creating an IP core make sure the IP is not available in the already available IP Catalog

5.3 XPS References

For Basic XPS: Reference 1
For Advanced XPS:
i. Creating Custom IP’s & Adding IP cores: Reference 2
ii. Editing MPD files: Reference 3
iii. Editing MHS files: Reference 3

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6 Software Development Kit (SDK)

Embedded System requires software for its operation; this software is commonly known as Embedded Software. Embedded
software is computer software, written to control machines or devices that are not typically thought of as computers. It is
typically specialized for the particular hardware that it runs on and has time and memory constraints. A precise and stable
characteristic feature is that no or not all functions of embedded software are initiated/controlled via a human interface, but
through machine-interfaces instead. Such software development requires use of a cross compiler, which runs on a computer
but produces executable code for the target device. Debugging requires use of an in-circuit emulator, JTAG or SWD.

Xilinx Software Development Kit is another tool which comes along with the EDK is used to develop embedded software
application projects. It is a complementary program to XPS which generates the Embedded System, and SDK is used to
develop the Embedded Software for the hardware platform developed using XPS.

6.1 Some Important SDK Terminologies

6.1.1 Workspace

Workspace is the SDK working Directory. On a computer, it is a folder where all your SDK project files will be saved after you
generate those using XPS. After opening SDK (either after Exporting the Design from XPS or invoking it separately), a
notification pops up asking for workspace directory. Figure 13 shows the Workspace Launcher notification prompt.

Figure 13: SDK - Workspace Launcher

One SDK browser can open only one SDK workspace. Switching between various Workspace can be done if required.
Multiple workspaces can be created to more easily manage multiple software versions.

NOTE:
1. After opening SDK the workspace launcher might not be shown and it might open the SDK GUI directly (This might be
because the previous user might have checked on “Use this as default and don’t ask again”). The work around for this
is to open one more SDK while this is open and then change the workspace as SDK cannot open same workspace in
two SDK windows.

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6.2 Working with SDK

6.2.1 SDK Graphical User Interface (GUI)

Figure 14 shows the SDK Main Window. The various Panels, Sections and Toolbar options are explained in detail.

The SDK window is mainly divided into three sections (as shown in Figure 14) –

1. Project Explorer: Mentions all the Projects and Project Files available in the current SDK workspace. A blue color
folder indicates the project is closed, whereas a yellow color open folder indicates the project is open and currently
SDK is using its data.

2. System Design: Shows the information contained in the various system hardware files and other related project files.
Double click on a file in the Project Explorer to open it.

3. XMD Console: Used to send XMD commands to MicroBlaze. User can control the processor from the XMD console.

The SDK window also comprises of some other panels –

4. Console: It displays the SDK commands being executed while performing various tasks, along with warnings and
error message.

5. SDK Toolbar: Contains various dropdown menus for changing various settings/ options related to the SDK project

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Figure 14: SDK - Main Window GUI

6.2.2 Creating a Workspace

The following steps should be followed to create a new workspace –

1. Open Windows Explorer  Go to Working Directory Folder  Create new Folder for SDK Workspace

2. Open SDK  It will launch the Workspace Launcher  Select the Workspace Directory  Click Create Workspace

NOTE:

1. It might happen after opening SDK the workspace launcher might not be shown and it might open the SDK GUI
directly (This might be because the previous user might have checked on “Use this as default and don’t ask again”).
The work around for this is -
• Open SDK  opens SDK with previous directory (this window should already be open)
• Launch another SDK application  Notification is displayed “Cannot create or open workspace”  Click OK 
Browse to the appropriate Workspace Folder Location  Press OK (opens up SDK with the new workspace) 
Close the previous browser and work with the recently launched SDK application.

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6.2.3 Creating Projects in SDK

SDK can be used to generate various application software files like a simple test case (Hello World) or complex
peripheral test application softwares. Before creating any application files, SDK requires the system hardware files; they
can be imported into SDK by “Exporting the design from XPS or ISE after synthesis”.

Follow the steps to generate any Application C Project in SDK –

1. Go to SDK Toolbar  File  New  Xilinx C project (for older versions) / Application project

2. If you select Xilinx C project  Select from given templates or select Create a New Blank C project  Specify
the Name  Click Create

3. If you select Application Project  Specify the Name  Select from given templates  Click Finish

NOTE:
1. Generally HelloWorld.c or Testperipheral.c projects are created to check the functioning of the system. Modifications
are made to them so as to generate the embedded software.

6.2.4 Using XMD Console

XMD console is used to send commands to MicroBlaze through the Xilinx JTAG Chain. XMD console can be used to
program FPGA with the system design and communicate with the processor to send commands to the various blocks
connected to it. The following commands can be used to communicate with MicroBlaze.

1. Syntax: fpga -f <bit_file>.bit

Description: To program FPGA with the Bitsream generated from XPS. Download.bit file is required to program the
FPGA properly (it includes system.bit and the bootloop file). Simpler way is to follow this - In SDK toolbar  Go to
Xilinx Tools  Program FPGA

NOTE:
File download.bit can be generated in the following way -
In XPS, toolbar, follow these 2 steps to get the download.bit file –
1. Project  Select elf file  Implementation elf File & Simulation elf file (keep both as “use bootloop”)
2. Device Configuration  Update Bitstream
The download.bit is generated in the following folder – {XPS System Folder}  implementation

But, the SDK folder wont contain this file. The work around for this without connecting a Hardware Platform (or JTAG) is
–
1. In SDK tool bar  Xilinx Tools  Program FPGA  It shows a fail message (Click OK)
2. Right Click on {Project}_hw_platform  Refresh

2. Syntax: connect mb mdm

Description: To connect MB with the software via JTAG interface.

NOTE:
1. After executing the command connect mb mdm if the XMD console displays an error or warning saying “MicroBlaze
is under Reset” or error message displaying memory stalled at some address, then check your system design and
especially the type of Reset (Active Low or Active High)

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Description: Download the application file. This file is created from the C code written by the user. After modification of
C file (of Hello World program/ Test peripheral program), SDK automatically creates an elf file. Search it in the
system_hello_world or system_hello_world_bsb folder. The application file is stored in the BRAM memory connected
to Microblaze via LMB bus.

4. Syntax: run

Description: Run the application file on the system.

5. Syntax: stop

Description: Stop the application file from performing further task through MicroBlaze.

6. Syntax: reset

Description: Reset MicroBlaze.

7. Syntax: mrd <peripheral_address>

Description: Read the value at the peripheral address specified (Base Address + offset). Peripheral address should be a
hex value and can be looked up in XPS: Go to System Assembly View  Go to Address Panel (Lists all the Peripheral
base and High Addresses, Register offset of individual IP’s should be referred in the IP Core User Guide)

8. Syntax: mwr <peripheral_address> <data>

Description: Writes the value to the peripheral address specified (Base Address + offset). Peripheral address should be
a hex value and can be looked up in XPS: Go to System Assembly View  Go to Address Panel (Lists all the
Peripheral base and High Addresses, Register offset of individual IP’s should be referred in the IP Core User Guide)
The XMD console can be invoked as a standalone without opening SDK. The following are the steps to be followed to
use the XMD console in standalone mode –

“Open ISE Command Prompt  Navigate to SDK Workspace Directory  Go to System_hw_platform Folder  Type
xmd to invoke the XMD console  Program the FPGA by selecting the appropriate bitstream file  Execute other XMD
commands to check the functionality  Type exit to come out of XMD console”.

6.2.5 GNU Debugger

Then GNU Debugger is a tool included in SDK which can be used to debug the embedded system design and software
for possible errors. It can be used to execute commands in the C code step by step or monitor the program at
breakpoints. These breakpoints can be added by the user in the C code. To open the GNU debugger: Go to SDK
Toolbar  Window  Open Perspective  Debug.

Figure 15 displays the GNU Debugger window. Further information on the use of GNU Debugger can be obtained from
Reference 2.

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Figure 15: SDK - GNU Debugger

6.3 References
For Basic EDK: Reference 1
For Advanced EDK:
i. XMD Console and Commands: Reference 2
ii. GNU Debugger: Reference 2

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7 Generation of Sub-System Hardware - Design using XPS

The Sub - system hardware design is created using Xilinx XPS tool. A sub-system design begins with a simple Base
System developed using the BSB wizard and then later complex IP blocks are added. This chapter would explain in
detail the procedure to instantiate the corresponding blocks and their respective connections which are to be made for
the block to function correctly.

7.1 Creating base System using BSB

The procedure to generate the base system design has already been explained in Section 5.1.1.

Figure 7 shows the IO Configuration window of the BSB wizard. The system developed using BSB wizard is called the
Base System and will comprise of at least MB, AXI Interconnect, BRAM block (for Boot RAM), Clock generator module,
Reset module and the Debug Module. These modules should be present for the system to function adequately (though it
is not necessary, but it is preferred to have them).

Common modifications for all Sub - System Designs

By default XPS generates a differential clock and connects it to the clock generator block. As a single ended clock is
used generally, following modifications are to be made o all sub-system designs –

1. After generating base system using BSB wizard  Go to System Assembly View in XPS main window Ports
 External Ports  Right Click on External Port named CLK_N  Delete External Port

2. Again go to System Assembly View in XPS main window Ports  External Ports  Right Click on External
Port named CLK_P  Delete External Port

3. System Assembly View Ports Go to clk_generator_0 module For the port name CLKIN the connected
port column is blank  Right Click on CLKIN  Select Make External (It generates an external port named
clock_generator_0_CLKIN_pin, which can be seen in External Ports)

4. System Assembly View Ports  External Ports Click on clock_generator_0_CLKIN_pin port, change
name to CLK

5. For the port CLK  Assign frequency(in HZ) 100000000 depending on the Input Clock

6. System Assembly View Ports  External Ports Click on RESET port, change name to RESETn (as the
Reset is Active Low Reset)

For port mapping of Clock signal on ZEUS Board refer to Appendix A.

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7.2 Adding various Modules to the System Design

This section explains in detail how to instantiate a particular IP block for sub-system design and the various configuration
settings required to be done for these blocks so that the sub-system functions properly.

7.2.1 UART

How to instantiate the IP block?

After starting the System design creation using the BSB wizard, selecting the Interconnect and selecting the appropriate
Board we reach on the “BSB Wizard - IO and Peripheral Configuration Window” (shown in Figure 7). Follow the
following steps to add an UART block –

1. Click on “Add Device”(opens a window as shown in Figure 16)  Expand the drop down menu of IO interface
Type  Select UART  Expand the drop down menu of Device  Select RS232  Click OK

Figure 16: BSB Wizard - IO and Peripheral Configuration Window (Add IO Devices for Generic Board)

2. In the right section “Included peripherals for microblaze_0” the added UART module is shown  Click on
RS232 Core to change the core settings –

RS232 Type = axi_uartlite

Baud Rate = 115200
Data Bit Width = 8
Use Interrupt = Check the Box if required (User dependent)
Pairty = No

3. Click Finish to generate the System design with UART

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Modifying the IP External Port Names and Signals

After generation of the system, following port modifications are to be done for UART apart from the clock generator
modifications –

1. After generating base system using BSB wizard  Go to System Assembly View in XPS main window Ports
 External Ports  Click on RS232_Uart_1_sin port, change name to UART_RX

2. System Assembly View Ports  External Ports  Click on RS232_Uart_1_sout port, change name to
UART_TX

For port mapping of UART signals on ZEUS Board refer to Appendix A.

For UART IP core Xilinx documentation refer to Reference 4.

7.2.2 GPIO – LED

How to instantiate the IP block?

1. Click on “Add Device”(opens a window as shown in Figure 16)  Expand the drop down menu of IO interface
Type  Select GPIO  Expand the drop down menu of Device  Select LEDS  Click OK

2. In the right section “Included peripherals for microblaze_0” the added LED module is shown  Click on LEDS
Core to change the core settings –

Core = axi_gpio
Data Width = 8
Use Interrupt = Check the Box if required (User dependent)

3. Click Finish to generate the System design with LEDs.

Modifying the IP External Port Names and Signals

After generation of the system, following port modifications are to be done for LED apart from the clock generator
modifications –

1. After generating base system using BSB wizard  Go to System Assembly View in XPS main window Ports
 External Ports  Click on LEDS_TRI_O port, change name to LED

2. System Assembly View Ports  External Ports  For the port name LED change the Range (in Range
Column) from [0:7] to [7:0]

For port mapping of LED signals on ZEUS Board refer to Appendix A.

For GPIO IP core Xilinx documentation refer to Reference 5.

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7.2.3 GPIO – Switch

How to instantiate the IP block?

1. Click on “Add Device”(opens a window as shown in Figure 16)  Expand the drop down menu of IO interface
Type  Select GPIO  Expand the drop down menu of Device  Select DIP_Switches  Click OK

2. In the right section “Included peripherals for microblaze_0” the added DIP_Switches module is shown  Click
on DIP_Switches Core to change the core settings –

Core = axi_gpio
Data Width = 8
Use Interrupt = Check the Box if required (User dependent)

3. Click Finish to generate the System design with SWITCH.

Modifying the IP External Port Names and Signals

After generation of the system, following port modifications are to be done for Switch apart from the clock generator
modifications –

1. After generating base system using BSB wizard  Go to System Assembly View in XPS main window Ports
 External Ports  Click on DIP_Switches_TRI_I port, change name to SWITCH

2. System Assembly View Ports  External Ports  For the port name SWITCH change the Range (in
Range Column) from [0:7] to [7:0]

For port mapping of Switch signals on ZEUS Board refer to Appendix A

For GPIO IP core Xilinx documentation refer to Reference 5

7.2.4 GPIO - Push Button

How to instantiate the IP block?

After starting the System design creation using the BSB wizard, selecting the Interconnect and selecting the appropriate
Board we reach on the “BSB Wizard - IO and Peripheral Configuration Window” (shown in Fig. 7). Follow the
following steps to add a PUSH_BUTTON block –

1. Click on “Add Device”(opens a window as shown in Fig. 16)  Expand the drop down menu of IO interface
Type  Select GPIO  Expand the drop down menu of Device  Select Push_Buttons  Click OK

2. In the right section “Included peripherals for microblaze_0” the added Push_Buttons module is shown  Click
on Push_Buttons Core to change the core settings –

Core = axi_gpio
Data Width = 3 (as it is mapped to USB3.0 Board)
Use Interrupt = Check the Box if required (User dependent)

3. Click Finish to generate the System design with Push Button.

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Modifying the IP External Port Names and Signals

After generation of the system, following port modifications are to be done for Push Button apart from the clock generator
modifications –

1. After generating base system using BSB wizard  Go to System Assembly View in XPS main window Ports
 External Ports  Click on Push_Buttons_TRI_I port, change name to PUSHB

2. System Assembly View Ports  External Ports  For the port name PUSHB change the Range (in
Range Column) from [0:7] to [2:0]

For port mapping of Push Button signals on ZEUS Board refer to Appendix A

For GPIO IP core Xilinx documentation refer to Reference 5

7.2.5 GPIO - Generic Bus

How to instantiate the IP block?

After starting the System design creation using the BSB wizard, selecting the Interconnect and selecting the appropriate
Board we reach on the “BSB Wizard - IO and Peripheral Configuration Window” (shown in Fig. 7). Follow the
following steps to add a Generic GPIO Bus block –

1. Click on “Add Device”(opens a window as shown in Fig. 16)  Expand the drop down menu of IO interface
Type  Select GPIO  Expand the drop down menu of Device  Select Generic_GPIO  Click OK

2. In the right section “Included peripherals for microblaze_0” the added Generic_GPIO module is shown 
Click on Generic_GPIO Core to change the core settings –

Core = axi_gpio
Data Pin are all inputs = false
Data Width = 8
Use Interrupt = Check the Box if required (User dependent)

3. Click Finish to generate the System design with Generic GPIO bus.

Modifying the IP External Port Names and Signals

After generation of the system, following port modifications are to be done for Generic GPIO Bus apart from the clock
generator modifications –

1. After generating base system using BSB wizard  Go to System Assembly View in XPS main window Ports
 External Ports  Click on Generic_GPIO_TRI_IO port, change name to GPIO

2. System Assembly View Ports  External Ports  For the port name Generic_GPIO_TRI_IO change the
Range (in Range Column) from [0:3] to [7:0]

For port mapping of Generic GPIO Bus signals on ZEUS Board refer to Appendix A.

For GPIO IP core Xilinx documentation refer to Reference 5.

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7.2.6 IIC/I2C

How to instantiate the IP block?

After starting the System design creation using the BSB wizard, selecting the Interconnect and selecting the appropriate
Board we reach on the “BSB Wizard - IO and Peripheral Configuration Window” (shown in Fig. 7). Follow the
following steps to add an IIC block –

1. Click on “Add Device”(opens a window as shown in Fig. 16)  Expand the drop down menu of IO interface
Type  Select IIC  Expand the drop down menu of Device  Select Generic_IIC_Bus  Click OK

2. In the right section “Included peripherals for microblaze_0” the added Generic_IIC_Bus module is shown 
Click on Generic_GPIO Core to change the core settings –

Core = axi_iic
Use Interrupt = Check the Box if required (User dependent)

3. Click Finish to generate the System design with IIC.

If multiple IIC instances are to be added to the system design, follow the following steps –
1. Go to IP Catalog  Communication Low-Speed  Double Click on AXI IIC Interface to add another I2C
Block.
2. Follow the steps mentioned in Section 5.2.2 to add the IP Block to the System Design

Modifying the IP External Port Names and Signals

After generation of the system, following port modifications are to be done for IIC Bus apart from the clock generator
modifications –

1. After generating base system using BSB wizard  Go to System Assembly View Ports Go to
Generic_IIC_Bus module  Go to (IO_IF) iic_0 sub-module For the port named Sda the connected port
column is blank  Right Click on Sda  Select Make External (It generates an external port named
Generic_IIC_Bus_Sda, which can be seen in External Ports)

2. System Assembly View Ports  External Ports Click on Generic_IIC_Bus_Sda port, change name to
IIC_DATA_M

3. Go to System Assembly View Ports Go to Generic_IIC_Bus module  Go to (IO_IF) iic_0 sub-module
For the ports named Scl the connected port column is blank  Right Click on Scl  Select Make External (It
generates an external port named Generic_IIC_Bus_Scl, which can be seen in External Ports)

4. System Assembly View Ports  External Ports Click on Generic_IIC_Bus_Scl port, change name to
IIC_DATA_S

If the IIC block is added separately after completing the BSB wizard or another instance of IIC is added then these steps
also need to be followed apart from the previous four -
1. After addition of the IIC Block  Go to System Assembly View Bus Interfaces  axi_iic_0  S_AXI 
From the drop down menu besides S_AXI select axi4lite_0 (makes the connection of the block with the AXI
Interconnect)
2. Go to System Assembly View Ports Go to axi_iic_0 module  Go to (BUS_IF) S_AXI sub-module For
the port named S_AXI_ACLK make the connection to the CLKOUT0 of the clock_generator_0 block as shown
in Fig. 17

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Figure 17: Connecting S_AXI_ACLK with CLKOUT0 of clock_generator_0

3. Go to System Assembly View  Addresses  If it shows any module in Unmapped addresses, Click on the
Button highlighted in Figure 18

Figure 18: Icon to Refresh the Address mapping of MicroBlaze to remove any unmapped addresses

4. Make the SDA & SCL connections as mentioned above.

For port mapping of IIC signals on ZEUS Board refer to Appendix A

For IIC IP core Xilinx documentation refer to Reference 6

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7.2.7 Timer

How to instantiate the IP block?

After starting the System design creation using the BSB wizard, selecting the Interconnect and selecting the appropriate
Board we reach on the “BSB Wizard - IO and Peripheral Configuration Window” (shown in Fig. 7). Follow the
following steps to add a Timer block –

1. Go to Available Peripherals Section (can be found below Add Device, shown in Fig. 7)  Internal
Peripherals  Select axi_timer Click Add

2. In the right section “Included peripherals for microblaze_0” the added axi_timer_0 module is shown  Click
on axi_timer_0 to change the core settings –

Core = axi_timer
Use Interrupt = Check the Box if required (User dependent)

3. Click Finish to generate the System design with IIC.

Modifying the IP External Port Names and Signals

After generation of the system, no modification in any of the Timer Ports is to be done.

For port mapping of Timer signals on ZEUS Board refer to Appendix A

For Timer IP core Xilinx documentation refer to Reference 7

7.2.8 Interrupt Controller (INTRC)

How to instantiate the IP block?

After starting the System design creation using the BSB wizard, selecting the Interconnect and selecting the appropriate
Board we reach on the “BSB Wizard - IO and Peripheral Configuration Window” (shown in Fig. 7). If interrupt of any
block is enabled here then the Interrupt Controller would be added to the system design automatically.

If Interrupt Controller is to be added to the system design after creating a system design, then follow the following steps –

1. Go to IP Catalog  Clock, Reset and Interrupt  Double Click on AXI Interrupt Controller to add the
Interrupt Controller

2. Follow the steps mentioned in Section 5.2.2 to add the IP Block to the System Design

NOTE: Refer to Xilinx INTRC User Guide (Reference 8) to see how to make connections after instantiating the Interrupt
Controller after generation of Base System.

Modifying the IP External Port Names and Signals

After generation of the system, no modification in any of the INTRC Ports is to be done.

For port mapping of INTRC signals on ZEUS Board refer to Appendix A

For INTRC IP core Xilinx documentation refer to Reference 8

Cadence Design Systems Page 39

7.2.9 BRAM and BRAM Controller

How to instantiate the IP block?

After starting the System design creation using the BSB wizard, selecting the Interconnect and selecting the appropriate
Board we reach on the “BSB Wizard - IO and Peripheral Configuration Window” (shown in Fig. 7). Follow the
following steps to add a BRAM Controller block –

1. Go to Available Peripherals Section (can be found below Add Device, shown in Fig. 7)  Internal
Peripherals  Select axi_bram_ctrl Click Add

2. In the right section “Included peripherals for microblaze_0” the added axi_bram_ctrl _0 (Cached) module is
shown  Click on axi_timer_0 to change the core settings –

Core = axi_bram_ctrl
Memory Size = 64 kB (User dependent)

3. Click Finish to generate the System design with BRAM.

Modifying the IP External Port Names and Signals

After generation of the system, no modification in any of the BRAM Controller Ports is to be done.

For port mapping of BRAM Controller signals on ZEUS Board refer to Appendix A

For BRAM IP core Xilinx documentation refer to Reference 9

For BRAM Controller IP core Xilinx documentation refer to Reference 10

7.2.10 DMA Controller

How to instantiate the IP block?

After starting the System design creation using the BSB wizard, selecting the Interconnect and selecting the appropriate
Board we reach on the “BSB Wizard - IO and Peripheral Configuration Window” (shown in Fig. 7). Add the IP cores
required for the Base system and Click Finish. After reaching the XPS GUI follow the steps to add a DMA Controller
block –

1. Go to IP Catalog  DMA and Timer  Double Click on AXI Central DMA to add the DMA Controller

2. Follow the steps mentioned in Section 5.2.2 to add the IP Block to the System Design.

Modifying the IP External Port Names and Signals

After generation of the system, following port modifications are to be done for DMA Controller apart from the clock
generator modifications –

1. After generating base system using BSB wizard and adding the DMA block Go to System Assembly View
Bus Interfaces Go to axi_cdma_0 module  Connect M_AXI to axi4lite_0

For port mapping of DMA Controller signals on ZEUS Board refer to Appendix A

For DMA Controller IP core Xilinx documentation refer to Reference 11

Cadence Design Systems Page 40

7.2.11 DDR2 Controller

How to instantiate the IP block?

After starting the System design creation using the BSB wizard, selecting the Interconnect and selecting the appropriate
Board we reach on the “BSB Wizard - IO and Peripheral Configuration Window” (shown in Fig. 7). Follow the
following steps to add an DDR2 Controller block-

1. Click on “Add Device”(opens a window as shown in Fig. 16)  Expand the drop down menu of IO interface
Type  Select S6_DDRX_MEMORY  Expand the drop down menu of Device  Select MCB_DDR2  Click
OK

2. In the right section “Included peripherals for microblaze_0” the added MCB_DDRX (Cached) module is shown
 Click on Generic_GPIO Core to change the core settings –
Core = axi_s6_ddrx

3. Click Finish to generate the System design with DDR2 Memory.

4.
Modifying the IP External Port Names and Signals

After generation of the system, following port modifications are to be done for Switch apart from the clock generator
modifications –

1. After generating base system using BSB wizard  Go to System Assembly View in XPS main window Ports
 External Ports  Rename all DDR signals according to the ucf (ucf is given in Appendix A)

2. Double click on MCB_DDR2 to invoke by MIG  In MIG change the location of DDR2-SRAM to MCB5 and
change the part no to MT47H32M16XX - 25E - IT and change frequency according to the need.

3. Then without changing any other setting - Click Next till you reach the end of MIG  Click Finish.

For port mapping of DDR2 signals on ZEUS Board refer to Appendix A

For MIG and DDRX IP core Xilinx documentation refer to Reference 12 and Reference 13

Cadence Design Systems Page 41

How to instantiate the IP block?

After starting the System design creation using the BSB wizard, selecting the Interconnect and selecting the appropriate
Board we reach on the “BSB Wizard - IO and Peripheral Configuration Window” (shown in Fig. 7). Add the IP cores
required for the Base system and Click Finish. After reaching the XPS GUI follow the steps to add a DMA Controller
block –

1. Go to IP Catalog  PCI  Double Click on AXI Memory mapped to PCI Express v1.09a to add the AXI to
PCIe Bridge and Controller.

2. Follow the steps mentioned in Section 5.2.2 to add the IP Block to the System Design.

Modifying the IP External Port Names and Signals

After generation of the system, following port modifications are to be done for PCIe apart from the clock generator
modifications, please refer to the Xilinx Reference for details.

For port mapping of PCIe signals on HTG Board refer to Appendix B

For PCIe IP core Xilinx documentation refer to Reference 14

Cadence Design Systems Page 42

8 Compiling Sub-System Design generated using XPS

The Sub - system hardware design created using Xilinx XPS tool is compiled to generate the simulation environment, in
such a way that the changes made in the C code are directly reflected in the simulation environment without the need of
modifying the test bench and compiling the files again. The steps to be followed are –

=======================================================================
Create New XPS project(<XPS_prj_path>)

--create system and complete all Flows

Copy <prj_reference> folder to your project work directory and rename the folder to your project name

copy <XPS_prj_path>/simulation/behavirol/.v and .vhd to prj_name\rtl\xilinx\system

copy <XPS_prj_path>/simulation/behavirol/elaborate to prj_name\rtl\xilinx\system

move prj_name\rtl\xilinx\system\system_tb.v to prj_name\verif\testbench

Edit testbench file as per requirements

copy <XPS_prj_path>\pcores to prj_name\rtl\xilinx\

copy all model files to prj_name\verif\models folder

copy other DUT related files to prj_name\rtl\

create fpga_top module file and paste to prj_name\rtl\fpga_top folder

copy <XPS_prj_path>/simulation/behavirol/system.prj to prj_name\verif\sim_isim and rename to "file_list.prj"

Cadence Design Systems Page 43

give proper path for below files (path: ../../rtl/xilinx/system/")

Original:
vhdl work "system_proc_sys_reset_0_wrapper.vhd"
vhdl work "system_microblaze_0_ilmb_wrapper.vhd"
vhdl work "system_microblaze_0_i_bram_ctrl_wrapper.vhd"
vhdl work "system_microblaze_0_dlmb_wrapper.vhd"
vhdl work "system_microblaze_0_d_bram_ctrl_wrapper.vhd"
verilog work "system_microblaze_0_bram_block_wrapper.v"
vhdl work "system_microblaze_0_wrapper.vhd"
vhdl work "system_debug_module_wrapper.vhd"
vhdl work "system_clock_generator_0_wrapper.vhd"
verilog work "system_axi4lite_0_wrapper.v"
vhdl work "system_rs232_wrapper.vhd"
vhdl work "system_leds_wrapper.vhd"
verilog work "system.v"
verilog work "system_tb.v"

Modified:
vhdl work "../../rtl/xilinx/system/system_proc_sys_reset_0_wrapper.vhd"
vhdl work "../../rtl/xilinx/system/system_microblaze_0_ilmb_wrapper.vhd"
vhdl work "../../rtl/xilinx/system/system_microblaze_0_i_bram_ctrl_wrapper.vhd"
vhdl work "../../rtl/xilinx/system/system_microblaze_0_dlmb_wrapper.vhd"
vhdl work "../../rtl/xilinx/system/system_microblaze_0_d_bram_ctrl_wrapper.vhd"
verilog work "../../rtl/xilinx/system/system_microblaze_0_bram_block_wrapper.v"
vhdl work "../../rtl/xilinx/system/system_microblaze_0_wrapper.vhd"
vhdl work "../../rtl/xilinx/system/system_debug_module_wrapper.vhd"
vhdl work "../../rtl/xilinx/system/system_clock_generator_0_wrapper.vhd"
verilog work "../../rtl/xilinx/system/system_axi4lite_0_wrapper.v"
vhdl work "../../rtl/xilinx/system/system_rs232_wrapper.vhd"
vhdl work "../../rtl/xilinx/system/system_leds_wrapper.vhd"
vhdl work "../../rtl/xilinx/system/system_dip_switches_wrapper.vhd"
vhdl work "../../rtl/xilinx/system/system_axi_apb_bridge_0_wrapper.vhd"
verilog work "../../rtl/xilinx/system/system.v"
verilog work "../testbench/system_tb.v"

Cadence Design Systems Page 44

© 2013 Cadence Design Systems Inc. All rights reserved. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems Inc. All others
are properties of their respective holders. Cadence Design Systems products are subject to continuous development and the Company reserves the right to
change, delete, or modify specifications and features without notice
AMBA based System for High Speed IP Validation
Hardware & Software Application Design Guide
Add DUT files in end of "file_list.prj"
eg:
verilog work "../../rtl/digrf/ccdigrfv4_apb_rx_asynch_fifo.v" -i "../../rtl/digrf/include"
verilog work "../../rtl/digrf/ccdigrfv4_apbslave_master.v" -i "../../rtl/digrf/include"
--------------------------------------------------------------------------------------------
go to prj_name\verif\sim_isim and modify the "run_compile.cmd" with below details
edit "work.<testbench_top_module>" to "work.<your_testbench_top_module_name>"
eg: work.system_tb
Open Xilinx CMD Prompt
Start -> All Programs -> Xilinx Design Tools -> ISE Design Suite 14.2 -> Accessories -> Xilinx Design Suite Command
Prompt
Go to simulation directory
cd <ProjectDirectory>/verif/sim_isim
To compile the Design
run run_compile.cmd in Prompt
Output of above command:
Time Resolution for simulation is xxxfs.
Waiting for xxx sub-compilation(s) to finish...
Compiled xxx VHDL Units
Compiled xx Verilog Units
Built simulation executable isim_system.exe
Fuse Memory Usage: xxxxxxx KB
Fuse CPU Usage: xxxxx ms
Note: xxx is any numbers
Check warnings and errors in fuse.log file
To generate boot image file go to software folder and refer readme.txt (follow all XPS and EDK steps also) {Also
given in the Chapter 9}
To simulate the Design
run run_simulation.cmd in Prompt
Simulation Commands:
Edit sim_commands.tcl file to modify/add sim commands
-- add signal to waveform window
-- run command
Chapter 9: Generating the elf File
This chapter will guide you about the procedure to generate the elf file. This procedure is to be followed once the system
design has been compiled using the steps mentioned in Chapter 8.
=======================================================================
Folder Descriptions -

src: Contains the Source codes (user.c is the top file, main source code)
inc: contains the microblaze header files
obj: contains system generated object files
system: contains system information files (xml)
image: contains generated image files for boot memory

----------------------------------------------------------------------------------------------------------------------
sofware creation for new system
----------------------------------------------------------------------------------------------------------------------

Create hello World program for new system using XPS & SDK

Replace following file and directoy from software folder with XPS & SDK project

rm -rf software/image/*
rm -rf software/inc/microblaze_0
rm -rf software/src/*
rm -rf software/system/*

cp -rf <XPS>/system/simulation/behavioral/system_sim.bmm software/image/system_sim.bmm

Cadence Design Systems Page 45

cp -rf <SDK>/<hello_world>/src/. software/src/.

cp -rf <software_refernece>/src/user.c software/src/.

cp -rf <SDK>/<hw_platform>/*.bit software/system/.

cp -rf <SDK>/<hw_platform>/*.xml software/system/.
cp -rf <SDK>/<hw_platform>/*.bmm software/system/.
cp -rf <XPS>/system/*.xmp software/system/.
cp -rf <XPS>/system/*.mhs software/system/.

----------------------------------------------------------------------------------------------------------------------
Image file generaion for ISim & FPGA
----------------------------------------------------------------------------------------------------------------------

Open Xilinx CMD prompt by Start-> Programs -> Xilinx Design Tools -> ISE Design Suite -> Accessories > ISE
Design Suite command prompt

cd to "software" directory ($cd <project_directory>/software)

Edit testcase "src/user.c" as per application requirement($notepad src/user.c)

run below command to generate .elf & .mem file

$build.cmd | tee build.log

Check the build.log file for any errors & warning

Cadence Design Systems Page 46

9 Appendices

9.1 Appendix A - Pin Map for Zeus Board

The pin map for various connections to be made while mapping the sub-system design on Zeus Board is given in this
section. Text in Bold indicates the comments.

# Clock Constraints

NET "CLK" LOC = W4 | IOSTANDARD = LVCMOS33;

NET "CLK" TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;

# Reset Pin

NET "RESET" LOC = N9 | IOSTANDARD = LVCMOS33 | PULLUP | TIG;

# LED's on Zeus Board

#NET "LED[0]" LOC = B25 | IOSTANDARD = LVCMOS33 | TIG;

# UART Tx & RX

NET "UART_TX" LOC = V1 | IOSTANDARD = LVCMOS33 | TIG;

NET "UART_RX" LOC = V2 | IOSTANDARD = LVCMOS33 | TIG;

# USB 3.0 Board GPIO Interface - LED's

NET "LED[0]" LOC = AE3 | IOSTANDARD = LVCMOS33 | TIG;

# USB 3.0 Board GPIO Interface - Switches

NET "SWITCH[0]" LOC = AA7 | IOSTANDARD = LVCMOS33 | TIG;

Cadence Design Systems Page 47

NET "PUSHB[0]" LOC = AH5 | IOSTANDARD = LVCMOS33 | TIG;

# USB 3.0 Board GPIO Interface - GPIO (#GPIO[*] represents actual GPIO Port)

NET "GPIO[1]" LOC = T7 | IOSTANDARD = LVCMOS33 | TIG;

# IIC_Master IO - Daughter Connector Board

NET "IIC_CLK_M" LOC = E6 | IOSTANDARD = LVCMOS18 | PULLUP | TIG;

NET "IIC_DATA_M" LOC = D7 | IOSTANDARD = LVCMOS18 | PULLUP | TIG;

# IIC_Slave IO - Daughter Connector Board

NET "IIC_CLK_S" LOC = G7 | IOSTANDARD = LVCMOS18 | PULLUP | TIG;

NET "IIC_DATA_S" LOC = E8 | IOSTANDARD = LVCMOS18 | PULLUP | TIG;

########## DDR2 - SDRAM Interface - Position is MCB5 #########

# Address Lines

NET "MCB_DDR2_dram_addr[0]" LOC = D28 | IOSTANDARD = SSTL18_II;

NET "MCB_DDR2_dram_addr[1]" LOC = D30 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_addr[2]" LOC = C30 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_addr[3]" LOC = E29 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_addr[4]" LOC = F27 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_addr[5]" LOC = H26 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_addr[6]" LOC = H27 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_addr[7]" LOC = C29 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_addr[8]" LOC = B27 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_addr[9]" LOC = A27 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_addr[10]" LOC = F26 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_addr[11]" LOC = A26 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_addr[12]" LOC = B30 | IOSTANDARD = SSTL18_II;

# Bank Address

NET "MCB_DDR2_dram_ba[0]" LOC = D27 | IOSTANDARD = SSTL18_II;

NET "MCB_DDR2_dram_ba[1]" LOC = C27 | IOSTANDARD = SSTL18_II;

Cadence Design Systems Page 48

NET "MCB_DDR2_dram_dq[0]" LOC = H28 | IOSTANDARD = SSTL18_II;

NET "MCB_DDR2_dram_dq[1]" LOC = H30 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_dq[2]" LOC = G29 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_dq[3]" LOC = G30 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_dq[4]" LOC = G27 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_dq[5]" LOC = G28 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_dq[6]" LOC = F28 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_dq[7]" LOC = F30 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_dq[8]" LOC = L27 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_dq[9]" LOC = L28 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_dq[10]" LOC = L29 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_dq[11]" LOC = L30 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_dq[12]" LOC = M26 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_dq[13]" LOC = M27 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_dq[14]" LOC = M28 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_dq[15]" LOC = M30 | IOSTANDARD = SSTL18_II;

# Other DDR Lines

NET "MCB_DDR2_dram_ras_n" LOC = K26 | IOSTANDARD = SSTL18_II;

NET "MCB_DDR2_dram_cas_n" LOC = K27 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_we_n" LOC = E26 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_cke" LOC = B29 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_clk" LOC = E27 | IOSTANDARD = DIFF_SSTL18_II;
NET "MCB_DDR2_dram_clk_n" LOC = E28 | IOSTANDARD = DIFF_SSTL18_II;

NET "MCB_DDR2_dram_dqs" LOC = J29 | IOSTANDARD = DIFF_SSTL18_II;

NET "MCB_DDR2_dram_dqs_n" LOC = J30 | IOSTANDARD = DIFF_SSTL18_II;
NET "MCB_DDR2_dram_udqs" LOC = K28 | IOSTANDARD = DIFF_SSTL18_II;
NET "MCB_DDR2_dram_udqs_n" LOC = K30 | IOSTANDARD = DIFF_SSTL18_II;
NET "MCB_DDR2_dram_udm" LOC = J27 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_ldm" LOC = J28 | IOSTANDARD = SSTL18_II;
NET "MCB_DDR2_dram_odt" LOC = E30 | IOSTANDARD = SSTL18_II;

NET "MCB_DDR2_rzq" LOC = G25 | IOSTANDARD = SSTL18_II | PULLDOWN;

NET "MCB_DDR2_zio" LOC = N24 | IOSTANDARD = SSTL18_II | PULLDOWN;

==============================================================================

Cadence Design Systems Page 49

# Clock Constraints

NET "CLK" LOC = E14 | IOSTANDARD = LVCMOS15;

NET "CLK" TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;

# Reset Pin

NET "RESETn" LOC = V33 | IOSTANDARD = LVCMOS15 | PULLUP | TIG;

NET "PCIe_PERSTn" LOC = AY19 | PULLUP ;

# UART Tx & RX

NET "UART_TX" LOC = AV40 | IOSTANDARD = LVCMOS15 | TIG;

NET "UART_RX" LOC = AW40 | IOSTANDARD = LVCMOS15 | TIG;

# LED's

NET "LED[0]" LOC = M14 | IOSTANDARD = LVCMOS15 | TIG;

# Switches

NET "SWITCH[0]" LOC = AA34 | IOSTANDARD = LVCMOS15 | TIG;

# Push Buttons

NET "PUSHB[0]" LOC = U34 | IOSTANDARD = LVCMOS15 | TIG;

Cadence Design Systems Page 50

NET "PCIe_Diff_Clk_P_EP" LOC = AF8;

NET "PCIe_Diff_Clk_N_EP" LOC = AF7;
NET "PCIe_TX_Dp_EP" LOC = AK3; #RC RX DP
NET "PCIe_TX_Dn_EP" LOC = AK4; #RC RX DN
NET "PCIe_RX_Dp_EP" LOC = AG5; #RC TX DP
NET "PCIe_RX_Dn_EP" LOC = AG6; #RC TX DN
#NET "LED[7]" LOC = BA19; #WAKE Signal for PCIe

########## DDR2 - SDRAM Interface - Position is MCB5 #########

## Address Lines
#
#NET "axi_s6_ddrx_0_mcbx_dram_addr[0]" LOC = D28 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_addr[1]" LOC = D30 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_addr[2]" LOC = C30 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_addr[3]" LOC = E29 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_addr[4]" LOC = F27 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_addr[5]" LOC = H26 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_addr[6]" LOC = H27 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_addr[7]" LOC = C29 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_addr[8]" LOC = B27 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_addr[9]" LOC = A27 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_addr[10]" LOC = F26 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_addr[11]" LOC = A26 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_addr[12]" LOC = B30 | IOSTANDARD = SSTL18_II;
#
## Bank Address
#
#NET "axi_s6_ddrx_0_mcbx_dram_ba[0]" LOC = D27 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_ba[1]" LOC = C27 | IOSTANDARD = SSTL18_II;
#
## Other DDR Lines
#
#NET "axi_s6_ddrx_0_mcbx_dram_ras_n" LOC = K26 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_cas_n" LOC = K27 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_we_n" LOC = E26 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_cke" LOC = B29 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_clk" LOC = E27 | IOSTANDARD = DIFF_SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_clk_n" LOC = E28 | IOSTANDARD = DIFF_SSTL18_II;
#
## Data Lines
#
#NET "axi_s6_ddrx_0_mcbx_dram_dq[0]" LOC = H28 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[1]" LOC = H30 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[2]" LOC = G29 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[3]" LOC = G30 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[4]" LOC = G27 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[5]" LOC = G28 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[6]" LOC = F28 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[7]" LOC = F30 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[8]" LOC = L27 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[9]" LOC = L28 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[10]" LOC = L29 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[11]" LOC = L30 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[12]" LOC = M26 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[13]" LOC = M27 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[14]" LOC = M28 | IOSTANDARD = SSTL18_II;
#NET "axi_s6_ddrx_0_mcbx_dram_dq[15]" LOC = M30 | IOSTANDARD = SSTL18_II;

Cadence Design Systems Page 51

==============================================================================

Cadence Design Systems Page 52

10 References
1. EDK Concepts, Tools and Techniques, Xilinx - UG683 (v13.4), 2012
2. Embedded System Tools Reference Manual, EDK, Xilinx - UG111 (v14.2), 2012
3. Platform Specification Format Reference Manual, EDK, Xilinx - UG642 (v12.3), 2010
4. LogiCore IP AXI UART Lite Datasheet – v1.02a, Xilinx – DS 741, 2012
5. LogiCore IP AXI GPIO Datasheet - v1.01b, Xilinx – DS 744, 2011
6. LogiCore IP AXI IIC Bus Interface Datasheet - v1.02a , Xilinx – DS 756, 2012
7. LogiCore IP AXI Timer Datasheet - v1.03a , Xilinx – DS 764, 2012
8. LogiCore IP AXI INTC Datasheet - v1.02a, Xilinx – DS 747, 2012
9. IP Processor Block RAM(BRAM) Block - v1.00a, Xilinx – DS 444, 2011
10. LogiCore IP AXI Block RAM Controller Datasheet - v1.03a, Xilinx – DS 777, 2011
11. LogiCORE IP AXI Central Direct Memory Access Datasheet - v3.03a, Xilinx - PG 034, 2012
12. Spartan-6 FPGA Memory Interface Solutions - v1.3.1, Xilinx - UG416, 2012
13. Spartan-6 FPGA Memory Controller - v2.3, Xilinx - UG388, 2010
14. LogiCore IP AXI Bridge for PCI Express Datasheet - v1.05a, Xilinx – PG 055, 2012

Cadence Design Systems Page 53

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