Design IP Brochure

Cadence IP Factory
Get on the Fast Track to SoC Design Innovation

Version 2.2
Cadence Design IP Overview Integration-Focused for Reduced Risk
Cadence IP Factory provides integration-focused IP and IP
®
Integration of IP has traditionally been a challenge for SoC
subsystems that are proven to reduce risk and accelerate the designers. By building our IP from the ground up, and by focusing
development of leading-edge SoCs. Our interface IP for key on integration, we help you significantly reduce both integration
memory, storage, and interconnect standards—in addition to our effort and risk. In addition, our ability to deliver fully integrated
core building-block IP—help you design and integrate the highest controller, PHY, and firmware solutions at both the interface and
quality SoCs with optimal performance and power. subsystem level further reduces your integration effort.

We Always Listen to You Unique Customization Infrastructure

We always listen to our customers and want to meet their needs. We can deliver IP configured to your specific SoC design
Prior to its realization, every SoC project is discussed with you and requirements, providing only those features and performance
examined in detail. levels needed for your particular application.

Using our customization infrastructure eliminates the need to

“...we respond quickly, and we listen compromise—you can specify the IP around your design rather
to the customer very closely. I spend than building your design around the IP. Furthermore, each of
our customized IP solutions is fully verified and delivered with
most of my time in front of customers. complete documentation plus an integration and verification
I want to be their trusted partner, to environment that is perfectly matched to the IP.
provide the best tools and solutions,
Proven Partner You Can Count On
and to help them work through some
Cadence Design IP is silicon proven and has been extensively
of the most challenging designs they validated. We offer comprehensive IP solutions that are in volume
have.” production and have been successfully implemented in more than
400 applications. With 13 years of experience delivering winning
Lip-Bu Tan interviewed by Richard Goering on August 27, 2013 IP solutions, Cadence is a proven partner you can count on.

“You have to rely on partners, you

Standards-Driven Design IP Targeted to Your
Needs have to rely on experts, whether
Supporting advanced capabilities Cadence Design IP offers
that’s hardware/software codesign,
superior performance and power-optimized solutions. Our analog-mixed signal, analysis tools,
extensive support for new standards, such as TSMC 28HPC,
signoff, DFT.”
ensures power- and cost-efficient design. No matter if the
application is a high-performance datacenter or a power-sipping Martin Lund being interviewed at MemCon 2013 by ChipEstimate.
mobile device, we provide you with IP which is targeted to your tv’s Sean O’Kane
specific needs.

“By delivering our interface, memory,

analog and systems/peripheral IP to
this 28HPC process, our customers
in the smartphone, tablet, and other
high-volume consumer markets can
take advantage of the 10 percent
smaller die size and 30 percent
power reduction benefits of this new
process.”
Martin Lund, September, 2014

2 Design IP Brochure Version 2.2 ip.cadence.com

Interface IP Solutions
We offer various complete, configurable, and production-proven interface protocols, such as Ethernet, MIPI®, PCI EXPRESS®, and USB. All
these solutions are designed with your SoC in mind, so that there is no need for you to design around our IP. Pre-verified solutions help
you save time and effort and allow you to focus on your own design priorities. Moreover, our highly configurable architecture provides
you with numerous customization options, including software and prototyping solutions.

PHY
TSMC
IP Protocols Performance Controller PCS
65nm 55nm 40nm 28nm 16nm

LP LPe LPe LP HPL HPM HPC LP FF

10M/100M 10M/100M* • •
10M/100M/1G 10M/100M/1G* • •
MAC
10/40G 10/40G • • • • •
40/100G 40/100G • •
Ethernet

10G 10/40G • • • •
10/40G 10/40G • • • •
PCS
40/100G 40/100G • • • •
XAUI/XAUI20 10/20G • • • •
Converter QSGMII R1.2 5G •
DSI DSI TX 1.5Gbps/lane • † † † † † †
CSI-2 RX 1.5Gbps/lane • † † † † † †
CSI
CSI-2 TX 1.5Gbps/lane • † † † † † †
DigRF SM
DigRF v4, v1.10 3Gbps/lane • ‡ ‡ ‡ ‡ ‡ ‡
MIPI

UniProSM UniPro 1.6 3 or 6Gbps/lane • ‡ ‡ ‡ ‡ ‡ ‡

Device v1.1 Audio/Data •
SLIMbus®
Manager v1.1 Audio/Data •
SoundWire Master Audio •
Gen 1 2.5Gbps • • • •
Gen 2 5Gbps • • • •
PCI EXPRESS

PCIe®
Gen 3 8Gbps • • • •
Gen 4 16Gbps • •
M-PCIe ECN, SL HS-G2/HS-G3 • • • •
M-PCIe™
M-PCIe ECN, ML HS-G2/HS-G3 • • • •
USB 2.0 480/12/1.5Mbps • • • • • • • • •
Host
USB 3.0 5Gbps and legacy • • • •
USB 1.1 12/1.5Mbps • • • • •
Device USB 2.0 480/12Mbps • • • • • • • • •
USB

USB 3.0 5Gbps and legacy • • • •

OTG USB 2.0 480/12/1.5Mbps • • • • • • • • •
Hub USB 2.0 480/12/1.5Mbps • • • • • • • • •
HSIC Interface USB 2.0 HSIC 480Mbps • • • •
SSIC Interface USB 3.0 SSIC 5/2.5/1.25Gbps • • • • • • •

Table 1: Interface IP Solutions * Soft PHY available

† – D-PHY
‡ – M-PHY

ip.cadence.com Design IP Brochure Version 2.2 3

Denali Memory IP Solutions
We offer the broadest and most configurable portfolio of the industry’s widely used memory and storage protocols.

Our Denali® Memory IP gives you the added value of multi-standard DDR support by providing controller IP that supports DDR4, DDR3,
DDR3L, LPDDR2, and LPDDR3 as a single IP solution. In order to address a wide range of applications, our DDR PHY IP includes two
families of DDR solutions, High-Speed (HS) and Low-Power (LP). Delivery options include soft, firm, hard, and full custom IP.

We also offer advanced memory IP solutions created by the best experts in the field to provide you with the controller, PHY, and
verification IP you need for your design.

PHY

Maximum TSMC GF ST
Protocols Controller
Speed Soft 40nm 28nm 16nm 28nm 28nm
LP G HPM HPC LP FF SLP HPP FDSOI
DDR DDR400 • •
DDR2 DDR800 • • •
DDR2/DDR DDR800 • •
DDR3*/DDR2 DDR800 • • •
DDR1333 • • • • • • • • • •
DDR3* DDR1600 • • • • • • • • •
DDR2133 • • • • • •
DDR1600 • • • • • • •
DDR2400 • • • • • •
DDR4
DDR2667 • • • •
DDR3200 • •
DDR1600 • • • • • • •
DDR2400 • • • • • •
DDR4/DDR3*
DDR2667 • • • •
DDR3200 • •
LPDDR DDR400 • •
LPDDR2 DDR800 • •
LPDDR2/LPDDR DDR800 • •
LPDDR2/DDR3* DDR800 • •
LPDDR2 DDR1066 • • • • • •
DDR1333 • • • • • •
LPDDR2/DDR3*
DDR1600 • • • •
DDR1333 • • • • • •
LPDDR3
DDR1600 • • • •
DDR1333 • • • • • •
LPDDR3/LPDDR2
DDR1600 • • • •
DDR1333 • • • • • •
LPDDR3/LPDDR2/DDR3*
DDR1600 • • • •
DDR2400 • •

LPDDR4/LPDDR3 DDR2667 • •
DDR3200 • •
DDR2400 • •
LPDDR4/LPDDR3/DDR4/
DDR2667 • •
DDR3
DDR3200 • •

Wide I/O 200MHz • •

Table 2: Denali Memory IP Solutions * DDR3 includes DDR3L support

4 Design IP Brochure Version 2.2 ip.cadence.com

Storage IP Solutions
Cadence storage IP solutions consist of two popular technologies, NAND Flash and SD/SDIO/eMMC. These memory technologies address
the needs of a broad range of market requirements.

The Cadence NAND Flash Controller IP supports all major NAND Flash manufacturers handling asynchronous devices and also meeting
standards such as ONFI 1, ONFI 2, ONFI 3, ONFI 3.2, Toggle 1, or Toggle 2. The Cadence NAND Flash PHY IP supports speeds up to
DDR800 for most process nodes, and is available as soft IP with a delay-locked loop (DLL) for your specific process and library.

The Cadence SD/SDIO/eMMC IP is compliant with the latest versions of Secure Digital and Embedded Multimedia Memory Card
standards, which makes our IP the perfect choice for both high-performance and low-power solutions.

PHY
IP Performance Controller
Soft
NAND Flash Async, ONFI 3.2/2/1, Toggle 1/2 Controller 533MTps •
NAND Flash

NAND Flash ONFI 4/3/2/1, Toggle 1/2 DLL PHY 800MTps •

NAND Flash ClearNAND Controller 200MTps • •
NAND Flash PHY for FPGA 200MTps •
SD 4.0 Host 312MBps • •
SD/SDIO/
eMMC

Combo SD/SDIO-3.0/eMMC 4.41 Host 104MBps • •

Combo SD 4.0/eMMC5.0 Host 400MBps • •
Combo SD 3.0/eMMC 5.0 PHY 400MBps •
Flash QSPI Controller 52MBps •

Table 3: Storage IP Solutions

High-Definition Display IP Solutions

The saying that a picture is worth a thousand words has never been as true as it is today. High-definition display has become an integral
part of any consumer device, with each product having specific display requirements, as well as needing to support industry-standard
interfaces and protocols.

Recognizing this fact, the newest addition to our IP portfolio includes solutions for HDMI®, DisplayPort™, MHL™, MyDP™, DP++™,
and eDP™. Our High-Definition Display IP supports the latest standard features such as 4Kx2K resolution, multiple streams, 3D video,
enhanced audio, content protection, and mobility.

PHY
TSMC SMIC
IP Protocols Performance
65nm 40nm 28nm 65nm
LP GP LP HPM HPC LL
HDMI1.4 3Gb per lane • • •
MHDP TX
Controller/Solution

MHL 2.1 3Gbps •

HDMI1.4 3Gb per lane • • •
MHDP RX MHL 2.1 3Gbps •
DP1.2 HBR , SST • • •
HDCP 1.4
HDCP 6Gbps per stream • • • • • •
HDCP 2.2
MHDP TX 6Gbps per lane •
MHDP TX HDP TX 3Gbps per lane • • • •
PHY

MHL TX 3Gbps per lane •

MHDP RX 3Gbps per lane •
MHDP RX
HDP RX 3Gbps per lane • • •

Table 4: High-Definition Display IP Solutions

ip.cadence.com Design IP Brochure Version 2.2 5

Analog IP Solutions
As an established industry leader in analog design tools, we offer some of the world’s fastest and lowest power analog IP solutions.

TSMC GF SMIC UMC

IP 65nm 40nm 28nm 16nm 65nm 55nm 40nm 28nm 28nm 40nm
LP G LP G HPL HPM HPC LP FF LP G LPe LPe LP SLP HK LP
General AFE • • •
Wi-Fi AFE • • • • • • • •
AFE

LTE AFE • •
TriBand (802.11n/ac/ad) AFE • •
LTE/Advanced LTE AFE • •
High-speed ADC (250MSps to 3.52GSps) • • • • •
Medium-speed ADC (20 to 250MSps) • • • • • • • • •
Low-speed ADC (<10MSps) • • • • • • •
High-speed DAC (250MHz to 3.52GHz) • • •
ADC and DAC

Medium-speed DAC (20 to 250MHz) • • • • •

Low-speed DAC (<10MHz) • • • • •
Audio • •
12b 80M ADC • •
12b 160M ADC • •
12b 320M ADC • •
7b 3.52G WiGiG ADC • •
Monitor

Temp Monitoring IP • • • • • • •

Voltage Monitoring IP • • •

LDO • • • • •
Power/
Timing

POR • • • • •
PLL/DLL • • • • • • • • • • • •
QSGMII/XAUI/Double XAUI • • •
PCIe3/2/1 PHY • • •
PCIe3/2/1 + SRIS + L1 sub-states PHY • • •
PCIe4 + SRIS + L1 sub-states PHY •
PCIe2/3, USB3 •
16G Mutli-
protocol
High-Speed SerDes

10GKR, PCIe3, XAUI, CEI-6G •

PCIe4, USB3.1, HMC-15G-SR •
6G Mutli- 10G Multi-

PCIe2/3, USB3 • •
protocol

10GKR, PCIe3, XAUI, CEI-6G • •

PCIe2, SATA 3.1,USB3.0, MIPI M-PHY •
protocol

DisplayPort TX 1.2a, SGMII •

12.5G Chip-to-Chip PHY •
10G-KR PHY • • •
10G EPON/GPON PMA • •
SATA 3.1 PHY •
USB 1.1 PHY (USB 2.0 Full Speed) • • • • • •
USB 2.0 PHY • • • • • • •
USB

USB 3.0 PHY • • •

USB 3.0 SSIC ( M-PHY) • • • • • •
USB 2.0 HSIC PHY • • •
M-PHY (HS-G2) • • • • •
MIPI

M-PHY (HS-G3) • • •
D-PHY • • • • • • • •

Table 5: Analog IP Solutions

6 Design IP Brochure Version 2.2 ip.cadence.com

Systems and Peripherals IP Solutions
Peripheral building blocks and efficient microprocessors have become an essential part of almost every SoC design. We offer peripheral,
8051 processor, and legacy processor IP. Our Systems and Peripherals IP solutions are architected to quickly and easily integrate into your
design, with configurability and compatibility being important features. All of our peripheral IP is compatible with the ARM® AMBA®
Specification, Revision 2.0.

Compatibility IP Description
AMBA Rev. 2.0 PWM Pulse Width Modulator
AMBA Rev. 2.0 WDT Watchdog Timer
Timer
AMBA Rev. 2.0 RTC Real-Time Clock
AMBA Rev. 2.0 TTC Triple Timer Counter
AMBA Rev. 2.0 AHBC Arbiter for ARM AMBA AHB interface
AMBA Rev. 2.0 AHB2APB Bridge ARM AMBA AHB to APB Bridge IP
Bus AMBA Rev. 2.0 APIC Advanced Peripheral Interrupt Controller
AMBA Rev. 2.0 SMC Static Memory Controller
Peripheral

AMBA Rev. 2.0 GPIO General Purpose I/O, provides up to 32 programmable ports
AMBA Rev 2.0, I2C bus specification Inter-Integrated Circuit Bus, functions as a master or slave in
I2C
version 2.0 (100kHz and 400kHz) a multi-master, two-wire serial I2C bus
AMBA Rev 2.0, I2C bus specification
Serial Interfaces I2C HS Inter-Integrated Circuit Bus, High-Speed version
version 2.0 (100kHz and 400kHz)
AMBA Rev. 2.0 SPI Serial Peripheral Interface Bus
AMBA Rev. 2.0 UART Universal Async Receiver Transmitter
AMBA Rev. 2.0, Philips Inter-IC Sound Bus Configurable single- or multi-channel Inter-IC Sound (I2S)
I2S
Specification (1986, revised in 1996) bus interface controller
Audio Connectivity
Unidirectional and self-clocking interface for connecting
AMBA Rev. 2.0 S/PDIF
digital audio equipment
Compatible with Intel® MCS® 51
R8051XC2 Intel 8051-compatible µC, fully configurable
8051 Processor

instruction set
8051 Compatible with Intel MCS 51 instruction
T8051 Tiny 8051-compatible µC, very small gate count
Microcontroller set
Compatible with Intel MCS 251 instruction Intel 80251-compatible µC, over 12 times faster than the
80251XC
set 80C51 from Intel
Compatible with M68000 instruction set C68000 MC68000-compatible microprocessor
Fully compatible with TMS320C25 TMS320C25 TI TMS320C25-compatible Digital Signal Processor
Legacy Processor

Series of high-performance, 16-bit microcontrollers

Compatible with Intel 80C86 or 80C186
Obsolete Parts C80186 compatible with Intel 80C186EC, Intel 80C186XL, Intel
instruction set
Replacement 80C186EA, with extended versions of peripherals
Compatible with i387SX instruction set C387L Intel i387SX-compatible 80-bit math co-processor
Compatible with Z80 instruction set Z80 Zilog Z80-compatible microprocessor
Improved Zilog Z80-compatible CPU
®
S80 Zilog Z80-compatible microprocessor, speed improved

Table 6: Systems and Peripherals IP Solutions

ip.cadence.com Design IP Brochure Version 2.2 7

Cadence Design Systems enables global electronic design innovation and plays an essential role in the
creation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to design
and verify today’s mobile, cloud, and connectivity applications. www.cadence.com
© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence, and Denali are registered trademarks of Cadence
Design Systems, Inc. AMBA and ARM are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights
reserved. MIPI® is a registered mark of MIPI Alliance, Inc. The terms HDMI and HDMI High-Definition Multimedia Interface, and the HDMI Logo
are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries. MHL, Mobile High-Definition Link and
the MHL Logo are trademarks or registered trademarks of the MHL, LLC. PCI-SIG®, PCIe®, and PCI EXPRESS® are registered trademarks of PCI-
SIG. JEDEC® and the JEDEC logo are registered trademarks of JEDEC Solid State Technology Association. Intel and MCS are trademarks of Intel
Corporation in the U.S. and/or other countries. ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All others
are the property of their respective holders.
Cadence IP Factory Version 2.2