Features on STM32M407
Sys-Tick timer
• This timer is dedicated to real-time operating systems, but can also be
used as a standard down counter.
• It features:
• A 24-bit down counter
• Auto-reload capability
• Programmable clock source
Intrrupts
Nested vectored interrupt controller (NVIC)
Extended interrupt/event controller (EXTI)
Buses: APB1 and APB2
BUSES: AHB1 and AHB2
Features comparison between TM4C123 and
STM32F407
MEMORY MAP
• Memory organization Program memory, data memory, registers and
I/O ports are organized within the same linear 4 GB address space.
• The bytes are coded in memory in little endian format. The lowest
numbered byte in a word is considered the word’s least significant
byte and the highest numbered byte, the word’s most significant.
• The addressable memory space is divided into 8 main blocks
Table 1. STM32F4xx register boundary addresses.
Configuration of General Purpose Input
Output
GPIOs configuration
• Each of the GPIO pins can be configured by software as output (push-
pull or open-drain), as input (with or without pull-up or pull-down) or
as peripheral alternate function.
• Most of the GPIO pins are shared with digital or analog alternate
functions.
Configuration of GPIOs
• Each general-purpose I/O port has four 32-bit configuration registers
(GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and
GPIOx_PUPDR)
• Two 32-bit data registers (GPIOx_IDR and GPIOx_ODR)
• Two 32-bit set/reset register (GPIOx_BSRR)
• One 32-bit locking register (GPIOx_LCKR)
• Two 32-bit alternate function selection register (GPIOx_AFRH and
GPIOx_AFRL)
• GPIO Configure the desired I/O as output or input in the
GPIOx_MODER register.
• Output states: push-pull or open drain + pull-up/down
It is possible to use the output driver in push-pull mode or open-
drain mode (only the N-MOS is activated when 0 is output).
• Peripheral alternate function For the ADC and DAC, configure the
desired I/O as analog in the GPIOx_MODER register. For other
peripherals:– Configure the desired I/O as an alternate function in
the GPIOx_MODER register
Input Pin
• Input states: floating(No-PULL), pull-up/down.
• All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not depending on the value in the GPIOx_PUPDR register
• Output data from output data register (GPIOx_ODR) or peripheral (alternate
function output) . When the pin is configured as output, the value written to the
output data register (GPIOx_ODR) is output on the I/O pin.
• The input data register (GPIOx_IDR) captures the data present on the I/O pin at
every AHB1 clock cycle.
• Bit set and reset register (GPIOx_BSRR) for bitwise write access to
• Locking mechanism (GPIOx_LCKR) provided to freeze the I/O configuration
• Alternate function input/output selection registers (at most 16 AFs per I/O) • Fast
toggle capable of changing every two clock cycles
GPIO_AFRH and GPIO_AFRL
• I/O pin multiplexer and mapping The microcontroller I/O pins are
connected to onboard peripherals/modules through a multiplexer
that allows only one peripheral’s alternate function (AF) connected to
an I/O pin at a time. In this way, there can be no conflict between
peripherals sharing the same I/O pin. Each I/O pin has a multiplexer
with sixteen alternate function inputs (AF0 to AF15) that can be
configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH
(for pin 8 to 15) registers: • After reset all I/Os are connected to the
system’s alternate function 0 (AF0) • The peripherals’ alternate
functions are mapped from AF1 to AF13
GPIOx_AFRL[31:0]
GPIOx_AFRH[31:0]
Pad configuration
• In STM32 microcontrollers (and other ARM-based MCUs), the GPIO
(General Purpose Input/Output) pad configuration refers to the
settings that define how a particular GPIO pin behaves electrically and
functionally. The key aspects of GPIO pad configuration are:
Input configuration
• When the I/O port is programmed as Input: • the output buffer is
disabled • the Schmitt trigger input is activated • the pull-up and pull-
down resistors are activated depending on the value in the
GPIOx_PUPDR register • The data present on the I/O pin are sampled
into the input data register every AHB1 clock cycle • A read access to
the input data register provides the I/O State
OUTPUT
RCC AHB1 peripheral clock register
• GPIO port registers can be accessed using two di erent buses.
Advanced Peripheral Bus (APB) Advanced High-Performance Bus
(AHB)
• (RCC_AHB1ENR) Address offset: 0x30
Reset value: 0x0010 0000
• The bit 0 to bit 5 of RCGC GPIO R register can be set to enable the
clock for PortA to PortF, respectively.
LED Configuration
• User LD3: orange LED -> I/O PD13
• User LD4: green LED -> I/O PD12
• User LD5: red LED -> I/O PD14
• User LD6: blue LED -> I/O PD15
Base addresses:
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
