Embedded Systems with ARM Cortex-M Microcontrollers

in Assembly Language and C

Chapter 15
General-Purpose Input/Output (GPIO)

HCMUS

2024

1
Interfacing Peripherals
 Port-mapped I/O
 Use special CPU instructions: Special_instruction Reg, Port
 Memory-mapped I/O
 Most CPUs these days do I/O via memory mapped I/O
 A simpler and more convenient way to interface I/O devices
 Each device registers is assigned to a memory address in the address space of the microprocessor
 Use native load/store instructions to input or output data: LDR/STR Reg, [Reg, #imm]

0x48000024
0x48000020
0x4800001C
Core Pin output
STR 0x48000018
0x48000014 GPIO Data Output Register GPIO
Output
0x48000010

Memory Space
2
ARM Cortex-M microprocessors use memory-mapped I/O.
Memory Map of Cortex-M4
0xFFFFFFFF
NVIC, System Timer, SCB,
0.5 GB System
vendor-specific memory
0xE0000000

1 GB External Device Such as SD card

0xA0000000

1 GB External RAM 4 GB
Off-chip memory for data

0x60000000
0.5 GB Peripheral AHB & APB, such as timers, GPIO
0x40000000
0.5 GB SRAM On-chip RAM, for heap, stack, & code
0x20000000
0.5 GB Code On-chip Flash, for code & data
0x00000000

3 One Byte (8 bits)

Memory Map of STM32L4
0xFFFFFFFF
0.5 GB System
0xE0000000

1 GB External Device

0x60000000
0xA0000000

…
1 GB External RAM
0x48001000
GPIO D (1 KB)
0x60000000 0x48000C00
0.5 GB Peripheral GPIO C (1 KB)
0x40000000 0x48000800
GPIO B (1 KB)
0.5 GB SRAM 0x48000400
0x20000000 GPIO A (1 KB)
0.5 GB Code 0x48000000
0x40000000
…
0x00000000

4 One Byte (8 bits)

GPIO Memory Map
0x48000400

ASCR
0x4800002C
BRR
0x48000028
0x48000024
AFR[1]
AFR[0]
0x48000020
0x48000400 LCKR
0x4800001C
GPIO A (1 KB) BSRR
0x48000000 0x48000018 48 bytes
0x48000014
ODR
IDR
0x48000010
PUPDR
0x4800000C
OSPEEDR
0x48000008
0x48000004
OTYPER
MODER
0x48000000

5
Each register has 4 bytes.
GPIO Memory Map
0x48000400

Set pin A.5 to high

ASCR
0x4800002C
BRR
0x48000028
0x48000024
AFR[1]
AFR[0]
0x48000020
0x48000400 LCKR
0x4800001C
GPIO A (1 KB) BSRR
0x48000000 0x48000018 48 bytes
0x48000014
ODR
IDR
0x48000010
PUPDR
0x4800000C Set bit 5
OSPEEDR
0x48000008 of ODR
OTYPER
0x48000004 to high
MODER
0x48000000

6
STM32L476
Nucleo ST-Link Debugger

User Push Button

Green LED

STM32L4

7
Output Data Register (ODR)
0x48000017
ODR 1 word (i.e., 32 bits)
0x48000014

0x48000017
0x48000016
4 bytes
0x48000015
0x48000014

Little Endian

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

8
Output Data Register (ODR)
0x48000017
ODR 1 word (i.e. 32 bits)
0x48000014

0x48000017
0x48000016
4 bytes
0x48000015
0x48000014

Little Endian

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1

*((uint32_t *) 0x48000014) |= 1UL<<5;

9 Dereferencing a pointer Bitwise OR

Dereferencing a Memory Address

ASCR
0x4800002C
BRR typedef struct {
0x48000028 volatile uint32_t MODER; // Mode register

0x48000024
AFR[1] volatile uint32_t OTYPER; // Output type register
volatile uint32_t OSPEEDR; // Output speed register
AFR[0] volatile uint32_t PUPDR; // Pull-up/pull-down register
0x48000020
LCKR volatile uint32_t
volatile uint32_t
IDR;
ODR;
//
//
Input data register
Output data register
0x4800001C
BSRR volatile uint32_t BSRR; // Bit set/reset register
0x48000018 volatile uint32_t LCKR; // Configuration lock register
0x48000014
ODR volatile uint32_t AFR[2]; // Alternate function registers
IDR volatile uint32_t
volatile uint32_t
BRR;
ASCR;
//
//
Bit Reset register
Analog switch control register
0x48000010
PUPDR } GPIO_TypeDef;
0x4800000C
OSPEEDR // Casting memory address to a pointer
0x48000008 #define GPIOA ((GPIO_TypeDef *) 0x48000000)
0x48000004
OTYPER
MODER
0x48000000

GPIOA->ODR |= 1UL<<5;
or (*GPIOA).ODR |= 1UL<<5;
10
Dereferencing a Memory Address

ASCR
0x4800002C
BRR typedef struct {
0x48000028 volatile uint32_t MODER; // Mode register

0x48000024
AFR[1] volatile uint32_t OTYPER; // Output type register
volatile uint32_t OSPEEDR; // Output speed register
AFR[0] volatile uint32_t PUPDR; // Pull-up/pull-down register
0x48000020
LCKR volatile uint32_t
volatile uint32_t
IDR;
ODR;
//
//
Input data register
Output data register
0x4800001C
BSRR volatile uint32_t BSRR; // Bit set/reset register
0x48000018 volatile uint32_t LCKR; // Configuration lock register
0x48000014
ODR volatile uint32_t AFR[2]; // Alternate function registers
IDR volatile uint32_t
volatile uint32_t
BRR;
ASCR;
//
//
Bit Reset register
Analog switch control register
0x48000010
PUPDR } GPIO_TypeDef;
0x4800000C
OSPEEDR // Casting memory address to a pointer
0x48000008 #define GPIOA ((GPIO_TypeDef *) 0x48000000)
0x48000004
OTYPER #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
MODER
0x48000000

GPIOA->ODR |= GPIO_ODR_ODR_5;

11
General Purpose Input/Output (GPIO)

 8 GPIO Ports:
A, B, C, D, E, F, G, H

 Up to 16 pins in each port

12
General Purpose Input/Output (GPIO)

D Bus
FLASH
ARM Cortex-M4 I Bus

AHB Bus
Matrix
SRAM
FPU S Bus

GPIO A
GPIO B APB Bus
GPIO C Matrix
GPIO D
GPIO E UART
GPIO F
GPIO G SPI
GPIO H
Timer
…
STM32L4

13
General Purpose Input/Output (GPIO)

D Bus
FLASH
ARM Cortex-M4 I Bus

AHB Bus
Matrix
SRAM
FPU S Bus

GPIO A
GPIO B APB Bus
GPIO C Matrix
GPIO D
GPIO E UART
GPIO F
GPIO G SPI
GPIO H
Timer
…
STM32L4

14
Basic Structure of an I/O Port Bit
Input and Output

Schmitt
trigger

15
Basic Structure of an I/O Port Bit: Output
GPIO Pull-up/Pull-down Register (PUPDR)
00 = No pull-up, pull-down 01 = Pull-up
10 = Pull-down 11 = Reserved

Output
Data Schmitt
trigger
Register GPIO Output Type Register (OTYPER)
0 = Output push-pull (default)
1 = Output open-drain

GPIO MODE Register

00 = Input, 01 = Output,
10 = AF, 11 = Analog (default)
16
Enable Clock
 AHB2 peripheral clock enable register (RCC_AHB2ENR)

SYSCLK Clock for Port A

1 GPIOEN
AND Gate

#define RCC_AHB2ENR_GPIOAEN ((uint32_t)0x00000001U)

RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN;

17
GPIO Mode Register (MODER)
 32 bits (16 pins, 2 bits per pin)

Pin 5 Pin 2 Pin 1 Pin 0

GPIOA->MODER &= ~(3UL<<10); // Clear bits 11 and 10 for Pin 5

GPIOA->MODER |= 1UL<<10; // Set bit 10, set Pin 5 as output

18
GPIO Mode Register (MODER)
 32 bits (16 pins, 2 bits per pin)

Pin 5 Pin 2 Pin 1 Pin 0

#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)

#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)

GPIOA->MODER &= ~(GPIO_MODER_MODER5); // Clear bits 11 and 10 for Pin 5

19
GPIOA->MODER |= GPIO_MODER_MODER5_0 ; // Set bit 10, set Pin 5 as output
GPIO Output Type Register (OTYPE)
 16 bits reserved, 16 data bits, 1 bit for each pin

+ Vcc

D
G
PMOS
GPIO S GPIO
Output Bit Output Pin
0/1 Controller

D
G
NMOS
S

GPIOA->OTYPE &= ~(1UL<<5); // Clear bit 5

Better code:
GPIOA->OTYPE &= ~(GPIO_OTYPER_OT_5); // Clear bit 5

20
In the device header file:
#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
GPIO Input: Pull Up and Pull Down
 A digital input can have three states: High, Low, and High-Impedance (also
called floating, tri-stated, HiZ)

Pull-Up Pull-Down
If external input is HiZ, the If external input is HiZ, the
input is read as a valid HIGH. input is read as a valid LOW.
21
GPIO Output: Push-Pull PUSH PULL

+ Vcc + Vcc

Source
D current
G
PMOS PMOS

GPIO S GPIO GPIO GPIO

Output Bit Output Pin Output Bit Output Pin
0
0/1 Controller 1 Controller
Output is
+Vcc
D
G
NMOS
NMOS
S

GPIO Output = 1
Source current to external circuit

22
GPIO Output: Push-Pull PUSH PULL

+ Vcc + Vcc

D
G
PMOS
PMOS
GPIO S GPIO
Output Bit GPIO GPIO
Output Pin Output Bit Output Pin
0/1 Controller 1
0 Controller
Output is
D Grounded
G
NMOS
NMOS
S Drain
current

GPIO Output = 0
Drain current from external circuit

23
GPIO Output: Open-Drain OPEN DRAIN

GPIO
Output Pin GPIO
Output Pin

Output is
GPIO GPIO Grounded
Output Bit Output Bit
D
G 1
0/1 Controller NMOS 0 Controller NMOS
S
Current

GPIO Output = 0
Drain current from external circuit

24
GPIO Output: Open-Drain OPEN DRAIN

GPIO
Output Pin GPIO
Output Pin

Output is
GPIO GPIO Floating
Output Bit Output Bit
D
G 0
0/1 Controller NMOS 1 Controller NMOS
S

Output = 1
GPIO Pin has high-impedance to external circuit

25
GPIO Output Speed
 Output Speed:
Speed of Rising
 Speed of rising and falling
Low
 Four speeds: Low, Medium, Fast, High
 Tradeoff
Medium
 Higher GPIO speed increases EMI
noise and power consumption
 Configure based on peripheral speed Fast
 Low speed for toggling LEDs
 High speed for SPI High

26
Slew Rate
Slew Rate
Maximum rate of change of the
output voltage

∆𝑉
𝑆𝑙𝑒𝑤 𝑅𝑎𝑡𝑒 = 𝑚𝑎𝑥
∆𝑡

A high slew rate allows the output

to be toggled at a fast speed.

27
GPIO Output: Push-Pull vs Open-Drain

Output Bit Push-Pull Open-Drain

1 High HiZ
0 Low Low

Use push-pull output, instead of open-drain output!

28
GPIO Output Data Register (ODR)
 16 bits reserved, 16 data bits, 1 bit for each pin

Pin 5

GPIOA->ODR |= 1UL << 5; // Set bit 5

Better Code: GPIOA->ODR |= GPIO_ODR_ODR_5; // Set bit 5
The device header file stm32l476xx.h defines:
#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
29
Light up the Green LED (PA.5)

RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN; // Enable clock of Port A

GPIOB->MODER &= ~(3UL<<5); // Clear mode bits

GPIOB->MODER |= 1UL<<5; // Set mode to output

GPIOB->OTYPE &= ~(1UL<<5); // Select push-pull output

GPIOB->ODR |= 1UL << 5; // Output 1 to turn on green LED

30
Light up the Green LED (PA.5)

Better Code:
RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN; // Enable clock of Port A

GPIOB->MODER &= ~GPIO_MODER_MODER5; // Clear mode bits

GPIOB->MODER |= GPIO_MODER_MODER5_0; // Set mode to output

GPIOB->OTYPE &= ~GPIO_OTYPER_OT_5; // Select push-pull output

GPIOB->ODR |= GPIO_ODR_ODR_5; // Output 1 to turn on green LED

31
Push Button ST-Link Debugger

User Push Button

STM32L4

32
User Push Button (PC13)

33
GPIO Initialization
 Turn on the clock to the GPIO Port (e.g. Port C)
RCC->AHB2ENR |= RCC_AHB2ENR_GPIOCEN; Reset and Clock Control (RCC)
 Configure GPIO mode, output type, speed, pull-up/pull-down
typedef struct
{
__IO uint32_t MODER;
__IO uint16_t OTYPER;
uint16_t RESERVED0;
__IO uint32_t OSPEEDR;
__IO uint32_t PUPDR;
__IO uint16_t IDR;
uint16_t RESERVED1;
__IO uint16_t ODR;
uint16_t RESERVED2;
__IO uint16_t BSRRL; /* BSRR register is split to 2 * 16-bit fields BSRRL */
__IO uint16_t BSRRH; /* BSRR register is split to 2 * 16-bit fields BSRRH */
__IO uint32_t LCKR;
__IO uint32_t AFR[2];
} GPIO_TypeDef;
#define PERIPH_BASE ((uint32_t)0x40000000)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800)
34 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Basic Structure of an I/O Port Bit
Input and Output

Schmitt
trigger

35
Basic Structure of an I/O Port Bit:
Output
GPIO Pull-up/Pull-down Register (PUPDR)
00 = No pull-up, pull-down 01 = Pull-up
10 = Pull-down 11 = Reserved

Output
Data Schmitt
trigger
Register GPIO Output Type Register (OTYPER)
0 = Output push-pull (default)
1 = Output open-drain

GPIO MODE Register

00 = Input, 01 = Output,
10 = AF, 11 = Analog (default)
36
Basic Structure of an I/O Port Bit: Input and Output

37
Basic Structure of an I/O Port Bit: Input

Schmitt • Reduce noise

trigger • Increase slew
rate

Input Data
Register (IDR)
Input is sampled into IDR
every AHB clock cycle!
GPIO Pull-up/Pull-down Register (PUPDR)
00 = No pull-up, pull-down 01 = Pull-up
10 = Pull-down 11 = Reserved

38
Schmitt Trigger

V in
Threshold

Analog signals
 Noisy
 Rise and fall slowly (small slew rate)

39
Schmitt Trigger

V in

Threshold

Simple
Comparator

40
Schmitt Trigger

Vout Vin

VTH
Immunity
Vout Band
VTL
0 V in
VTH
Vout
VDD
Schmitt
Trigger
0 V in 0
VTL
Vout VDD
Simple
Comparator
V in 0
0
VTL VTH

Trigger Trigger
Low High

Schmitt-trigger gives cleaner signal on input

41
Enable Clock
 AHB2 peripheral clock enable register (RCC_AHB2ENR)

SYSCLK Clock for Port C

1 GPIOAEN
AND Gate

#define RCC_AHB2ENR_GPIOCEN ((uint32_t)0x00000001U)

RCC->AHB2ENR |= RCC_AHB2ENR_GPIOCEN; // Enable clock of Port C

42
GPIO Mode Register (MODER)
 32 bits (16 pins, 2 bits per pin)

Pin 2 Pin 1 Pin 0

// Set Pin 0 as input

GPIOC->MODER &= ~(3UL<<(13*2)); // Clear bits 27 and 26 for Pin 13
or:
GPIOC->MODER &= ~(GPIO_MODER_MODER13); // Clear bits 27 and 26 for Pin 13

43 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)

 GPIO Pull-up/Pull-down Register (PUPDR)
 16 pins per port, 2 bits per pin

Pin 2 Pin 1 Pin 0

// No pull-up, pull-down
GPIOC->PUPDR &= ~3UL<<26;
or:
GPIOC->PUPDR &= ~ GPIO_PUPDR_PUPDR13;

44 Pull-Down Pull-Up
GPIO Input Data Register (IDR)
 16 bits reserved, 16 data bits (1 bit per pin)

// Demo of reading pin 13

uint32_t mask = 1UL<<13;
uint32_t input = (GPIOC->IDR & mask) == mask;

or

uint32_t input = (GPIOA->IDR & GPIO_IDR_IDR_13) >> 13;

45
Read Input of Pin PC.13
uint32_t input;

RCC->AHB2ENR |= RCC_AHB2ENR_GPIOCEN; // Enable clock of Port C

GPIOC->MODER &= ~GPIO_MODER_MODER13; // Set PC.13 as digital input
GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR13; // No pull-up, no pull-down

while (1) {
// Read pin 0
input = (GPIOC->IDR & GPIO_IDR_IDR_13);

if (input == 0) {
// Button is pressed
...
} else {
// Button is not pressed
...
}
}
46
Keypad Scanning

R1 R2 R3 R4 C1 C2 C3

47
Keypad Scanning

1. Any key pressed?

2. If so, find out:
a) Which column?
b) Which row?
3. Go back step 1

R1 R2 R3 R4 C1 C2 C3

48
Keypad Scanning

49
Keypad Scanning

0 Step 1: Set Output

R1,R2,R3,R4 = 0000

0 Step 2: Read Input

C1,C2,C3 = 111

0
⟹ No key pressed
0

1 1 1
50
Keypad Scanning

Key “0” is pressed

51
Keypad Scanning

0 Step 1: Set Output

R1,R2,R3,R4 = 0000

0 Step 2: Read Input

C1,C2,C3 = 101

0 ⟹ A key in the 2nd column is pressed

Next, find which row

0

52
1 0 1
Keypad Scanning
Scan 1st row

0 Step 1: Set Output

R1,R2,R3,R4 = 0000

1 Step 2: Read Input

C1,C2,C3 = 101

1 Step 3a: Scan 1st row

R1,R2,R3,R4 = 0111
C1,C2,C3 = 111
1
⟹ No key in 1st row is pressed

53
1 1 1
Keypad Scanning
Scan 2nd row

1 Step 1: Set Output

R1,R2,R3,R4 = 0000

0 Step 2: Read Input

C1,C2,C3 = 101

1 Step 3b: Scan 2nd row

R1,R2,R3,R4 = 1011
C1,C2,C3 = 111
1
⟹ No key in 2nd row is pressed

54
1 1 1
Keypad Scanning
Scan 3rd row

1 Step 1: Set Output

R1,R2,R3,R4 = 0000

1 Step 2: Read Input

C1,C2,C3 = 101

0 Step 3c: Scan 3rd row

R1,R2,R3,R4 = 1101
C1,C2,C3 = 111
1
⟹ No key in 3rd row is pressed

55
1 1 1
Keypad Scanning
Scan 4th row

1 Step 1: Set Output

R1,R2,R3,R4 = 0000

1 Step 2: Read Input

C1,C2,C3 = 101

1 Step 3d: Scan 4th row

R1,R2,R3,R4 = 1110
C1,C2,C3 = 101
0
⟹ key in 4th row is pressed

56
1 0 1
Keypad Scanning

1
⟹ The key pressed is in
• the 2nd column and
1 • the 4th row.

57
1 0 1
Keypad Scanning

58
I/O Debouncing
 Example signal when a button is pressed
3

2.5

Voltage across push button

2

1.5

0.5

-0.5
-0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Time (microseconds)

59
RC Circuit: Charging
𝑡
−𝑇
𝑉𝑐 = 𝑉𝑖𝑛 (1 − 𝑒 𝐶)
𝑉𝑐
𝑉𝑖𝑛

𝑇𝐶 = 𝑅𝐶

60
RC Circuit: Discharging

𝑉𝑐
𝑉𝑆

𝑇𝐶 = 𝑅𝐶 𝑡
−𝑇
𝑉𝑐 = 𝑉𝑆 × 𝑒 𝐶

61
Hardware Debouncing
Switch is
Voltage closed.
on Pin
Vdd
Switch bounces
Switch is open. and is open.
Vdd
R1 4.7KΩ
R2
PC13 Switch is
330Ω closed.
0 0.01ms
C1 100nF Push
Button Time
3τ=3*0.033ms≈0.1ms

Voltage
on Pin

Switch bounces
Switch is open
Vdd and is closed.

0 Time
3τ=3*5ms≈15ms
Switch is
62 open.
De-Bouncing
 Hardware De-bouncers
 Simple RC circuit as a low-pass filter
 Software De-bouncing
 Solution A: Read the switch after a sufficient delay to allow the bounces to settle
down
 Solution B: Reading periodically and use a counter as a filter
 Reset the counter when the signal is “unpressed”
 Counts up if “pressed”
 If counter > threshold, the contacts has stopped bouncing

63