PROCESSOR DESIGN AND

COMPUTER ARCHITECTURE
GROUP PROJECT
INTRODUCTION

Group Members
Oluwapelumi Oyetade
Ayomide Shittu
Lauretta Orji-Okafor
Maajo Sanjo-Lawal
Oluwatamilore Animasaun
Lateef Abiodun
Israel Oyekunbi
Omeh Chidi
Ogini Kene
 PROCESSOR
DESIGN OVERVIEW

Outline:
Basic building blocks
How Processors work
Instruction sets
Processor hardware design
Verilog
Processor code and demo
 BASIC BUILDING BLOCKS
The building blocks needed in the
design of digital circuits are gates
and registers.

GATES
They are electronic designs that
perform logical operations on binary
inputs.

Types of gates

XOR Gate DMux Gate

OR Gate
NOT Gate Mux Gate (multiplexer) AND Gate
 TYPES OF GATES

AND Gate: Outputs 1 only if all

inputs are 1. Otherwise, it outputs 0.

.
OR Gate: Outputs 1 if at least
one input is 1. It outputs 0 only
if all inputs are 0.
 TYPES OF GATES

NOT Gate: Inverts the input. It outputs 1

if the input is 0, and vice versa.

XOR Gate: Outputs 1 if the inputs are

different. It outputs 0 if the inputs
are the same.
.
 TYPES OF GATES

Mux Gate (multiplexer): It is also known as a selector. It

connects one input to the output. It is also used to
implement various digital circuits like adders, subtractors,
logic gates e.t.c. An adder adds two numbers and a
multiplier multiplies two numbers. The output of the
multiplier is basically double the input.

Dmux Gate: It is the inverse of a

mux, it connects the input to one of
the outputs and the rest of the
outputs to zero.
 REGISTERS
They are a type of memory used to store bits or numbers and
they run on a repeating square wave called a clock. Input is
stored at the rising edge of the clock only when the enable
signal is high.
HOW PROCESSORS WORK
Processors work by executing instructions
stored in memory but let us dive into the
instruction set first to get a better
understanding of this.
Instruction sets are instructions that tell a
processor to perform a specific task such
as adding two numbers or loading data
from memory.
 Some instruction sets

Add: Adds two numbers and stores the result in a register.

Subtract: Subtracts two numbers and stores the result in a register.
Multiply: Multiplies two numbers and stores the result in a register.

NAND: Performs a NAND operation on two numbers and stores the result in a
register.
Load Word: Loads a word from memory into a register.
Store Word: Stores a word from a register into memory.
The instructions are converted into machine code which is understood by the
processor.
 VERILOG
Verilog: A language for digital circuits.

Verilog is a hardware description

language (HDL) used to design and
simulate circuits. In other words, it
is a programming language for
hardware that allows you to
describe the behavior of electronic
circuits using text-based codes.
 KEY CONCEPTS IN VERILOG

Modules: A module is a self-contained block of code that defines

specific circuits or components. It is like a function in a programming
language, taking inputs, performing operations, and producing outputs.
 KEY CONCEPTS IN VERILOG

Inputs and Outputs: Modules Data types: Verilog has different data
have inputs and outputs, which
types, such as wire, reg, and integer,
connect them to other modules.
Inputs and outputs are received which are used to represent different
and sent by modules. kinds of signals.
 KEY CONCEPTS IN VERILOG

Operators: Verilog uses various Timing control: Timing control constructs like
operators, such as logical, always blocks and initial blocks can be used to
arithmetic, and bitwise operators, specify how the circuit should behave over time.
to perform calculations and Once the hardware design is complete, the
manipulate data. Verilog code is written next to implement the
processor’s logic.
 A simple processor might have the following modules:

Control Unit: Fetches instructions from memory. Decodes instructions to determine the
operation to be performed. Generates control signals to control the ALU, register file, and
memory.
ALU: Performs arithmetic and logical operations on data. Register File: Stores data.
Memory: Stores instructions and data.
 Here is an example of the verilog code:

M4333333module control_unit(
input clk,
input reset,
// ... other inputs and outputs
);

always @(posedge clk, posedge reset) begin

if (reset) begin
// Reset the control signals
end else begin
// Fetch the next instruction
// Decode the instruction
// Generate control signals based on the decoded
instruction
end
end

// ... other Verilog code for the control unit

endmodule
 PROCESSOR DEMO

Stimulation
This is the stimulation of the verilog code once it is written in order to verify its
functionality. Tools used for stimulation include ModelSim or Vivado. These tools are
used to test the processor’s behaviour under different input conditions.

Synthesis
Conversion of high-level language into hardware description language (HDL)
 PROCESSOR DEMO

RUNNING A PROGRAM ON THE PROCESSOR

The program machine code must be loaded into the

memory, the instructions is then fetched from the
processor, decoded and executed. The results ata the
end of the execution are then stored in the memory
or registers.
 RISC-V INSTRUCTION SET

A set of instruction that RISC-V processor can understand and

execute. The RISC-V Instriction Set Architecture (RISC-V ISA) is
divided into several base integer instruction groups, and they all
have specific purpose:
RV32I: This is the base of the integer instruction set, which only
loads and stores of instructions, access memory and arithmetic
instructions, and control flow instructions.
RV32M: Adds instruction for multiplication and division.
 RISC-V INSTRUCTION SET

RV32A: Adds atomic instructions for synchronization

RV32F: Adds double-precision floating-point instruct
RV32D: This extension adds double-precision floating-
point instructions.
The RISC-V ISA is also designed to be extensible, so new
instruction sets can be added in the future.
 FEATURES OF THE RISC-V ISA

Simple instruction set: The RISC-V ISA has a relatively

small number of instructions, which makes it easy to
implement and learn.
Fixed-length instructions: All RISC-V instructions are 32
bits long, which simplifies the hardware design.
Load-store architecture: RISC-V uses a load-store
architecture, which means that data must be loaded
from memory into registers before it can be used in
calculations
 FEATURES OF THE RISC-V ISA

Delayed branch: RISC-V uses a delayed branch

instruction, which allows the processor to execute one
instruction after a branch instruction, even if the
branch is taken.
The RISC-V ISA is a powerful and flexible ISA that is
well-suited for a variety of applications. It is becoming
increasingly popular, especially for embedded systems
and custom hardware designs.
 REFERENCES

https://youtu.be/HCzIK322Pzw?si=LXQVEb8GVLoR0tN7
https://www.numerade.com/ask/question/question-i-
points-explain-the-instruction-execution-cycle-steps-
and-indicate-which-execution-unit-is-used-in-each-
step-37917/
https://www.youtube.com/watch?v=2IReMT_zjK8
https://youtu.be/HCzIK322Pzw?si=LXQVEb8GVLoR0tN7
https://patents.google.com/patent/WO2019133039A1/en
THANK YOU
For Your Attention