RISC-V RV32I RTL DESIGN USING VERILOG HDL
FINAL PROJECT REPORT
UNDER GUIDELINES
Of
MAVEN SILICON
by
CHAKKA LAVISH VAMSI RAJA
20BEV7004
VITAP
Project Overview:
The RISC-V RV32I RTL Design project aims to design a 32-bit RISC-V
processor using the RV32I instruction set architecture. The project
involves the development of the processor's RTL (Register Transfer Level)
design using Verilog HDL (Hardware Description Language) and the
verification of its functionality through simulation.
Top Module Block Diagram and Functionality:
The top module in a digital design is responsible for coordinating the
interactions between various submodules or functional units within the design.
It serves as the main control unit and manages the flow of data and control
signals throughout the design. The top module typically receives input signals,
processes them through different submodules, and generates output signals
accordingly. Its functionality can include tasks such as data routing, signal
synchronization, clock management, and overall system control. Essentially, the
top module acts as the central hub that connects and controls all the
componentsof the design.
MICRO ARCHITECTURE OF RISC-V RV32I :
FINAL UVM VERIFICATION FOR RISC-V RV32I RTL
PASS
SUB MODULES BLOCK DIAGRAM WITH DESCRIPTION AND IT’S
FUNCTIONALITY:
PC MUX:
Hold address of next instruction to be executed, it uses every input to the output
Boot_address to play with every input with its reset.
REG BLOCK 1
It register the pc_mux_in and produces the output at the posedge of clk if
There is no reset.
IMMEDIATE GENERATOR
Rearranges the immediate bits continued in the instruction.
IMMEDIATE ADDER
Addes the immediate bits.
INTEGER FILE WRITE ENABLE GENERATOR
Integer file is a commonly used file format for storing data as plain text, where
each line represents an integer value. It is typically used for input/output
operations in programming, allowing for easy reading and writing of integer
data from/to files.
INSTRUCTION MUX
The instruction mux selects the appropriate instruction based on the control
signals and opcode, enabling the processor to fetch the correct instruction for
execution. It multiplexes between different instructions in the instruction
memory based on the control signals and opcode inputs, providing the desired
instruction to the subsequent stages of the processor for further processing and
execution.
BRANCH UNIT
The branch unit in a processor is responsible for evaluating branch conditions
and determining whether a branch instruction should be taken or not based on
the specified condition, controlling the flow of program execution accordingly.
It compares register values or other operands to determine if the branch
condition is true, and signals the control unit to update the program counter
(PC) to the target address if the condition is met.
Decoder
Decoder Description: A decoder is a combinational logic circuit that takes an
input code and activates a specific output line based on the input code, enabling
a one-to-many mapping.
Decoder Functionality: The decoder decodes the input code and activates a
single output line corresponding to the input code, allowing the selection or
activation of a specific function or device among multiple options.
CSR FILE
CSR (Control and Status Register) file is a special register file in a computer
system that contains control and status information. It provides functionality for
managing system-level operations and monitoring various aspects of the
processor, such as exception handling, memory management, and privileged
instructions.
REG BLOCK 2
Themsrv32_reg_block_2 module is a register block in a processor design,
responsible for storing and synchronizing register values. It uses clock edge-
triggered flip-flops to update the register values based on the input signals
during the rising edge of the clock signal.
STORE UNIT
The store unit in a processor is responsible for handling store instructions,
which store data from a register to memory. It calculates the memory address
based on the instruction operands and data from the source register, and writes
the data to the specified memory location.
LOAD UNIT
The load unit is responsible for handling memory load operations in a processor.
It retrieves data from memory based on the specified memory address and
forwards it to the appropriate destination register or pipeline stage for further
processing or storage.
ALU
ALU stands for Arithmetic Logic Unit, which is a digital circuit within a
processor that performs arithmetic and logical operations on data. It takes input
operands and an operation code, performs the specified operation, and produces
the result as output, supporting operations such as addition, subtraction,
multiplication, logical AND/OR, shifting, and comparison.
WB MUX SELECTION UNIT
Its functionality is to select the appropriate data source for the write-back stage,
typically choosing between the output of the ALU (Arithmetic Logic Unit) and
the data read from memory, based on control signals such as the instruction
opcode or operation type.
OUTPUT WAVEFORMS
PC MUX:
REG_BLOCK_1:
BRANCH_UNIT:
IMM_GENERATOR:
IMM_ADDER:
INTEGER_FILE:
WR_EN_GENERATOR:
INSTRUCTION_MUX:
DECODER:
STORE_UNIT:
REG_BLOCK_2:
LOAD_UNIT:
ALU:
WB_MUX_SEL_UNIT:
THANK YOU
