diagram for this implementation is as shown in Fig. 221. ) CA digital Multiplexer is a / combinational circuit that ; ' selects binary information \ 2.3.4 Multiplexers : Multiplex means “many into one”. A multiplexer is a circuit fom one of many input with many inputs but only one output. Multiplexing means lines and directs it to a transmitting a large number of information units over 2 | single output line smaller of channels or lines. In multiplexer, the selection of a particular input ine is controlled by a set of selection lines. Normally there are 2” input lines whose bit combihations determine which input is selected. ‘A multiplexer (abbreviated MUX) is used when a complex logic circuit is to be shared by a number of input signals. This process is called multiplexing. Let us see how this multiplexer works. You have learnt 2-to-4 decoder (Fig. 2.19) in section 2.3.3. As you know that, in decoders, the input combination decides which AND gate is to be selected for output. Now if you add one more input line to each of the AND gates (i. ‘lines P, O, R, $ are added to four AND gates, one line for one AND gate), the new circuit, would look like [Fig. 2.22(a)]. ie ee a 1. The circuit doing the opposite thing ice, directing single input to multiple output lines, is ” ultiple ines, demult this process is called demultiplexing. hie aang a \ f \ Scanned with CamScanner110 innsenne COMPUTER SCIENCE-Xil (Isc) Now as you see, the input combination of AB would determine = NOTE which of the four AND gates Fy, F,, Fp, F; would be chosen. | 4 multiplexer is also ‘And whichever AND gate is chosen, it would produce the | called data selector as it same result as that of the extra input line to it. For example, if | selects one of the several Fy is chosen, it will produce the same result as that of P which | inputs and then feels it is the extra input line it. (For instance, P is 0, Fy would produce through to a single output. Oand if Pis 1, Fy would produce 1). Similarly, other AND gates produce the same result as that of their extra input line. Now, if you put alll these outputs of AND gates to an OR gate, the circuit is like Fig, 2.22(b) and the final result is the same as that of the extra input line as selected by the input combination. Thus, this circuit is capable of choosing one of the four input lines P, Q, R, S. If you rename A and B as the selector lines Sy and $, and P, Q, R, $as Ig, ;, Iz, 13 (input lines) the circuit is as Fig. 2.22(c) which is nothing but a multiplexer capable of selecting one particular input line out of four. A 8 te) =e te fe ie) ce @ | Bw 2 nel teal aee ERE (a) Ordinary Decoder (2 to 4) with extra input lines to each of the AND gates. a Ss Figure 2.22 (b) Decoder outputs input to OR. (0) A multiplexer. Scanned with CamScannerCOMPUTER HARDWARE Now the function table of 4 to 1 line multiplexer can be written as table 2.18. Table 2.18 [os % Y 0 0 ij o 1 i 1 0 h a 1 ky The block diagram of 4 to 1 line multiplexers would be as follows : Inputs cree MUX SS Select woneeneree 111 | output Figure 2.23 Block diagram for 4 x 1 MUX. Scanned with CamScanner