EECE 303 - Digital Electronics
Multiplexers and Demultiplexers
Week 6
Jawad M. Rubayat Dhrubo
Lecturer
Dept. of EECE
Multiplexers
A multiplexer (MUX) is a device that allows digital information from several
sources to be routed onto a single line for transmission over that line to a
common destination.
The basic multiplexer has
• Several data-input lines
• A single output line.
• It also has data-select inputs
(Normally, there are 2n input lines and n selection lines whose bit
combinations determine which input is selected)
Data-select inputs permit digital data on any one of the inputs to be switched
to the output line. Multiplexers are also known as data selectors.
Multiplexers
4-to-1 line MUX
• If a binary 0 (S1 = 0 and S0 = 0) is applied
to the data-select lines, the data on input
D0 appear on the data-output line.
• If a binary 1 (S1 = 0 and S0 = 1) is applied
to the data-select lines, the data on input
D1 appear on the data output.
• If a binary 2 (S1 = 1 and S0 = 0) is applied,
the data on D2 appear on the output.
A 2-bit code on the data-
select (S) inputs will • If a binary 3 (S1 = 1 and S0 = 1) is applied,
allow the data on the the data on D3 are switched to the
selected data input to output line.
pass through to the data
output.
Multiplexers
Multiplexers
The AND gates and inverters in the multiplexer resemble a decoder circuit, and
indeed, they decode the selection input lines. In general, a 2n-to-1 -line
multiplexer is constructed from an n-to-2n decoder by adding 2n input lines to it,
one to each AND gate. The outputs of the AND gates are applied to a single OR
gate.
The size of a multiplexer is specified by the number 2n of its data input lines and the
single output line.
The n selection lines are implied for the 2n data lines. As in decoders, multiplexers
may have an enable input to control the operation of the unit. When the enable
input is in the inactive state. the outputs are disabled, and when it is in the active
state, the circuit functions as a normal multiplexer.
Multiplexers
• It was shown that a decoder can be used to implement Boolean
functions by employing external OR gates.
• An examination of the logic diagram of a multiplexer reveals
that it is essentially a decoder that includes the OR gate within
the unit.
• The minterms of a function are. generated in a multiplexer by
the circuit associated with the selection inputs,
• The individual minterms can be selected by the data inputs.
• Thereby providing a method of implementing a Boolean
function of n variables with a multiplexer that has n selection
inputs and 2n data inputs, one for each minterm.
Multiplexers
Examples
• Implement F(A,B,C,D) = σ ( 1, 3, 4, 11, 12, 13, 14, 15) using 16x1, 8x1, 4x1 MUX
• Implement the logic function A⊙B⊕C using 4x1 MUX.
• Implement XNOR logic using 2x1 MUX.
• Implement 1-bit binary full adder using 4x1 MUX
A B C D F
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Demultiplexers
• A demultiplexer (DEMUX) basically reverses the multiplexing
function.
• It takes digital information from one line and distributes it to a
given number of output lines.
• For this reason, the demultiplexer is also known as a data
distributor.
• As you will learn, decoders can also be used as demultiplexers.
Demultiplexers
The figure shows a 1-line-to-4-line demultiplexer (DEMUX) circuit.
• The data-input line goes to all of the AND gates.
• The two data-select lines enable only one gate at a time
• The data appearing on the data-input line will pass through the selected gate to the
associated data-output line.
Demultiplexers
4-Line-to-16-Line Decoder as a Demultiplexer
In demultiplexer applications,
• the input lines are used as the data-
select lines.
• One of the chip select inputs is used as
the data input line,
• with the other chip select input held
LOW to enable the internal negative-
AND gate at the bottom of the diagram
Demultiplexers
Examples
• Implement F1(A,B,C) = σ ( 0,1,4,6) 𝑎𝑛𝑑 F2(A,B,C) = σ ( 2,6) using a demux when
I. When o/p are complemented
II. When o/p are not complemented
A B C F1 F2
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Exclusive-OR AND equivalence functions
Exclusive-OR AND equivalence functions
Exclusive-OR AND equivalence functions
Exclusive-OR AND equivalence functions
Parity generation and checking
Parity generation and checking
