ME 4710 Motion and Control
Frequency Response Design of a Phase-Lag Compensator for a
Spring-Mass-Damper (SMD) Positioning System
o To illustrate the frequency response design of a phase-lag compensator, consider the
following SMD positioning system controlled by the compensator Gc (s) . Here, X d ( s)
and X ( s ) are the desired and actual positions of the mass.
SMD
X d ( s) + 1 X (s)
Gc (s)
s 2 2s 2
o Proportional control ( Gc (s) K ): Large gains are required to control steady-state error
to a step input. Unfortunately, large gains produce undesirable, oscillatory closed-loop
response. Below, we design a phase-lag compensator to lower the steady-state error
without introducing highly oscillatory behavior.
Problem: Design a phase-lag compensator so the closed-loop system has a steady-state
position error ess 1 xss 0.1 to a unit step input and a phase margin
PM 45 (deg) . Plot the step response of the resulting closed-loop system.
Frequency Response Design M-file: PhaseLagPositionControlSMDwithBode.m
Step 1: Determine the compensator gain required to satisfy the error specification.
The steady state error can be defined in terms of the loop transfer function as
1 1 1
ess lim 0.1
s 0 1 GH ( s )
1 K 2 1 Kp
So, K p 9 and K 18 .
Step 2: Evaluate the phase margin of the uncompensated system with K 18 .
Using MATLAB, the phase margin of this (the uncompensated system) is
PM 28 (deg) . See plot below. This is well below the desired phase margin.
Kamman – ME 4710: page 1/4
Phase Margin of
Uncompensated System is
28 (deg) at 4.2 (rad/s)
Step 3: Locate the zero of the compensator
By examination of the Bode diagram, we see that the phase margin requirement would
be satisfied at 2.74 (rad/sec). This statement assumes the magnitude plot crosses over
the zero dB line at this point. So, we locate the zero of the compensator at least one
decade below this frequency, for example, at 0.25 (rad/sec).
Step 4: Locate the pole of the compensator
To make 2.74 (rad/s) the zero dB crossover point, we require approximately 8 dB of
attenuation from the compensator. (See Bode plot of uncompensated system.) We
now calculate by setting 8 20log( ) to find 0.3981 . Our first iteration
yields the compensator
s 0.25
Gc ( s) 0.3981 (Phase-lag compensator)
s 0.0995
Step 5: Check the phase margin of the new compensated system.
The Bode diagram of the loop transfer function of the compensated system
s 0.25 18
GH ( s) 0.3981
s 0.0995 s 2s 2
2
shows that the phase margin is PM 43.7 (deg) , satisfying the original requirement.
Kamman – ME 4710: page 2/4
Phase Margin of Compensated
System is 43.7 (deg)
Step 6: Repeat steps 3-5 until the desired phase margin is obtained.
Our compensated system nearly meets the specification. We will use this result.
Step 7: Check the step response.
Step response of the uncompensated system shows a large overshoot (about 49%) and
low damping (settling time of 3.78 seconds), while the step response of the phase lag
compensated system shows a smaller overshoot (around 22%) with higher damping and
a longer settling time of 7.7 seconds. So, the reduction of overshoot comes at the price
of increasing the settling time.
Step Response of Compensated
System has less overshoot and
more damping than the
Uncompensated System.
Unfortunately, it also has a longer
settling time. This is typical of
integrator-type compensators.
Kamman – ME 4710: page 3/4
Frequency Response of Compensated Closed Loop System:
The frequency response of the closed loop system is shown below. The bandwidth of
the closed loop system is approximately 4 (rad/s).
Kamman – ME 4710: page 4/4
