APB Master/Slave input output signals
PCLK – Input for both Master and Slave
PRESETn – Input for both Master and Slave
PADDR – Master output ,input to Slave
PSELx - Master output ,input to Slave
PENABLE - Master output ,input to Slave
PWRITE - Master output ,input to Slave
PWDATA - Master output ,input to Slave
PWRITE - Master output ,input to Slave
PREADY - Slave output ,input to Master
PRDATA - Slave output ,input to Master
PSLVERR - Slave output ,input to Master
Setup Violation
Timing paths
1. Input to Flip flop (5)
P1 – A through MUX1 to FF1
P2 – B through MUX1 to FF1
P3 – C through MUX2 TO FF2
P4 – D through OR1 to FF3
P5 – D through MUX3 to FF4
2. Flip flop to Flip flop (6)
P1 - FF1 TO FF2
P2 – FF1 TO FF1
P3 - FF1 TO FF3
P4 – FF3 TO FF4
P5 – FF2 TO FF2
P6 - FF4 TO FF4
3. Flip flop to output (4)
P1 – FF2 TO X
P2 – FF2 TO Y
P3 – FF3 TO Z
P4 – FF3 TO Y
4. Input to Output (0)
Design Code :
module four_ff_with_mux (
input wire clk,
input wire A,
input wire B,
input wire C,
input wire D,
output reg Q1,
output reg Q2,
output reg Q3,
output reg Q4,
output reg x,
output reg y,
output reg z
);
reg m1;
always @(posedge clk) begin
m1 <= B ? A : Q1;
Q1 <= m1;
Q2 <= C ? Q1 : Q2;
Q3 <= (m1 | D);
Q4 <= D ? Q3 : Q4;
x <= Q2;
y <= Q2 | Q4;
z <= Q4;
end
endmodule
Testbench :
module tb_four_ff_with_mux;
reg clk;
reg A, B, C, D;
wire Q1, Q2, Q3, Q4, x, y, z;
four_ff_with_mux uut (
.clk(clk),
.A(A),
.B(B),
.C(C),
.D(D),
.Q1(Q1),
.Q2(Q2),
.Q3(Q3),
.Q4(Q4),
.x(x),
.y(y),
.z(z)
);
always #5 clk = ~clk;
initial begin
integer i;
for (i = 0; i < 16; i = i + 1) begin
A = i[3];
B = i[2];
C = i[1];
D = i[0];
$monitor("Time: %0t, A = %b, B = %b, C = %b, D = %b, Q1 = %b, Q2 = %b, Q3 = %b, Q4 = %b, x = %b,
y = %b, z = %b",
$time, A, B, C, D, Q1, Q2, Q3, Q4, x, y, z);
#10;
end
$finish;
end
endmodule
