Port-Mapped I/O vs.
Memory-Mapped I/O
1. Port-Mapped I/O (PMIO):
o Uses separate I/O address space and special instructions (IN, OUT) for data
transfer.
o Example: x86 architecture.
2. Memory-Mapped I/O (MMIO):
o Treats I/O devices as part of memory, accessed with normal memory
instructions (LOAD, STORE).
o Example: ARM architecture.
Key Difference: PMIO has separate address space, while MMIO shares address space with
memory.
Handshaking and Data Conversion
1. Handshaking:
o Synchronizes sender and receiver using signals (e.g., Ready, Acknowledge).
o Ensures reliable communication without data loss.
2. Data Conversion:
o Converts data formats, such as:
Parallel to Serial: For transmission.
Serial to Parallel: For processing.
Example: UART handles both handshaking and data conversion for communication.
Synchronous vs. Asynchronous Data Transfer
1. Synchronous Transfer:
o Data is sent at regular intervals, synchronized by a clock signal.
o Sender and receiver share the same clock.
o Faster and suitable for continuous data streams.
o Example: Data transfer in CPUs and memory (DDR RAM).
2. Asynchronous Transfer:
o No clock signal; data is sent with start and stop bits.
o Sender and receiver operate independently.
o More flexible and reliable over long distances.
o Example: UART communication.
Key Differences:
Feature Synchronous Asynchronous
Clock Signal Required Not required
Speed Faster Slower
Feature Synchronous Asynchronous
Complexity Higher Lower
Example Memory buses, SPI UART, RS232
Advantages
1. Synchronous:
o High-speed communication.
o Efficient for large, continuous data.
2. Asynchronous:
o Simple implementation.
o Suitable for variable or bursty data.
Handshaking Method for Asynchronous Transfer
Handshaking Steps:
1. Sender asserts a signal (e.g., "Data Ready").
2. Receiver responds with an acknowledgment signal (e.g., "Ack").
3. Data transfer begins after acknowledgment.
Example: UART uses start/stop bits and optional control signals (e.g., RTS/CTS) for
asynchronous handshaking.
Modes of Data Transfer
1. Programmed I/O:
o CPU actively checks (polls) the I/O device for data transfer.
o Advantages: Simple to implement.
o Disadvantages: CPU is fully occupied, wasting time in polling.
2. Interrupt-Driven I/O:
o I/O device interrupts the CPU when it is ready for data transfer.
o Advantages: CPU is free to perform other tasks.
o Disadvantages: Slower for large data transfers due to frequent interrupts.
3. Direct Memory Access (DMA):
o Data transfer occurs directly between memory and the I/O device, bypassing the
CPU.
o Advantages: High-speed transfer and CPU is free for other tasks.
o Disadvantages: More complex and requires a DMA controller.
DMA Controller Operations
1. Steps:
o CPU initializes DMA by providing source, destination, and transfer size.
o DMA controller takes control of the system bus to perform data transfer.
o Upon completion, it sends an interrupt to the CPU.
2. Transfer Modes:
o Burst Mode: Transfers a block of data without releasing the bus.
o Cycle Stealing Mode: DMA transfers one word of data per bus cycle, allowing CPU
usage in between.
o Transparent Mode: DMA transfers data only when the CPU is idle.
Example: Hard disk to memory data transfer uses DMA for efficiency.
Interrupt Structure of 8085
1. Types of Interrupts:
o TRAP:
Non-maskable, highest priority.
Used for critical events like power failure.
o RST 7.5, 6.5, 5.5:
Maskable and vectored interrupts.
Prioritized as RST 7.5 > RST 6.5 > RST 5.5.
o INTR:
General-purpose, maskable, non-vectored interrupt.
Requires external hardware to provide the address of the ISR.
2. Maskable vs. Non-Maskable Interrupts:
o Maskable: Can be disabled or ignored by software (e.g., RST 7.5, INTR).
o Non-Maskable: Cannot be disabled and must be serviced (e.g., TRAP).
3. Interrupt Service Routine (ISR):
o A specific routine executed when an interrupt occurs.
o Steps:
1. Save the current state (registers, program counter).
2. Execute the ISR.
3. Restore the saved state and resume normal execution.
Example: When RST 7.5 triggers, the CPU jumps to its predefined memory location to
execute its ISR.
