Clockee D itp-fiop

S
D 9
tnable F

R
L R 9

.S
EN S R gnr
0 0 EN

O -

X gn (nochong )

he Rand s hpuks s dhoon Po

Ihe addPPon kwo ANO goles at
wl ußult pep hat Can be enabled ou
thak
elPsabled.
he R and6
lhen th tnable Pnput Ps hig Pnyoumafion at
he Oupur. The lalch s
AIPH be huonkmflld cluectly
hlPlI Chunge Mspons
SaPd to be enable. The 0uput
enable high. Alhen he
long he
nput Chonges wil uelan the nloumahon
eneble nput gos low, the Output
Nhen he hfgh-to -
low
tha ltt DAuesent 0 he hpuf
s Calleel a 9aled o
huans?hon took place. ThPs
JUplop
tu h- Ieble nof JusF dPmply e
Clocked tp-lop The
s becaLge hle mus (cnsdes two aeot
ThS
Snt1 time, he hme befouehe Enable gotes locd
Pnskrn s
enobles goes low Qntl.
n Gand he Hme Just at
have
he op Ps cl'sabed &R Ond S
Erl=
hlhen X
he, hes hul Jable tnhuy o R ond S
no
 CUO

The he
Cus lon lou On
Chonge
put
goes
p i e s c n t

Ane
enable t h e t
callel he
n o m a fon
J e p

RS pop
not dnply9
able Oulput

The truuth Cons des uwO cllluent

we
mus he enaole
becuSe beloue
+me
enable
me the
JusF Vallo goes o
me dsable Re
e Go he
& the
he
when e n =O

-Jan-2023
Clocked D Tap- Flops
O

C
En

SR FE

Last 6tate

Set
o Reset
Jnva lPel,
 EDG
En D
O

DO

S Co) DueviouS

En

D- Flp Flop.

D-fiio Fiop Ps noth but a clala

lop lop th
out P
lop s clsapleed
En
cwhen en o
ronspaorent ehen hign
en s lous both AND gatus Cuue cls abled
When
Ulthout the value
0 Can Chonge Value ecking
When En s hgh both AND ales
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9 elealns 04 6loues the
Alhn En Gos o
last Value NPII
clont Caue
hlh?e hlhen En 8
ts las hate
Hemain Latch Pn
lag t Va luue
akes he
hegh En hgh
9 the
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0 hat
Lash
3 J-k maslu 6lave
maslw Slaue

CIK

K
D
AcHo0
O O
Mo change
RESET
O
SET

Toggle
ve leve
level gle 8slave
ye
The mask
to
Plsd&k Hpots beoue
maslau Hesponcs
hugge the
clock
dETS On the tve
maske
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the
the
I. huons?lobn
an
an he PT
RESE TS
maskx
maskx
mask
=1 he
he
Outpot
2. J= O & K 9
femplPma
the Cloch The heh he olave the masl
On
to he K oput on he p
gocs both high i toggles
Jk nput e oggele on
Slave har
he Clock & the
AIT
cleabled
Cloch
O then lp-lep
9
LLemafnS
unchangedl
 d-R Hp top
4 hulggorec
Edge

D
CIK

K ot A ion
G
O n(lastSltAlo chonge
RESET
SET

Toggie
dues
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Clock genuaiogd-k fop he

tve pul&e he baBfc Cecai nHalto thepulyeou8

lop P h tuwo imp adldPhion
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the bo
he
The Q0uput s onneced b back npot back tohe
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AO galgaod 9Oupu
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L.hen K 0Le both oud both ANO gdes ue
Clock p1 lses have no ben K ae
uekaens P e Va lue.
both O. g gate
gal sceableel,
dlablecd, do
do
3. 1ow 4 R high, the CPpu
2. hen J he Only posbflpty Ps
hwe s no AlCUy 10 the pp a RESET pulse
teset. Mh1n 9 8 high he louw pa&e3

On next +ve clock

3 Joo the low gale dhebled
8 hgh & k
3, When
PmpokPble RE6ET the p-{lop. When 9 lo
passes a SET peulse on he
& g s high the uppo gole
nekf tve
6 pos?ble
to

SET
SET
bo th hfgh
4. Alhen J4k se
he bov golc pa
hfghhe
a ueßet pulse
RESET he Jlflop 9
he otha hand g s lou he Oppo
On the next pl On
SET Du lSe Jol Kal mean fhe
got pus es PI Thdoue
p-lop oggle On he ntxF tve Clock edge
 F
5 Postve thuigga

D 9.
CK

AcHon
SK Qntl
S- Nb chong

D 0
RESET
6ET

TnvalPd

K D R

to a gotil RS p-op
The pos?Re hilggor pplred Rs 2
stcsult 8 a pes9Aa edge huegged
tht the dymbol Paeleates that
The mall tsufangle nstde
Slolt Al?th tye
only huaiyged
on heunge Clocks puodoces vo nwouo

Each PT the
he
he clock. to he AND gate
that applled ond
PT
actve only when pr high
The AND galt this hof
Con hong. 6hale Only claulng
time pulod.

CIK
L
PT
Ito u

S TL
loe Gat daleh
the easiest way lo
to Consruuct a
P p
One
One
s nvestkors docles
Feeelboek lhe

Va

INVA INVB

BPslable CucePt to the

nveulor B back
The 1e ConnecHn9 he Output
a8 fudback 1Pne
Pne
A Meonecl
npot nvextou Jeeclback Ihe
Coneider V a3

For Pnslance remove the 6Panals

input Va Output. Thoe e onlyOnly t o po8fble
O
V DC O H Pe, t5 VDC
(ause
B NOR
NoR A
R
N2

NOR B R AcHon
hes achially has uvo Lash slo dhange
The lepop mee onoual tumS
Sate
deiog ET
Octtput
0 RESE
foubrlden

Grate lalch
NAND R 59
das Salo
S

2 Fobellen
9 slANO
P
gale AP
a
puf to
RS pop Ps low any
any St the laleh
hPgh. Thus a on S mpot wll
Pls Ou tpor loco both
JouCe wPll reset P (g-0). T bo1
g-1&9=0). A lo On he R opot
96 pe ytou8
R&S e high, the lep wPll ema fh
boh R 9 low 6multoneously 8 joubtdden
Slott. Sefng
Snce hs oce bolh 9 hign
high
 Mon Memou

PaocesoH memo

Contol
PC Ro
R ALU PuoceMo
IR
Ros
h g n qenuual puwpole
uegPsky
I . ) puumonce

Ihe mos mp
onp meaBwte peyoumance a Compule hou
guic hly9 Con execule PuOgiom8.
Ihe dpeed a Computot qectedlby by he destgn
) Tnshuwctfon et
)Hadawaxe the tchnology whfth the
hasdeawe
mplemente
3) aofloare heluelng he oposuong oyskm

BecoetiSe PuocuamS ase uually wullio n a HLL Deusumace

scalso allecTed by he Compila haf tuonslats putoguoms
to machne ongaa ge .
ne Cewuy desPn (ompPlo
he
Fo begt puefotmonce,
machYne nshuocHon 6et handuwasHe Co-dPncuTed way.

Matn Cauche
momou
Pauoceso
memgy

Bus

execuHon, all puOgRam inshuucons CacLe

A the last
Sloue c dhe matn memo
nstuochon CHe Jetched nb the Duocesot
7 execution puoceeels,
and a (opy PS placec h the Cache
needecl a cend Hone
dale, he dame hShuuchon

Head dPueclyuOm he Cache

PPs
exeute ast momnF dale
O P be
puoguam
memouy & he puocesOH
malo
behween he usYng he t Ccuche
achPveelby
minfmzed whPch
COMPUTER ORGANIZATION
PERFORMANCE
The most important measure of performance of a computer is how quickly it can execute programs.
The speed of a computer is affected by the design of

Hardware &the technology in which the hardware is

implemented
3) Software including the operating system.
Because programs are in a
usually written also
HLL, performance is
translates programs into machine language. (HLL High Level Language.
affected by the compiler that
F o r best performance, it is necessary to design the compiler, machine instruction set and nardware in
a co-ordinated way
Let

Main Cache
memoy mmon

hgure 15 The processor coche

examine the flow of program instructions and data between the memory & the processor.
At the start of execution, all program instructions are stored in the main-memory.
tne cdcne.
AS executton procEEds, nstructions re etcned nto e Processodna coPypidce
directiy ronm cdu
the cache.
.A program will be executed faster
t movement of instruction/data between the main-memory and the processor is minimized
which is achieved by using the cache.

PROCESSOR CLOCK
Processor circuits controlled by a timing signal called a Clock.
are
The dlock defines regular time intervals called Clock Cycles.
T o execute a machine instruction, the processor divides the action to be performed into a sequence
of basic steps such that each step can be completed in one dock cyde.

LetPuength of one ciock cycle

Relation between P and R is given by

P
Ris measured in cycles per second.
Cycles per second is also called Hertz (H2)

BASIC PERFORMANCE EQUATION

Let T Processor time required to executed a program.
N - Actual number of instruction executions.
S Average number of basic steps needed to execute one machine instruction.
R= Clock rate in cycles per second.
The program execution time is given by
r-

Equl is referred to as the basic pertormance equation.

-(1)
To achieve high pertormance, the computer designer must reduce the value of T, which means
T h e value of Nis reduced if source program is compiled into fewer machine
instruction5
T h e value of S is reduced if instructions have a smaller number of basic steps to perform.
T h e value of R can be increased by using a higher trequency clock
Care has to be taken while modifying values since changes in one parameter may affect the other.

1-32
 COMPUTER ORGANIZATION_
CLOCK
RATE
There are 2 possibilities for increasing the clock rate R:
uits
step. (IC integrated circuits).
This allows the clock period P to be reduced and the dock rate R to be increased.
2) Reducing the amount of processing done in one basic step also reduces the clock period P.
I n presence of a cache, the percentage of accesses to the main-memory is small.
Hence, much of performance-gain expected from the use of faster technology can be realized.
The value of T will be reduced by same factor as R is increased S& Nare not affected.

PERFORMANCE MEASUREMENT
Benchmark refers to standard
task used to measure how well aprocessoroperates.
The Performance Measure Is the time taken by à computer to execute a given Dencnmark.
r e s u i t s tor different application
domains. (SPEC formance Evaluation Cororatio
SPEC Rating is 9iven by

SPEC rating Kuning line on the relerene conpule

Running tdime on the compuler under test
SPEC rating= 50 The computer under test is s0 times as fast as reference-computer.
The is the SPEC
test repeated tor all programs in the Suite.
Let
Then, the geometric mean of the results is computed.
SPECRating for program in the suite.
Overall SPEC rating for the computer is given by

where n = no. of programs in the suite.

RUCTION SET: CISC AND RISC

CISC
Simple instructions taking one cycle.
Instructions are executed by hardwired control
Complex instructions taking multiple cycle.
Instructions are executed by microprogrammed
unit. control unit.
Fewinstructions. Many instrUctions.
Fixed tormat instructions. vdridDie TOrmat instructionsS
Many addressing modes.
Few addressing modes, and most instructions
haveregister to register addressing mode
Multiple register set. Singleregister set.
Highily pipelined. I No pipelined or less pipelined.
Problem 1:
List the steps needed to execute the machine instruction:
Load R2, LOC
in terms of transfers between the components of processor and some simple control commands.
that the address of the memory-location containing this instruction is initialy in register PC.
ASSume
Solution:
1.2. Transfer the contents of register PC to register MAR.
Issue a Read command to memory
And, then wait until it has transferred the requested word into register MDR.
ecode t.
T or he address LOCA from IR to MAR.
5. Issue a Read command and wait until MDR is loaded.
6. Transfer contents of MDR to the ALu.
7. Transfer contents of RO to the AL..
Perform addition of the two operands in the ALU and transfer result into RO.
9. Transfer contents of PC to ALU.
10. Add 1 to operand in ALU and transfer incremented address to PC.

1-32
COMPUTERORGANIZATION
BYTE-ADDRESSABTLITY
I n byte-addressable memory, successive addresses refer to successive byte locations in the memory.
Byte locations
Ifthe word-length is 32 bits, successive words are located at addresses 0,
having 4 bytes.
4, 8. . with each word

BIG-ENDIAN & LITTLE-ENDIAN ASSIGNMENTS

There are two ways in which byte-addresses are arranged (Higure 2.3).
1 Big-Endian: Lower byte-addresses are used tor the more signiicant bytes ot the word.
2) Little-Endian: Lower byte-addresses are used for the less significant bytes of the word
I n both cases, byte-addresses 0, 4, 8. . . .. are taken as the addresses of successive words in the
memory.
Word
address Byte address Byte addrcss

23

(a) Big-endian assignment (D) Litile-endian assignment

Figure 2.3 Byte and word addressing
Consider a 32-bit integer (in hex): Ox12345678 which consists of 4 bytes: 12, 34, S6, and 78.
ence this integer wi Occupy Dyres in memory. a r d n g 9 1000.

On little-endian, memory will look like

Address VaTue

34
100

On big-endian, memory will look like

AddressValue
1000

1003 78

wORD ALIGNMENT
Words are said to be Aligned in memory if they begin at a byte-address that is a multiple of the
inà wora.
number of bytes
For example,
the word length is l6(2bytes), algned words begin at byte-addresses 0, 2, 4
I f the word length is 64(2 bytes), aligned words begin at byte-addresses 0, 8, 16 .
rde
Words are said to have Unaligned Addresses, if they begin at an arbitrary byte-address.

1-32
 Moclule-04

OmpulotCugonPzalon
Funclon al Un?ts
keyboar
baaio
Contrel uai
Mem ouy
Stouoqe dev?ce
ArithmoPe &
ALUT
loge un?
MONTe

Input UnPt (Ompaleterpect ocdcled olourmaHon

Unsts t whfch sead heodafa
thuough pot
Ho Ex keybocued,t moccse eke.

pues ec the Coeespondfng lellsu

Alhen C Key
to Ps
tronsBafëcd
cli ufomahially
tronsm?Iec Ovo Cable
Coxnespondhg bnaxy Code
|h puoceesgl
memouy

Mimouy Un?t The punc hion the memouy OnfE

dafa here Que
to orove puOuomnms

wo mimou 6houage Putmcisey 8

pes
dtcond au y memouy
Jest memouy hat Operateg
Prmany
at eleconc opeec uoguoms most 6foe
Cohentu3he) aue been executed.
the memgu
 hulthne he Onc
(ogie Untt (BLU nat
Cpewahons erccos the HU
Duocek oo Bppot too nurnbus locatrd te
CuLe two be added hu uve
puoce8
buo to e
And he achual acld4Fan Out
ALU. The
mauy
OcmQLu e MGlelned
non be
6laud
the puoceo
Output OnfF 3
The
Coun tou S Output un?t
PHe
paut he unft
to Dend puOCee puncHen
Hezult to the
weuld. okPde

UpPt he memoy , ALU,

Sloue &
puoces afauncefon poro é
opetations

basfc Opuiationa (oncepts

Main MemoLys
MAR-
 ELG3.

Memouu Opuualfons.

Both puoquam
CLe gShoted
nstmochons and clala Opands
the mem oHy to exe ceuti on
suoc on he uoces oy ContuolCGce?smus
laust he 1woud Conkning the be
nshuuction
huan&ued Lom the 9Y to
mem The PO CeBO.

oae Opuuationse
p tuonsp he opy heConkn
SpaeP memoy locaffoncto heo oces
Fhe meunouis Contnts emah nchange
Suat (oacs Opuafioo he Duo ce59H dnds
he acleluess he cles huee locafion o
Conent o
he mrm
ou Llcguest nat
b Mad.

TMasre opera hon. ontont ouio tien uom

huonsJow and

the Duocs to a,nOpeilfe mem&y lotaffon

Contens thaf locatio
he oumau
elshuoing
the desie
.deols he adedues
he Puoteso he clata
he mimauy Oquthu
locaton hat
locctron.
o b ehunsthto