Chapter 6

Registers and Counters

• Registers
• Shift Registers
• Ripple Counters
• Synchronous Counters
• Other Counters
Registers

• Clocked sequential circuits consists of:

– a group of flip-flops and combinational gates
– connected to form a feedback path
• Flips Flops are essential because in their absence,
the circuit reduces to purely combinational circuit.
(provided there is no feedback among the gates)
• Circuits that include flip flops are usually classified
by the function they perform
• Two such circuits are registers and counters
Registers

• Register
– A register is a group of flip-flops, each flip flop capable of storing
one bit of information
– A register may have combinational gates that determine how the
information is transferred into the register
– An n-bit register consist of a group of n flip-flops capable of storing
n bits of binary information. There are different types of registers
available commercially
• Counter
– A counter is a special type of register that goes through a
predetermined sequence of states.
– The gates in the counter are connected in such a way to produce the
prescribed sequence of binary states
 Simple Register
• The simplest register is one that
consists of only flip flops without any
gates
• A n-bit register consists of n flip-flops
capable of storing n bits of binary
information
• Fig shows a 4-bit register with four D-
type flip flops. The information is
loaded in parallel.
• The four outputs can be sampled at
any time to obtain the binary
information stored in the register
• The clear input goes to R (reset) input
of all four flip flops
• When this input goes to zero all flip
flops are reset (to all 0’s)
asynchronously
Register with Parallel Load
• Synchronous digital systems have a master clock
generator that supplies a continuous train of clock
pulses
• A separate control signal must be used to decide
which specific clock pulse will have an effect on a
particular register
• The transfer of new information into a register is
referred to as loading the register
• If all the bits are loaded simultaneously with a
common clock pulse we say that the loading is done
in parallel
• A clock edge applied to C inputs of the register (fig 6-
1) will load all inputs in parallel
• If the content of the register be left unchanged then
the clock must be inhibited from reaching the register
Register with Parallel Load

• The clock can be inhibited from reaching the register

by controlling the clock input signal with an enabling
gate. Clock pulses perform the logic
• This insertion of gates produce uneven propagation
delays between the master clock and the inputs of flip
flops
• To synchronize the system we must ensure that clock
pulses must arrive at the same time anywhere in the
system so that all flip flops trigger simultaneously
• Performing logic with clock pulses, inserts variable
delays and may cause the system to go out of
synchronism
• For this reason it is advisable to control the operation
of register with the D inputs rather than controlling the
clock in the C inputs of flip flops
4-bit register with parallel load

load'
load
Register with Parallel Load
• A 4-bit register with a load control input that is
directed through gates and into the D inputs of the flip
flops is shown in fig 6-2
• The load input to the register determines the action to
be taken with each clock pulse
• When the load input is 1, the data in the four inputs
are transferred into the register with next positive
edge of the clock
• When the load input is 0, the outputs of the flip flops
are connected to their respective inputs
• The feedback connection from output to inputs is
necessary because the D-flip flop doesn’t have a “no
change” condition
• With each clock edge the D input determines the next
state of the register. To leave the output unchanged it
is necessary to make the D input equal to present
value of the output
Register with Parallel Load

• The clock pulses are applied to the C inputs at all

times. The load input determines whether the next
pulse will accept new information or leave the
information in the register intact
• The transfer of information from the data inputs or the
outputs of the register is done simultaneously with all
four bits in response to clock edge
Shift Registers

• A Shift register is a register capable of shifting its

binary information in one or both directions
• It consists of a chain of flip flops in cascade, with
output of one flip flop connected to the input of next
flip flop
• All flip flops receive common clock pulses which
activate the shift from one stage to the next
• A simplest possible shift register uses only flip flops
and is shown in figure 6-3
Shift Registers

1 0 1 1 0
1 1 0 1 1
Shift Registers

• The output of a given flip flop is connected to the D

input of the flip flop at its right
• Each clock pulse shifts the contents of the register
one bit position to the right
• The serial input determines what goes into the left-
most flip flop during the shift
• The serial output is taken from the output of the
rightmost flip flop
• If it is required to control the shift so that it occurs
only with certain pulses but not with others then we
inhibit the clock from the input of the register to
prevent it from shifting. Shift is then controlled by
connecting the clock through an AND gate with an
input that controls the shift
Serial Transfer
• A digital systems can work either in serial transfer
mode or parallel transfer mode
– Serial transfer
» Information is transferred one bit at a time
» shifts the bits out of the source register into the destination
register
– Parallel transfer:
» All the bits of the register are transferred at the same time
• The serial transfer of information from register A to
register B is done with shift registers as shown in fig
6-4
• The serial output (SO) of register A is connected to
the serial input (SI) of register B
• To prevent the loss of information stored in the
source register, the information in register A is made
to circulate by connecting the serial output to its
serial input
Example: Serial Transfer from Register A to Register B
Example: Serial Transfer from Register A to Register B

• The initial content of register B is shifted out through

its serial output and is lost unless it is transferred to a
third shift register
• The shift control input determines when and how
many times the registers are shifted
• This is done with an AND gate that allows clock pulse
to pass into the CLK terminals only when the shift
control is active
• Suppose the shift register have four bits each. The
control unit that supervises the transfer must be
designed in such a way that it enables the shift
register, through the shift control signal, for a fixed
time of four clock pulses. (as shown in timing diagram
of fig 6-4 b)
Example: Serial Transfer from Register A to Register B

• The shift shift control is synchronised with the clock

and changes value just after the negative edge of the
clock
• The next four clock pulses find the shift control signal
in the active state so that the output of the AND gate
connected to the CLK input produces four pulses T1,
T2, T3 and T4. Each rising edge of pulse causes a shift
in both registers
• The fourth pulse changes the shift control to 0 and the
shift registers are disabled
• Assume the binary contents of A before the shift is
1011 and that of B is 0010
• The serial transfer from A to B occurs in four steps as
shown in table 6-1
Example: Serial Transfer from Register A to Register B
• With the first pulse T1, the rightmost of A is shifted
into leftmost bit of B and is also circulated into the
leftmost position of A
• At the same time all bits of A and B are shifted one
position to the right
• The previous serial output from B in the rightmost
position is lost and its value changes from 0 to 1
• The next three pulses perform identical operations,
shifting the bits of A into B , one at a time
• After the fourth shift,
the shift control goes
to 0 and both registers
A and B have the value
1011
Example: Serial Transfer from Register A to Register B

• The contents of A is transferred into B, while the

contents of A remains unchanged
• This is a serial transfer where the registers have a
single serial input and a single serial output. The
information is transferred one bit at a time while the
registers are shifted in the same direction
 Serial Addition

• Operation in digital computers are usually done in

parallel because this is faster mode of operation
• Serial operations are slower but have the advantage of
requiring less equipment
• We see here a serial adder (the parallel counterpart
was discussed in section 4-4, Binary Adder)
• The two binary numbers to be added serially are
stored in two shift registers
• Bits are added one pair at a time through a single full
adder (FA) circuit, as shown in fig 6-5
• The carry out of the full adder is transferred to a D flip
flop
 Serial Addition

• The output of this flip flop is then used as the carry

input for the next pair of significant bits
• The sum bit from the S output of the full adder could
be transferred into a third shift register
• By shifting the sum into A while the bits of A are
shifted out, it is possible to use one register for
storing both the augend and the sum bits
• The serial input of register B can be used to transfer a
new binary number while the addend bits are shifted
out during the addition
Serial Addition
Serial addition using D flip-flops

1 0
0101 0 0
1010
1
1
1 0
1 1
0011
?001
Serial Adder using JK flip-flops

JQ = x y
KQ = x y = (x + y)
S =xyQ
Circuit Diagram
JQ = x y
KQ = x y = (x + y)
S =xyQ

Ci
Universal Shift Register

– Unidirectional shift register

– Bidirectional shift register
– Universal shift register:
» has both direction shifts & parallel load/out
capabilities
Capability of a universal shift register:

1. A clear control to clear the register to 0.

2. A clock input to synchronize the operations.
3. A shift-right control to enable the shift right operation and the
serial input and output lines associated w/ the shift right.
4. A shift-left control to enable the shift left operation and the
serial input and output lines associated w/ the shift left.
5. A parallel-load control to enable a parallel transfer and the n
parallel input lines associated w/ the parallel transfer.
6. n parallel output lines.
7. A control state that leaves the information in the register
unchanged in the presence of the clock.
Example: 4-bit universal shift register

Parallel outputs
A3 A2 A1 A0

Clear CLK
s1
s2 4-bit universal
shift register
Serial Serial
input for input for
shift-right shift-left

I3 I2 I1 I0
Parallel inputs
Example: 4-bit universal shift register

– Function table

Clear s1 s0 A3+ A2+ A1+ A0+ (Operation)

0 × × 0 0 0 0 Clear
1 0 0 A3 A2 A1 A0 No change
1 0 1 sri A3 A2 A1 Shift right
1 1 0 A2 A1 A0 sli Shift left
1 1 1 I3 I2 I1 I0 Parallel load
Example: 4-bit universal shift register

A2
A1
A0
Counter

– a register that goes through a prescribed sequence of states

– upon the application of input pulses
» Input pulses: May be clock pulses or originate from some
external source
» The sequence of states may follow
• The binary number sequence ( Binary counter) or
• any other sequence of states
Categories of counters

1. Ripple counters
The flip-flop output transition serves as a source for
triggering other flip-flops
 no common clock pulse (not synchronous)
2. Synchronous counters
The CLK inputs of all flip-flops receive a common clock
Example: 4-bit binary ripple counter
A3 A2 A1 A0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
 Example: 4-bit binary ripple counter

Clk

A0 0 1 0 1 0 1 0 1 0

A1 0 0 1 1 0 0 1 1 0

A2 0 0 0 0 1 1 1 1 0

A3 0 0 0 0 0 0 0 0 1
 10

10
BCD Ripple Counter
 Example: 4-bit binary ripple counter

Clk

A0 0 1 0 1 0 1 0 1 0 1 0

A1 0 0 1 1 0 0 1 1 0 0 0

A2 0 0 0 0 1 1 1 1 0 0 0

A3 0 0 0 0 0 0 0 0 1 0 0
The BCD Ripple Counter
Circuit (with JK FF)
Decade Counter
6-4 Synchronous Counters

• Sync counter
– A common clock triggers all flip-flops simultaneously
• Design procedure
– apply the same procedure of synch seq ckts
– Sync counter is simpler than general sync seq ckts
4-bit Binary Counter

C_en A0

C_en A0 A1

C_en A0 A1 A2
4-bit up/down binary counter

up
down

up A0
down A'0

down A'0 A'1 up A0 A1

down A'0 A'1 A'2

BCD counters
4-bit Binary Counter with Paralle Load
 count load'
load c_en
BCD Counter Examples

• Generate any count sequence:

– E.g.: BCD counter  Counter w/ parallel load
6-5 Other Counters

• Counters:
– can be designed to generate any desired sequence of states
• Divide-by-N counter (modulo-N counter)
– a counter that goes through a repeated sequence of N states
– The sequence may follow the binary count or may be any other
arbitrary sequence
Divide By 2 Counter
Consider a single flip-flop with a continuous succession of clock
pulses at a fixed frequency, such as the one shown to the right.
We note three useful facts about the output signals seen at Q
and Q':

They are exactly inverted from each other.

They are perfect square waves (50% duty cycle).
They have a frequency just half that of the clock pulse train.

The duty cycle of any rectangular waveform refers to the

percentage of the full cycle that the signal remains at logic 1. If
the signal spends half its time at logic 1 and the other half at logic
0, we have a waveform with a 50% duty cycle. This describes a
perfect, symmetrical square wave.
 Divide By 3 Counter
• Frequency division by an odd number is also possible. The
circuit is a demonstration of a divide-by-3 counter. No gates
are required to control the sequence if JK flip-flops are used;
feeding the output signals back to the appropriate inputs is
sufficient.
• Of course, it is not possible to get a symmetrical (50% duty
cycle) square wave with this circuit. The A output is at logic 1
for two clock pulses out of three; the B output is at logic 1 for
one clock pulse out of three. Thus, duty cycles of 1/3
(33.333%) and 2/3 (66.667%) are available.
CLK

B
 Divide By 5 Counter
• This rendition of a divide-by-5 counter actually follows the
normal decimal (or binary) count from zero through four. The
primary control feature is the feedback from the C' output to
flip-flop A's J input. This feedback prevents flip-flop A from
switching from logic 0 to logic 1 in an effort to go from a count
of four to a count of five. At the same time, the C output is
applied to flip-flop C's K input to force flip-flop C to reset on
the next clock pulse.
• This particular arrangement is often combined with a single
flip-flop in an IC package. The combination can then be used
either as a normal decimal counter or as a divide-by-10
counter with a true square-wave output.
CLK

A
B
 Divide By 6 Counter
• If it is not necessary to maintain a standard binary counting
sequence, we can often interconnect the flip-flops so as to
eliminate the need for any extra gates, as shown. Note that the
K inputs to both flip-flops A and B are connected to logic 1. As
a result, outputs A and B will remain at logic 1 for only one
clock pulse at a time, and will then reset to logic 0. Output C
will toggle after B goes to logic 1.
• Output C has a 40% duty cycle. Outputs A and B produce two
output pulses for each pulse from C, but not at equal intervals.
The counting sequence is 0, 1, 2, 5, 6, 0, etc.
 Divide By 6 Counter
This counter circuit actually has a flaw as shown:
• If it powers up in state 4 (A = 0, B = 0, C = 1), it will remain in
that state and be unable to change at all. To correct this, we
can disconnect C's K input from output B, and connect it to
output A' instead. Now the first clock pulse will force the circuit
to state 0 (000), from which the count will proceed normally.
This change will not affect the normal counting sequence,
because a logic 1 at the K input cannot prevent the flip-flop
from changing to a logic 1, and would force C back to a logic 0
at the same time it would change anyway.
 6-5 Other Counters

• n flip-flops  2n binary states

• Unused states
– states that are not used in specifying the FSM
» may be treated as don’t-care conditions or
» may be assigned specific next states
• Self-correcting counter
– Ensure that when a ckt enter one of its unused states, it eventually goes
into one of the valid states after one or more clock pulses so it can
resume normal operation.
 Analyze the ckt to determine the next state from an
unused state after it is designed
Example: Counter with unused States

Two unused states: 011 & 111

The simplified flip-flop input eqs:
JA = B, KA = B
JB = C, KB = 1
JC = B, KC = 1
The logic diagram & state diagram of the counter
Ring counter

– A circular shift register with only one flip-flop

being set at any particular time, all others are
cleared
(initial value = 1 0 0 … 0 )

– The single bit is shifted from one flip-flop to the

next to produce the sequence of timing signals
Ring counter
• A 4-bit ring counter

A3 A2 A1 A0
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
1 0 0 0
Ring counters

• Application of counters
– Counters may be used to generate timing signals to control the
sequence of operations in a digital system.
• Approaches for generation of 2n timing signals
1. a shift register w/ 2n flip-flops
2. an n-bit binary counter together w/ an n-to-2n-line decoder
Ring Counter Timing Signals
Johnson counter

• Ring counter vs. Switch-tail ring counter

– Ring counter
» a k-bit ring counter circulates a single bit among the flip-
flops to provide k distinguishable states.
– Switch-tail ring counter
» is a circular shift register w/ the complement output of the
last flip-flop connected to the input of the first flip-flop
» a k-bit switch-tail ring counter will go through a sequence
of 2k distinguishable states. (initial value = 0 0 … 0)
Johnson counter
– A k-bit switch-tail ring counter + 2k decoding gates
– provide outputs for 2k timing signals
» Example: 4-bit Johnson counter

– The decoding follows a regular pattern:

» 2 inputs per decoding gate
Johnson counter example: Switch-tail ring counter
Important to note

• Disadv. of the switch-tail ring counter

– If it finds itself in an unused state, it will persist to circulate in
the invalid states and never find its way to a valid state.
– One correcting procedure: DC = (A + C) B
– ABC = 010 will make DC = 0 instead of DC = B = 1
• Summary:
– Johnson counters can be constructed for any # of timing
sequences:
# of flip-flops = 1/2 (the # of timing signals)
# of decoding gates = # of timing signals
2-input per gate