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Mid Term Assignment

The document outlines an assignment for the VLSI Circuit Design course at American International University-Bangladesh, detailing the course code, semester, and instructor information. It includes a marking rubric for evaluating student responses and specifies a problem related to constructing photomask layers for an inverter using the n-well CMOS process. The assignment is due on April 30, 2025, and is worth a total of 10 marks.

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farhanaislam1601
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59 views2 pages

Mid Term Assignment

The document outlines an assignment for the VLSI Circuit Design course at American International University-Bangladesh, detailing the course code, semester, and instructor information. It includes a marking rubric for evaluating student responses and specifies a problem related to constructing photomask layers for an inverter using the n-well CMOS process. The assignment is due on April 30, 2025, and is worth a total of 10 marks.

Uploaded by

farhanaislam1601
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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American International University- Bangladesh (AIUB)

Faculty of Engineering

Course Name: VLSI Circuit Design Course Code: EEE 4217


Semester: Spring 2024-25 Term: Mid
Total Marks: 10 Submission Date: 30-04-2025
Instructor Name: Mohammad Ashiqur Noor Assignment: 01
Course Outcome Mapping with Questions
Obtained
Item COs POIs K P A Marks
Marks
Q1 CO2 P.a.4.C3 K4 P1, P3, P7 10
Total: 10

Student Information:
Student Name: Student ID:

Section: A & B Department:

Marking Rubrics (to be filled by Faculty):


Excellent Proficient Good Acceptable Unacceptable No Response
[10] [8-9] [6-7] [4-5] [1-3] [0]
Detailed unique No
response Response with no Response shows Partial problem is Unable to clarify Response/(Copi
Secured
Problem # explaining the apparent errors understanding of solved; response the understanding ed/identical
Marks
concept properly and the answer is the problem, but indicates part of of the problem submissions
and answer is correct, but the final answer the problem was and method of the will be graded
correct with all explanation is not may not be not understood problem solving as 0 for all
works clearly adequate/unique. correct clearly. was not correct parties
shown. concerned)
1
Total marks
Comments
(10)

1. Apply the concept of the n-well CMOS process to construct photomask layers for fabricating an inverter
whose architecture is shown below. Show the relevant cross sections. [10]

ID (middle 5 bits) Figure No. Pull-down device Pull-up device


A < ID <= B Figure 1 NMOS with gate connected to input NMOS with gate connected to Vdd
signal
B < ID <= C Figure 2 NMOS with gate connected to input NMOS with gate and source
signal shorted
C < ID <= D Figure 3 NMOS with gate connected to input PMOS with gate and drain shorted
signal
D < ID <= E Figure 4 NMOS with gate connected to input PMOS with gate connected to
signal ground
ID > E Figure 5 NMOS with gate and drain shorted PMOS with gate connected to input
signal
Figure 1 Figure 2

Figure 3 Figure 4

Figure 5

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