Data Sheet

AD5593R
8-Channel, 12-Bit, Configurable ADC/DAC with On-Chip Reference, I2C Interface

GENERAL DESCRIPTION
FEATURES The AD5593R has eight input/output (I/O) pins, which can be inde-
► 8-channel, configurable ADC/DAC/GPIO pendently configured as digital-to-analog converter (DAC) outputs,
analog-to-digital converter (ADC) inputs, digital outputs, or digital
►Configurable as any combination of
inputs. When an I/O pin is configured as an analog output, it is
► 8 12-bit DAC channels
driven by a 12-bit DAC. The output range of the DAC is 0 V to VREF
► 8 12-bit ADC channels or 0 V to 2 × VREF. When an I/O pin is configured as an analog
► 8 general-purpose I/O pins input, it is connected to a 12-bit ADC via an analog multiplexer.
► Integrated temperature sensor The input range of the ADC is 0 V to VREF or 0 V to 2 × VREF.
► 16-lead TSSOP and LFCSP and 16-ball WLCSP packages The I/O pins can also be configured to be general-purpose, digital
input or output (GPIO) pins. The state of the GPIO pins can be set
► I2C interface
or read back by accessing the GPIO write data register and GPIO
APPLICATIONS read configuration registers, respectively, via an I2C write or read
operation.
► Control and monitoring
The AD5593R has an integrated 2.5 V, 20 ppm/°C reference that
► General-purpose analog and digital I/O
is turned off by default and an integrated temperature indicator that
gives an indication of the die temperature. The temperature value is
read back as part of an ADC read sequence.
The AD5593R is available in 16-lead TSSOP and LFCSP, as well
as a 16-ball WLCSP, and operates over a temperature range of
−40°C to +105°C.
Table 1. Related Products
Product Description
AD5592R AD5593R equivalent with SPI interface
AD5592R-1 AD5593R equivalent with SPI interface and VLOGIC pin
FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Rev. H
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Data Sheet AD5593R
TABLE OF CONTENTS

Features................................................................ 1 DAC Write Operation........................................24

Applications........................................................... 1 DAC Readback.................................................24
General Description...............................................1 ADC Operation ................................................ 25
Functional Block Diagram......................................1 GPIO Operation................................................26
Specifications........................................................ 3 Three-State Pins.............................................. 26
Timing Characteristics........................................6 85 kΩ Pull-Down Pins...................................... 26
Absolute Maximum Ratings...................................7 Power-Down/Reference Control.......................26
Thermal Resistance........................................... 7 Reset Function................................................. 26
Electrostatic Discharge (ESD) Ratings...............7 Applications Information...................................... 27
ESD Caution.......................................................7 Microprocessor Interfacing............................... 27
Pin Configuration and Function Descriptions........ 8 AD5593R to ADSP-BF537 Interface................ 27
Typical Performance Characteristics..................... 9 Layout Guidelines.............................................27
Terminology......................................................... 14 Register Map....................................................... 28
Theory of Operation.............................................17 Register Summary: AD5593R Pointer Byte
DAC Section.....................................................17 Map ............................................................... 28
ADC Section.....................................................18 Register Summary (Bit-Wise): AD5593R
GPIO Section................................................... 19 Pointer Byte Map ...........................................28
Internal Reference............................................19 Register Summary: AD5593R Control
Reset Function................................................. 19 Register Map.................................................. 28
Temperature Indicator...................................... 19 Register Details: AD5593R Pointer Byte Map..29
Serial Interface.................................................... 20 Register Details: AD5593R Control Register
Write Operation................................................ 20 Map................................................................ 31
Read Operation................................................ 21 Register Details: AD5593R ADC and DAC
Pointer Byte......................................................22 Readback ...................................................... 44
Control Registers..............................................22 Outline Dimensions............................................. 46
General-Purpose Control Register................... 22 Ordering Guide.................................................47
Configuring the AD5593R................................ 22 Evaluation Boards............................................ 47

REVISION HISTORY

8/2023—Rev. G to Rev. H
Changes to Table 3.......................................................................................................................................... 6
Change to Figure 36...................................................................................................................................... 20
Changes to Figure 37 and Figure 38............................................................................................................. 21
Changes to Figure 39.................................................................................................................................... 22
Changes to Figure 41.................................................................................................................................... 24
Changes to Figure 42.................................................................................................................................... 25
Change to Reset Function Section................................................................................................................ 26
Changes to Table 8........................................................................................................................................ 28
Changes to Table 9........................................................................................................................................ 28

1/2023—Rev. F to Rev. G
Changes to Figure 42.................................................................................................................................... 25

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Data Sheet AD5593R
SPECIFICATIONS

VDD = 2.7 V to 5.5 V, VLOGIC = 2.7 V to 5.5 V, VREF = 2.5 V (internal), Temperature Range TA = TMIN to TMAX, unless otherwise noted. Typical
specs are verified by characterization, not production tested.

Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
TEMPERATURE RANGE (TA)
Specified Performance −40 +105 °C
ADC PERFORMANCE fIN = 10 kHz sine wave
Resolution 12 Bits
Input Range1 0 VREF V ADC range select bit = 0
0 2 × VREF V ADC range select bit = 1
Integral Nonlinearity (INL) −2 +2 LSB
Differential Nonlinearity (DNL) −1 +1 LSB
Offset Error ±5 mV
Gain Error 0.3 % FSR
Track Time (tTRACK)2 500 ns
Conversion Time (tCONV)2 2 µs
Signal to Noise Ratio (SNR)3 69 dB VDD = 2.7 V, input range = 0 V to VREF
67 dB VDD = 5.5 V, input range = 0 V to VREF
61 dB VDD = 5.5 V, input range = 0 V to 2 × VREF
Signal-to-Noise + Distortion (SINAD) Ratio 69 dB VDD = 2.7 V, input range = 0 V to VREF
67 dB VDD = 3.3 V, input range = 0 V to VREF
60 dB VDD = 5.5 V, input range = 0 V to 2 × VREF
Total Harmonic Distortion (THD) −91 dB VDD = 2.7 V, input range = 0 V to VREF
−89 dB VDD = 3.3 V, input range = 0 V to VREF
−72 dB VDD = 5.5 V, input range = 0 V to 2 × VREF
Spurious Free Dynamic Range (SFDR) 91 dB VDD = 2.7 V, input range = 0 V to VREF
91 dB VDD = 3.3 V, input range = 0 V to VREF
72 dB VDD = 5.5 V, input range = 0 V to 2 × VREF
Aperture Delay2 15 ns VDD = 3 V
12 ns VDD = 5 V
Aperture Jitter2 50 ps
Channel-to-Channel Isolation −95 dB fIN = 5 kHz
Full Power Bandwidth 8.2 MHz At 3 dB
1.6 MHz At 0.1 dB
DAC PERFORMANCE4
Resolution 12 Bits
Output Range 0 VREF V DAC range select bit = 0
0 2 × VREF V DAC range select bit = 1
INL −1 +1 LSB
DNL −1 +1 LSB
Offset Error −3 +3 mV
Offset Error Drift2 8 µV/°C
Gain Error ±0.2 % FSR Output range = 0 V to VREF
±0.1 % FSR Output range = 0 V to 2 × VREF
Zero Code Error 0.65 2 mV
Total Unadjusted Error (TUE) ±0.03 ±0.25 % FSR Output range = 0 V to VREF
±0.015 ±0.1 % FSR Output range = 0 V to 2 × VREF
Capacitive Load Stability 2 nF RLOAD = ∞
10 nF RLOAD = 1 kΩ
Resistive Load 1 kΩ

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Data Sheet AD5593R
SPECIFICATIONS

Table 2. (Continued)
Parameter Min Typ Max Unit Test Conditions/Comments
Short-Circuit Current 25 mA
DC Crosstalk2 −4 +4 µV Single channel, full-scale output change
DC Output Impedance 0.2 Ω
DC Power Supply Rejection Ratio (PSRR)2 0.15 mV/V DAC code = midscale, VDD = 3 V ± 10% or 5 V ± 10%
Load Impedance at Rails5 25 Ω
Load Regulation 200 µV/mA VDD = 5 V ± 10%, DAC code = midscale, −10 mA ≤ IOUT ≤ +10 mA
200 µV/mA VDD = 3 V ± 10%, DAC code = midscale, −10 mA ≤ IOUT ≤ +10 mA
Power-Up Time 7 µs Exiting power-down mode, VDD = 5 V
DAC AC SPECIFICATIONS
Slew Rate 1.25 V/µs
Settling Time 6 µs
DAC Glitch Impulse 2 nV-sec
DAC to DAC Crosstalk 1 nV-sec
Digital Crosstalk 0.1 nV-sec
Analog Crosstalk 1 nV-sec
Digital Feedthrough 0.1 nV-sec
Multiplying Bandwidth 240 kHz DAC code = full scale, output range = 0 V to 2 × VREF
Output Voltage Noise Spectral Density 200 nV/√Hz DAC code = midscale, output range = 0 V to 2 × VREF, measured
at 10 kHz
SNR 81 dB
SFDR 77 dB
SINAD 74 dB
Total Harmonic Distortion −76 dB
REFERENCE INPUT
VREF Input Voltage 1 VDD V
DC Leakage Current −1 +1 µA No I/Ox pins configured as DACs
VREF Input Impedance 12 kΩ DAC output range = 0 V to 2 × VREF
24 kΩ DAC output range = 0 V to VREF
REFERENCE OUTPUT
VREF Output Voltage 2.495 2.5 2.505 V
VREF Temperature Coefficient 20 ppm/°C
Capacitive Load Stability 5 μF RLOAD = 2 kΩ
Output Impedance 0.15 Ω VDD = 2.7 V
0.7 Ω VDD = 5 V
Output Voltage Noise 10 µV p-p 0.1 Hz to 10 Hz
Output Voltage Noise Density 240 nV/√Hz At ambient, f = 1 kHz, CL = 10 nF
Line Regulation 20 µV/V At ambient, sweeping VDD from 2.7 V to 5.5 V
10 µV/V At ambient, sweeping VDD from 2.7 V to 3.3 V
Load Regulation
Sourcing 210 µV/mA At ambient, −5 mA ≤ load current ≤ +5 mA
Sinking 120 µV/mA At ambient, −5 mA ≤ load current ≤ +5 mA
Output Current Load Capability ±5 mA VDD ≥ 3 V
GPIO OUTPUT
ISOURCE and ISINK 1.6 mA
Output Voltage
High, VOH VDD − 0.2 V ISOURCE = 1 mA
Low, VOL 0.4 V ISINK = 1 mA
GPIO INPUT
Input Voltage

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Data Sheet AD5593R
SPECIFICATIONS

Table 2. (Continued)
Parameter Min Typ Max Unit Test Conditions/Comments
High, VIH VDD × 0.7 V
Low, VIL VDD × 0.3 V
Input Capacitance 20 pF
Hysteresis 0.2 V
Input Current ±1 µA
LOGIC INPUTS
Input Voltage
High, VINH 0.7 × VLOGIC V
Low, VINL 0.3 × VLOGIC V
Input Current, IIN −1 +0.01 +1 µA
Input Capacitance, CIN 10 pF
LOGIC OUTPUT (SDA)
Output High Voltage, VOH VLOGIC − 0.2 V ISOURCE = 200 µA; VLOGIC = 2.7 V to 5.5 V
Output Low Voltage, VOL 0.4 V ISINK = 200 µA
Floating-State Output Capacitance 10 pF
TEMPERATURE SENSOR2
Resolution 12 Bits
Operating Range −40 +105 °C
Accuracy ±3 °C
Track Time 5 µs ADC buffer enabled
20 µs ADC buffer disabled
POWER REQUIREMENTS
VDD 2.7 5.5 V
IDD Digital inputs = 0 V or VLOGIC
Power-Down Mode 3.5 µA
Normal Mode
VDD = 5 V 1.6 mA I/O0 to I/O7 are DACs, internal reference, gain = 2
1 mA I/O0 to I/O7 are DACs, external reference, gain = 2
2.4 mA I/O0 to I/O7 are DACs and sampled by the ADC, internal
reference, gain = 2
1.1 mA I/O0 to I/O7 are DACs and sampled by the ADC, external
reference, gain = 2
1 mA I/O0 to I/O7 are ADCs, internal reference, gain = 2
0.75 mA I/O0 to I/O7 are ADCs, external reference, gain = 2
0.5 mA I/O0 to I/O7 are general-purpose outputs
0.5 mA I/O0 to I/O7 are general-purpose inputs
VDD = 3 V 1.1 mA I/O0 to I/O7 are DACs, internal reference, gain = 1
1 mA I/O0 to I/O7 are DACs, external reference, gain = 1
1.1 mA I/O0 to I/O7 are DACs and sampled by the ADC, internal
reference, gain = 1
0.78 mA I/O0 to I/O7 are DACs and sampled by the ADC, external
reference, gain = 1
0.75 mA I/O0 to I/O7 are ADCs, internal reference, gain = 1
0.5 mA I/O0 to I/O7 are ADCs, external reference, gain = 1
0.45 mA I/O0 to I/O7 are general-purpose outputs
0.45 mA I/O0 to I/O7 are general-purpose inputs
VLOGIC 1.8 VDD V
ILOGIC 3.5 μA

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Data Sheet AD5593R
SPECIFICATIONS

1 When using the internal ADC buffer, there is a dead band of 0 V to 5 mV.
2 Guaranteed by design and characterization; not production tested.
3 All specifications expressed in decibels are referred to full-scale input, FSR, and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4 DC specifications tested with the outputs unloaded, unless otherwise noted. Linearity calculated using a reduced code range of 8 to 4085. An upper dead band of 10 mV
exists when VREF = VDD.
5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For
example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 26 and Figure 27).

TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD = 2.7 V to 5.5 V, 1.8
V ≤ VLOGIC ≤ VDD; 2.5 V ≤ VREF ≤ VDD; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.
Parameter1 Min Typ Max Unit Conditions/Comments
t1 2.5 µs SCL cycle time
t2 0.6 µs tHIGH, SCL high time
t3 1.3 µs tLOW, SCL low time
t4 0.6 µs tHD,STA, start/repeated start condition hold time
t5 100 ns tSU,DAT, data setup time
t 62 0.9 µs tHD,DAT, data hold time
t7 0.6 µs tSU,STA, setup time for repeated start
t8 0.6 µs tSU,STO, stop condition setup time
t9 1.3 µs tBUF, bus free time between a stop and a start condition
t10 300 ns tR, rise time of SCL and SDA when receiving
0 ns tR, rise time of SCL and SDA when receiving (CMOS compatible)
t11 250 ns tF, fall time of SDA when transmitting
0 ns tF, fall time of SDA when receiving (CMOS compatible)
300 ns tF, fall time of SCL and SDA when receiving
20 + 0.1 × CB3 ns tF, fall time of SCL and SDA when transmitting
tRESETL_PW 250 ns RESET low pulse width
CB3 400 pF Capacitive load for each bus line

1 Guaranteed by design and characterization; not production tested.

2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling edge
of SCL.
3 CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VLOGIC and 0.7 VLOGIC.

Timing Diagram

Figure 2. 2-Wire Serial Interface Timing Diagram

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Data Sheet AD5593R
ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to 100 Do not use θJA, θJC, and θJB thermal resistances to perform direct
mA do not cause SCR latch-up. calculation/measurement of the die temperature because doing so
Table 4.
results in incorrect values. The thermal resistances assume 100%
of the power that is dissipated along the specified path between the
Parameter Rating
measurement points. The thermal resistances are directly depend-
VDD to GND −0.3 V to +7 V ent on the PCB design and environment.
VLOGIC to GND −0.3 V to +7 V
I/Ox to GND −0.3 V to VDD + 0.3 V
If direct measurement of the package is required, the ΨJT and ΨJB
values must be used because they more accurately reflect the true
Digital Inputs to GND −0.3 V to VLOGIC + 0.3 V
thermal dissipation paths.
Digital Outputs to GND −0.3 V to VLOGIC +0.3 V
VREF to GND −0.3 V to VDD +0.3 V θJC must only be used where an external heat sink is attached
Operating Temperature Range −40°C to +105°C directly to the package.
Storage Temperature Range −65°C to +150°C System level thermal simulation is highly recommended.
Junction Temperature (TJ max) +150°C
Lead Temperature JEDEC industry-standard For more details about the thermal resistances, refer to JE-
Soldering J-STD-020 DEC51-12: Guidelines for Reporting and Using Electronic Package
Thermal Information.
Stresses at or above those listed under Absolute Maximum Ratings
Table 5. Thermal Resistance
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other Package Type θJA θJB θJC-TOP ΨJT ΨJB Unit
conditions above those indicated in the operational section of this CP-16-32 92.4 39.6 48.2 0.9 37.4 °C/W
specification is not implied. Operation beyond the maximum operat- RU-16 127 60.2 42.2 2.6 59.1 °C/W
ing conditions for extended periods may affect product reliability. CB-16-3 103.2 64 0 0 78 °C/W

THERMAL RESISTANCE ELECTROSTATIC DISCHARGE (ESD) RATINGS

Thermal performance is directly linked to printed circuit board The following ESD information is provided for handling of ESD-sen-
(PCB) design and operating environment. Careful attention to PCB sitive devices in an ESD protected area only.
thermal design is required.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Thermal characteristics are specified for the worst-case conditions,
that is, a device soldered in a circuit board for surface-mount pack- Field induced charged device model (FICDM) and charged device
ages. Thermal resistance values specified in Table 5 are simulated model (CDM) per ANSI/ESDA/JEDEC JS-002.
based on JEDEC specifications using a 2S2P thermal test board
(see JEDEC JESD51), except for θJC-TOP, which uses a JEDEC 1S ESD Ratings for AD5593R
test board. Table 6. AD5593R, 16-Ball WLCSP, 16-Ball LFCSP, and 16-Lead TSSOP
θJA is the junction to ambient thermal resistance, measured in a ESD Model Withstand Voltage (V) Class
JEDEC natural convection environment. HBM 500 1B
θJC is the junction to case thermal resistance, measured at the cen- FICDM 1250 C3
ter of the package top surface, with an infinite heat sink attached to
the package surface. ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devi-
θJB is the junction to board thermal resistance, measured at a point
ces and circuit boards can discharge without detection. Although
on the board 1mm from the package edge, along the package
this product features patented or proprietary protection circuitry,
centerline, measured in a JEDEC θJB environment.
damage may occur on devices subjected to high energy ESD.
ΨJB is the junction to board thermal characterization parameter, Therefore, proper ESD precautions should be taken to avoid
measured in a JEDEC natural convection environment. performance degradation or loss of functionality.

ΨJT is the junction to package top thermal characterization parame-

ter, measured in a JEDEC natural convection environment.

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Data Sheet AD5593R
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. 16-Lead TSSOP Pin Configuration Figure 5. 16-Ball WLCSP Pin Configuration

Figure 4. 16-Lead LFCSP Pin Configuration

Table 7. Pin Function Descriptions
Pin No.
TSSOP LFCSP WLCSP Mnemonic Description
1 15 A3 RESET Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5593R is reset to its
default configuration.
2 16 A4 A0 Address Input. Sets the LSB of the 7-bit slave address.
3 1 B4 VDD Power Supply Input. The AD5593R can operate from 2.7 V to 5.5 V. Decouple the supply with a 0.1 µF capacitor to GND.
4 to 7, 2 to 5, B3, C4, C3, I/O0 to I/O7 Input/Output 0 Through Input/Output 7. These pins can be independently configured as DACs, ADCs, or general-purpose
10 to 13 8 to 11 C2, D1, D4, digital inputs or outputs. The function of each pin is determined by programming the appropriate bits in the configuration
C1, B2 registers.
8 6 D3 VREF Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on the VREF pin.
A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance from the
AD5593R. When the internal reference is disabled, an external reference must be applied to this pin. The voltage range for
the external reference is 1 V to VDD.
9 7 D2 VLOGIC Interface Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V.
14 12 B1 GND Ground Reference Point for All Circuitry.
15 13 A1 SDA Serial Data Input. This pin is used with the SCL line to clock data in to or out of the input shift register. SDA is a
bidirectional, open-drain line that must be pulled to the VLOGIC supply with an external pull-up resistor.
16 14 A2 SCL Serial Clock Line. This pin is used with the SDA line to clock data in to or out of the 16-bit input register.

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Data Sheet AD5593R
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 6. ADC INL; VDD = 5.5 V Figure 9. ADC DNL; VDD = 2.7 V

Figure 7. ADC DNL; VDD = 5.5 V Figure 10. Histogram of ADC Codes; VDD = 2.7 V

Figure 8. ADC INL; VDD = 2.7 V Figure 11. Histogram of Codes; VDD = 5.5 V

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Data Sheet AD5593R
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 12. ADC Bandwidth Figure 15. DAC Adjacent Code Glitch

Figure 13. DAC INL Figure 16. DAC Digital to Analog Glitch (Rising)

Figure 14. DAC DNL Figure 17. DAC Digital to Analog Glitch (Falling)

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Data Sheet AD5593R
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 18. DAC Settling Time (100 Code Change, Rising Edge) Figure 21. DAC Settling Time, Output Range = 0 V to 2 × VREF

Figure 19. DAC Settling Time (100 Code Change, Falling Edge) Figure 22. DAC Settling Time vs. Capacitive Load

Figure 20. DAC Settling Time, Output Range = 0 V to VREF Figure 23. DAC 1/f Noise with External Reference

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Data Sheet AD5593R
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 24. DAC 1/f Noise with Internal Reference Figure 27. DAC Output Sink and Source Capability, Output Range = 0 V to 2 ×
VREF

Figure 25. DAC Output Noise Spectral Density

Figure 28. Internal Reference 1/f Noise

Figure 26. DAC Output Sink and Source Capability, Output Range = 0 V to
VREF Figure 29. Reference Noise Spectral Density

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Data Sheet AD5593R
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 30. Reference Line Regulation

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Data Sheet AD5593R
TERMINOLOGY

ADC Integral Nonlinearity (INL) Total Harmonic Distortion (THD)

For the ADC, INL is the maximum deviation from a straight line THD is the ratio of the rms sum of harmonics to the fundamental.
passing through the endpoints of the ADC transfer function. The For the AD5593R, it is defined as
end points of the transfer function are zero scale, a point that is
V22 + V32 + V42 + V52 + V62
1 LSB below the first code transition, and full scale, a point that is 1 THD dB = 20 × log V1
(1)
LSB above the last code transition.
where V1 is the rms amplitude of the fundamental and V2, V3, V4,
ADC Differential Nonlinearity (DNL)
V5, and V6 are the rms amplitudes of the second through the sixth
For the ADC, DNL is the difference between the measured and the harmonics.
ideal 1 LSB change between any two adjacent codes in the ADC.
Peak Harmonic or Spurious Noise
Offset Error
Peak harmonic or spurious noise is defined as the ratio of the rms
Offset error is the deviation of the first code transition (00 … 000) to value of the next largest component in the ADC output spectrum
(00 … 001) from the ideal, that is, AGND + 1 LSB. (up to fS/2 and excluding dc) to the rms value of the fundamental.
Normally, the value of this specification is determined by the largest
Gain Error harmonic in the spectrum, but for ADCs where the harmonics are
Gain error is the deviation of the last code transition (111 … 110) to buried in the noise floor, it is a noise peak.
(111 … 111) from the ideal (that is, VREF − 1 LSB) after the offset DAC Relative Accuracy or Integral Nonlinearity
error has been adjusted out. (INL)
Channel-to-Channel Isolation For the DAC, relative accuracy or integral nonlinearity is a meas-
Channel-to-channel isolation is a measure of the level of crosstalk urement of the maximum deviation, in LSBs, from a straight line
between channels. It is measured by applying a full-scale 5 kHz passing through the endpoints of the DAC transfer function. A
sine wave signal to all non-selected ADC input channels and deter- typical INL vs. code plot is shown in Figure 13.
mining how much that signal is attenuated in the selected channel. DAC Differential Nonlinearity (DNL)
This specification is the worst case across all ADC channels for the
AD5593R. For the DAC, differential nonlinearity is the difference between
the measured change and the ideal 1 LSB change between any
Track-and-Hold Acquisition Time two adjacent codes. A specified differential nonlinearity of ±1 LSB
The track-and-hold amplifier goes into track mode when the ADC maximum ensures monotonicity. This DAC is guaranteed monotonic
sequence register has been written to. The track and hold amplifier by design. A typical DNL vs. code plot can be seen in Figure 14.
goes into hold mode when the conversion starts (see Figure 39). Zero Code Error
Track-and-hold acquisition time is the minimum time required for
the track-and-hold amplifier to remain in track mode for its output to Zero code error is a measurement of the output error when zero
reach and settle to within ±1 LSB of the applied input signal, given a code (0x000) is loaded to the DAC register. Ideally, the output is 0
step change to the input signal. V. The zero code error is always positive in the AD5593R because
the output of the DAC cannot go below 0 V due to a combination
Signal-to-Noise Distortion Ratio SINAD of the offset errors in the DAC and the output amplifier. Zero code
SINAD is the measured ratio of signal to (noise + distortion) at the error is expressed in mV.
output of the analog-to-digital converter. The signal is the rms am- Gain Error
plitude of the fundamental. Noise is the sum of all non-fundamental
signals up to half the sampling frequency (fS/2), excluding dc. The Gain error is a measure of the span error of the DAC. It is the
ratio is dependent on the number of quantization levels in the deviation in slope of the DAC transfer characteristic from the ideal
digitization process; the more levels, the smaller the quantization expressed as % of FSR.
noise. The theoretical SINAD for an ideal N-bit converter with a sine
wave input is given by Offset Error

Signal-to-(Noise + Distortion) (dB) = 6.02N + 1.76 Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the transfer
Thus, for a 12-bit converter, this is 74 dB. function. Offset error can be negative or positive.

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Data Sheet AD5593R
TERMINOLOGY

Offset Error Drift Digital Crosstalk

Offset error drift is a measurement of the change in offset error with Digital crosstalk is the glitch impulse transferred to the output of one
a change in temperature. It is expressed in µV/°C. DAC at midscale in response to a full-scale code change (all 0s
to all 1s and vice versa) in the input register of another DAC. It is
DAC DC Power Supply Rejection Ratio (PSRR) measured in standalone mode and is expressed in nV-sec.
For the DAC, PSRR indicates how the output of the DAC is affected Analog Crosstalk
by changes in the supply voltage. PSRR is the ratio of the change
in VOUT to a change in VDD for full-scale output of the DAC. It is Analog crosstalk is the glitch impulse transferred to the output of
measured in mV/V. VREF is held at 2 V, and VDD is varied by ±10%. one DAC due to a change in the output of another DAC. It is first
measured by loading one of the input registers with a full-scale
Output Voltage Settling Time code change (all 0s to all 1s and vice versa). Then it is measured
Output voltage settling time is the amount of time it takes for the by executing software LDAC and monitoring the output of the DAC
output of a DAC to settle to a specified level for a ¼ to ¾ full-scale whose digital code was not changed. The area of the glitch is
input change and is measured from the rising edge of SDA that expressed in nV-sec.
generates the stop condition. DAC-to-DAC Crosstalk
Digital-to-Analog Glitch Impulse DAC-to-DAC crosstalk is the glitch impulse transferred to the output
Digital-to-analog glitch impulse is the impulse injected into the of one DAC due to a digital code change and subsequent analog
analog output when the input code in the DAC register changes output change of another DAC. It is measured by loading the attack
state. It is normally specified as the area of the glitch in nV-sec, and channel with a full-scale code change (all 0s to all 1s and vice
is measured when the digital input code is changed by 1 LSB at the versa), using the write to and update commands while monitoring
major carry transition (0x7FF to 0x800) (see Figure 16 and Figure the output of the victim channel that is at midscale. The energy of
17). the glitch is expressed in nV-sec.
Digital Feedthrough Multiplying Bandwidth
Digital feedthrough is a measure of the impulse injected into the The amplifiers within the DAC have a finite bandwidth. The multiply-
analog output of the DAC from the digital inputs of the DAC, but ing bandwidth is a measure of this finite bandwidth. A sine wave on
is measured when the DAC output is not updated. It is specified in the reference (with full-scale code loaded to the DAC) appears on
nV-sec, and measured with a full-scale code change on the data the output. The multiplying bandwidth is the frequency at which the
bus, that is, from all 0s to all 1s and vice versa. output amplitude falls to 3 dB below the input.
Reference Feedthrough DAC Total Harmonic Distortion (THD)
Reference feedthrough is the ratio of the amplitude of the signal at For the DAC, THD is the difference between an ideal sine wave
the DAC output to the reference input when the DAC output is not and its attenuated version using the DAC. The sine wave is used as
being updated. It is expressed in dB. the reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Noise Spectral Density (NSD)
Voltage Reference Temperature Coefficient
NSD is a measurement of the internally generated random noise. (TC)
Random noise is characterized as a spectral density (nV/√Hz). It is
measured by loading the DAC to midscale and measuring noise at Voltage reference TC is a measure of the change in the reference
the output. It is measured in nV/√Hz. A plot of noise spectral density output voltage with a change in temperature. The voltage reference
is shown in Figure 25. TC is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given temperature
DC Crosstalk range expressed in ppm/°C, as follows:
DC crosstalk is the dc change in the output level of one DAC in VREF(MAX) − VREF(MIN)
response to a change in the output of another DAC. It is measured TC = VREF(NOM) × Temp Range × 106 (2)
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale. It is where:
expressed in μV. VREF(MAX) is the maximum reference output measured over the total
temperature range.
DC crosstalk due to load current change is a measure of the impact VREF(MIN) is the minimum reference output measured over the total
that a change in load current on one DAC has to another DAC kept temperature range.
at midscale. It is expressed in μV/mA.
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Data Sheet AD5593R
TERMINOLOGY

VREF(NOM) is the nominal reference output voltage, 2.5 V. Temp Range is the specified temperature range of −40°C to
+105°C.

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Data Sheet AD5593R
THEORY OF OPERATION

The AD5593R is an 8-channel, configurable analog and digital

I/O port. The AD5593R has eight pins that can be independently
configured as a 12-bit DAC output channel, a 12-bit ADC input
channel, a digital input pin, or a digital output pin.
The function of each pin is determined by programming the ADC,
DAC, or GPIO configuration registers as appropriate.
DAC SECTION
The AD5593R contains eight 12-bit DACs. Each DAC consists of a
string of resistors followed by an output buffer amplifier. Figure 31
shows a block diagram of the DAC architecture.

Figure 32. Resistor String

DAC Output Buffer

The output buffer is designed as an input/output rail-to-rail buffer.
The output buffer can drive 2 nF capacitance with a 1 kΩ resistor
Figure 31. DAC Channel Architecture Block Diagram in parallel. The slew rate is 1.25 V/µs with a ¼ to ¾ scale settling
time of 6 µs. By default, the DAC outputs update directly after data
The DAC channels share a single DAC range bit (in the General- has been written to the input register. The LDAC register delays the
Purpose Control Register section, see Bit 4 in Table 19) that sets updates until additional channels have been written to if required.
the output range to 0 V to VREF or 0 V to 2 × VREF. Because the See the LDAC Mode Operation section for more information.
range bit is shared by all channels, it is not possible to set different
output ranges on a per channel basis. The input coding to the DAC
DAC Output Range
is straight binary. Therefore, the ideal output voltage is given by
The DAC output voltage range can be configured to 0 V to VREF
D
VOUT = G × VREF × (3) (gain = 1) or 0 V to 2 × VREF (gain = 2) using DAC range bit of the
2N
general-purpose control register, as shown in Figure 33 and Figure
where: 34, respectively. When VREF = VDD, the 0 V to 2 × VREF range does
G = 1 for an output range of 0 V to VREF or G = 2 for an output not allow the DAC to swing the output beyond VDD.
range of 0 V to 2 × VREF.
VREF is the voltage on the VREF pin.
D is the decimal equivalent of the binary code (0 to 4095) that is
loaded to the DAC register.
N = 12.

Resistor String
The simplified segmented resistor string DAC structure is shown
in Figure 32. The code loaded to the DAC register determines the
switch on the string that is connected to the output buffer.
Because each resistance in the string has the same value, R, the
string DAC is guaranteed monotonic.

Figure 33. Output Voltage Range of the DAC with Gain = 1 (Unloaded
Condition)

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Data Sheet AD5593R
THEORY OF OPERATION

Calculating ADC Input Current

The current flowing into the I/Ox pins configured as ADC inputs
varies with sampling rate (fS), the voltage difference between
successive channels (VDIFF), and whether buffered or unbuffered
mode is used. Figure 35 shows a simplified version of the ADC
input structure. When a new channel is selected for conversion,
5.8 pF must be charged to or discharged from the voltage that on
the previously selected channel. The time required for the charge
or discharge depends on the voltage difference between the two
channels. This dependence affects the input impedance of the
multiplexer and, therefore, the input current flowing into the I/Ox
pins.
In buffered mode, Switch S1 is open and Switch S2 is closed. In
Figure 34. Output Voltage Range of the DAC with Gain = 2 (Unloaded buffered mode, the U1 buffer directly drives the 23.1 pF capacitor
Condition) and the charging time of the capacitors is negligible. In unbuffered
mode, Switch S1 is closed and Switch S2 is closed. In unbuffered
When VREF = VDD for gain = 1 or VREF = 0.5 × VDD for gain = 2, mode, the 23.1 pF capacitor must be charged from the I/Ox pins;
there is an upper dead band of 10 mV at the DAC channel output this charging contributes to the input current. For applications
in unloaded conditions. Additionally, there is a lower dead band of where the ADC input current is too high, an external input buffer
~4.88 mV at the DAC channel output in unloaded conditions. When may be required. The choice of buffer is a function of the particular
drawing a load current at either rail, the output voltage headroom application.
with respect to that rail is limited by the 25 Ω typical channel
Calculate the input current for buffered mode as follows:
resistance of the DAC channel. For example, when sinking 1 mA,
the minimum output voltage = 25 Ω × 1 mA = 25 mV. fS × C × VDIFF + 1 nA
ADC SECTION where:
fS is the ADC sample rate in Hz.
The ADC section is a fast, 12-bit, single-supply ADC with a conver- C is the sampling capacitance in farads.
sion time of 2 µs. The ADC is preceded by a multiplexer that VDIFF is the voltage change between successive channels.
switches selected I/O pins to the ADC. A sequencer is included
to switch the multiplexer to the next selected channel automatical- Calculate the input current for buffered mode as follows:
ly. Channels are selected for conversion by writing to the ADC
fS × C × VDIFF
sequence register. When the write to the ADC sequence register
has completed, the first channel in the conversion sequence is where 1 nA is the dc leakage current associated with unbuffered
put into track mode. Each channel can track the input signal for a mode.
minimum of 500 ns. The conversion is initiated on the rising edge
of the clock for the acknowledge (ACK) that occurs after the slave The input current for the ADC in buffered mode, where I/O0 = 0.5 V,
address (see Figure 39). I/O1 = 2 V, and fS = 10 kHz, is as follows:

Each conversion takes 2 µs. The ADC has a range bit (ADC range (10,000 × 5.8 × 10−12 × 1.5) + 1 nA = 88 nA
select in the general-purpose control register, see Bit 5 in Table 19) Under the same conditions, the ADC input current in unbuffered
that sets the input range as 0 V to VREF or 0 V to 2 × VREF. All input mode is as follows:
channels share the same range. The output coding of the ADC is
straight binary. It is possible to set each I/Ox pin as both a DAC and (10,000 × 28.9 × 10−12 × 1.5) = 433.5 nA
an ADC. In this case, the primary function is that of the DAC. If the
pin is selected for inclusion in an ADC conversion sequence, the
voltage on the pin is converted and made available via the serial
interface. This allows the DAC voltage to be monitored.

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Data Sheet AD5593R
THEORY OF OPERATION

Figure 35. ADC Input Structure

GPIO SECTION AD5593R during this time. The AD5593R has a software reset that
performs the same function as the RESET pin. The reset function is
Each of the eight I/Ox pins can be configured as a general-purpose activated by writing 0x0F to the pointer byte and 0x0D and 0xAC to
digital input by programming the GPIO read configuration register the most significant and least significant bytes of the software reset
or output pin by programming the GPIO write configuration register. register, respectively.
When an I/Ox pin is configured as an output, the pin can be set
high or low by programming the GPIO write data register. Logic TEMPERATURE INDICATOR
levels for general-purpose outputs are relative to VDD and GND.
When an I/Ox pin is configured as an input, its status can be The AD5593R contains an integrated temperature indicator that
determined by setting the pointer byte to 0b01100000. When an can be read to provide an estimation of the die temperature. This
I/Ox pin is set as an output, it is possible to read its status by also can be used in fault detection where a sudden rise in die temper-
setting it as an input pin. When reading the status of the I/Ox pins ature may indicate a fault condition, such as a shorted output.
set as inputs the status of an I/Ox pin set as both and input and Temperature readback is enabled by setting Bit 8 in the ADC
output pin is also returned. sequence register. The temperature result is then added to the ADC
sequence. The temperature result has an address of 0b1000 (see
INTERNAL REFERENCE Table 34) and care must be taken that this result is not confused
with the readback from DAC0 (see Table 32). The temperature
The AD5593R contains an on-chip 2.5 V reference. The reference conversion takes 5 µs with the ADC buffer enabled and 20 µs when
is powered down by default and is enabled by setting Bit 9 in the the buffer is disabled. Calculate the temperature using the following
power-down/reference control register to 1. When the on-chip refer- formulae:
ence is powered up, the reference voltage appears on the VREF pin
and may be used as a reference source for other components. For ADC gain = 1,
When the internal reference is used, it is recommended to decouple ADC Code − 0.5 / VREF × 4095
VREF to GND using a 100 nF capacitor. It is recommended that Temperature (°C) = 25 + 2.654 × 2.5 / VREF
the internal reference be buffered before using it elsewhere in
the system. When the reference is powered down, an external For ADC gain = 2,
reference must be connected to VREF. Suitable external reference
Temperature (°C) =
sources for the AD5593R include the AD780, AD1582, ADR431, ADC Code − 0.5 / 2 × VREF × 4095
REF193, and ADR391. 25 + 1.327 × 2.5 / VREF
RESET FUNCTION The range of codes returned by the ADC when reading from the
The AD5593R has an asynchronous RESET pin. For normal oper- temperature indicator is approximately 645 to 1035, (for ADC gain
ation, RESET is tied high. A falling edge on RESET resets all = 1) corresponding to a temperature between −40°C and +105°C.
registers to their default values and reconfigures the I/O pins to The accuracy of the temperature indicator is typically 3°C when
their default values (85 kΩ pull-down resistor to GND). The reset averaged over five samples.
function takes 250 µs maximum; do not write new data to the

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Data Sheet AD5593R
SERIAL INTERFACE

The AD5593R has a 2-wire, I2C-compatible serial interface (refer tions on the SDA line must occur during the low period of SCL and
to The I2C -Bus Specification, Version 2.1, January 2000). The remain stable during the high period of SCL. When all data bits
AD5593R is connected to an I2C bus as a slave device under the have been read or written, a stop condition is established.
control of a master device. See Figure 2 for a timing diagram of
a typical write sequence. The AD5593R supports standard mode In write mode, the master pulls the SDA line high during the 10th
(100 kHz) and fast mode (400 kHz). Support is not provided for clock pulse to establish a stop condition. In read mode, the master
10-bit addressing and general call addressing. The AD5593R has a issues a no acknowledge for the ninth clock pulse (that is, the
7-bit slave address; its six MSBs are set to 001000. The LSB is set SDA line remains high). The master brings the SDA line low before
by the state of the A0 address pin, which determines the state of the 10th clock pulse and then high during the 10th clock pulse to
the A0 bit. The facility to change the logic level of the A0 pin before establish a stop condition.
a read or write operation allows the user to incorporate multiple WRITE OPERATION
AD5593R devices on one bus.
When writing to the AD5593R, the user must begin with a start
The 2-wire serial bus protocol operates as follows: the master command followed by an address byte R/W = 0), after which the
initiates data transfer by establishing a start condition when a AD5593R acknowledges that it is prepared to receive data by
high-to-low transition on the SDA line occurs while SCL is high. pulling SDA low. The AD5593R requires three bytes of data. The
The following byte is the address byte, which consists of the 7-bit first byte is the pointer byte. This byte contains information defining
slave address. The slave address corresponding to the transmitted the type of operation that is required of the AD5593R, such as
address responds by pulling SDA low during the ninth clock pulse configuring the I/O pins and writing to a DAC. The pointer byte is
(this is termed the acknowledge bit). At this stage, all other devices followed by the most significant byte and the least significant byte,
on the bus remain idle while the selected device waits for data to be as shown in Figure 36. After these data bytes are acknowledged by
written to or read from its shift register. the AD5593R, a stop condition follows.
Data is transmitted over the serial bus in sequences of nine clock
pulses (eight data bits followed by an acknowledge bit). The transi-

Figure 36. 4-Byte I2C Write

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Data Sheet AD5593R
SERIAL INTERFACE

READ OPERATION follow to read two bytes of data from the AD5593R. Both bytes are
acknowledged by the master, as shown in Figure 37.
When reading data back from the AD5593R, the user begins with a
start command followed by an address byte (R/W = 0), after which It is also possible to perform consecutive readbacks without having
the AD5593R acknowledges that it is prepared to transmit data by to provide interim start and stop conditions or slave addresses. This
pulling SDA low. The pointer byte is then written to select what is method can be used to read blocks of conversions from the ADC,
to be read back. A repeat start or a new I2C transmission can then as shown in Figure 39.

Figure 37. Read One 16-Bit Word

Figure 38. Read One 16-Bit Word, Maintain Control of the Bus

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Data Sheet AD5593R
SERIAL INTERFACE

Figure 39. I2C Block Read

POINTER BYTE GENERAL-PURPOSE CONTROL REGISTER

The pointer byte contains eight bits. Bits[7:4] are mode bits that The general-purpose control register enables or disables certain
select the operation to be executed. The data contained in Bits[3:0] functions associated with the DAC, ADC, and I/O pin configuration
depend on the operation required. Table 8 and Table 9 show (see Table 19). The register sets the output range of the DAC
the configuration of the pointer byte. When Bits[7:4] are 0b0000, and input range of the ADC, which sets their transfer functions, en-
the mode dependent bits (Bits[3:0]) select a control register (see ables/disables the ADC buffer, and enables the precharge function
Table 10) to write data to. The data written to a control register is (see the ADC Section section for more details). The register is also
contained in the MSB and LSB as shown in Figure 36. The mode used to lock the I/O pin configuration to prevent accidental change.
dependent data bits also select which DAC is updated during a When Bit 7 is set to 1, writes to the configuration registers are
DAC write operation and which register is selected for readback. ignored.
CONTROL REGISTERS CONFIGURING THE AD5593R
Table 11 shows the control register map for the AD5593R. The The AD5593R I/O pins are configured by writing to a series of pin
control registers configure the I/O pins and set various operating configuration registers. The control registers are accessed when
parameters in the AD5593R, such as enabling the reference, se- Bits[7:4] of the pointer byte are 0b0000. Bits[3:0] determine which
lecting the LDAC mode function, or selecting power-down modes. register is accessed as shown in Table 11.
The control registers are written to using the 4-byte I2C write se-
quence shown in Figure 36. To write to a control register, the mode On power-up, the I/O pins are configured as 85 kΩ resistors
bits (Bits[7:4]) of the pointer byte are zeros. The mode dependent connected to GND. The I/O channels of the AD5593R can be
data bits (Bits[3:0]) of the pointer byte select which control register configured to operate as DAC outputs, ADC inputs, digital outputs,
is to be accessed. The data to be written to the control register is digital inputs, three-state, or connected to GND with 85 kΩ pull-
contained in the most significant and least significant data bytes. down resistors. When configured as digital outputs, the pins have
These contain a total of 16 bits and are shown as Bits[15:0] in the additional option of being configured as push/pull or open-drain.
the Register Details: AD5593R Control Register Map section. The The I/O channels are configured by writing to the appropriate
contents of the control registers can be read back using the read configuration registers, as shown in Table 11. To assign a particular
sequence shown in Figure 37 or Figure 38. function for an I/O channel, write to the appropriate register and

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Data Sheet AD5593R
SERIAL INTERFACE

set the corresponding bit to 1. For example, setting Bit 0 in the the primary function is as an output pin. This configuration allows
DAC pin configuration register configures I/O0 as a DAC. In the the status of the output pin to be determined by programming the
event that the bit for an I/O channel is set in multiple configuration GPIO read configuration register and then setting the pointer byte
registers, the I/O channel adopts the function dictated by the last to 0b01100000.
write operation.
The general-purpose control register contains a lock configuration
The exceptions to this rule are that an I/Ox pin can be set as both bit. When the lock configuration bit is set to 1, any writes to the pin
a DAC and ADC or as a digital input and output. When an I/Ox pin configuration registers are ignored, thus preventing the function of
is configured as a DAC and ADC, the primary function is as a DAC the I/O pins from being changed.
and the ADC can be used to measure the voltage being provided
by the DAC. This feature can be used to monitor the output voltage The I/O pins can be reconfigured any time when the AD5593R is in
to detect short circuits or overload conditions. Figure 40 shows an idle state, that is, no ADC conversions are taking place and no
an example of how to configure I/O1 and I/O7 as DACs. When registers are being read back. The lock configuration bit must also
a pin is configured as both a general-purpose input and output, be set to 0.

Figure 40. Configuring I/O1 and I/O7 as DACs

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Data Sheet AD5593R
SERIAL INTERFACE

DAC WRITE OPERATION the LDAC mode bits to 10, the values in the input registers transfer
to the DAC registers and the analog outputs update simultaneously.
Data is written to a DAC when the mode bits (Bits[7:4]) of the The LDAC mode bits then revert to 01.
pointer byte are 0b0001 (see Table 8). Bits[2:0] determine which
DAC is addressed (see Table 12). Data to be written to the DAC DAC READBACK
is contained in the MSB and LSB, as shown in Table 31. Data is
written to the selected DAC input register. Data written to the input The input register of each DAC can be read back via the I2C inter-
register can be automatically copied to the DAC register, if required. face. This can be useful to confirm that the data was received cor-
Data is transferred to the DAC register based on the setting of the rectly before writing to the LDAC mode register or simply checking
LDAC mode register (see Table 23). what value was last loaded to a DAC. Data can be read back from
a DAC only when no ADC conversion sequence is taking place. A
DAC input register can be read back using the sequence shown in
LDAC Mode Operation
Figure 37 or Figure 38. The mode dependent bits, Bits[3:0], of the
The transfer of data from an input register to a DAC register is DAC readback mode register (pointer byte = 0b0101XXXX), select
controlled by Bits[1:0] of the LDAC mode register (pointer byte which DAC input register is to be read back (see Table 14). When
= 0b00000111). When the LDAC mode bits (Bits[1:0]) are set to the DAC register is read back as shown in Table 32, the MSB of the
00, new data is automatically transferred from the input register to most significant data byte is a 1 to indicate that the result is a DAC
the DAC register and the analog output updates. When the LDAC register. The next three bits (Bits[14:12]) contain the DAC register
mode bits are set to 01, data remains in the input register. This address (see Table 32) and Bits[11:0] contain the DAC register
allows writes to input registers without affecting the analog outputs. value. Figure 41 shows an example of reading the input register of
After loading the input registers with the desired values and setting DAC2.

Figure 41. DAC Input Register Readback

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Data Sheet AD5593R
SERIAL INTERFACE

ADC OPERATION sequence. If the REP bit is clear, the ADC clocks out the last result
on subsequent I2C reads. When ADC data is clocked out by the
The ADC channels of the AD5593R operate as a traditional multi- serial interface, Bit 15 = 0 to indicate that the result is ADC data.
channel ADC, where each serial transfer selects the next channel Bits[14:12] contain a 3-bit address to indicate which ADC the data
for conversion. The user must write to the ADC pin configuration is coming from, and Bits[11:0] contain the 12-bit ADC result (see
register (see Table 20) to select the input channels as ADC inputs Table 33).
to be included in the conversion sequence before initiating any
conversions. This is done using the I2C write sequence shown in Figure 42 shows how to configure the AD5593R to perform ADC
Figure 36. When writing to the ADC sequence register (see Table conversions. In Step 1, I/O7 and I/O0 are configured as ADCs.
18), select which channels are to be converted in sequence. The Step 2 writes to the ADC sequence register, sets the REP bit, and
user can also set the REP bit to have the ADC repeat conversions selects ADC7 and ADC0 for inclusion in the conversion sequence.
in the sequence. Step 3 selects the ADCs for reading and Step 4 begins reading the
ADC results (see Table 33). The conversions are repeated until a
When the sequence register has been written to, the ADC begins stop condition is given by the controller.
to track the first channel in the sequence. ADC data can be read
from the AD5593R using any of the three read operations shown in The ADC sequence can be changed by writing the new sequence
Figure 37, Figure 38, and Figure 39, with the I2C block read (Figure to the ADC sequence register when conversions are not taking
39) being the most efficient. place. When a new sequence is written, any channels remaining to
be converted from the earlier sequence are ignored and the ADC
If more than one channel is selected in the ADC sequence register, starts converting the first channel of the new sequence.
the ADC converts all selected channels sequentially in ascending
order. Conversion is started by the rising edge of SCL at the To stop the ADC conversion sequence, clear the REP, TEMP, and
acknowledge (ACK) preceding the MSB (see Figure 39). ADC7 to ADC0 bits in the ADC sequence register to 0.
If the REP bit is set after all of the selected channels in the
sequence register have been converted, the ADC repeats the

Figure 42. Configuring the ADC for Conversion

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Data Sheet AD5593R
SERIAL INTERFACE

GPIO OPERATION 85 KΩ PULL-DOWN PINS

Each of the I/Ox pins of the AD5593R can be configured to operate The I/Ox pins can be connected to GND via a pull-down resistor
as a general-purpose, digital input or output pin. The function of (85 kΩ) by setting the appropriate bits in the pull-down configuration
the pins is determined by writing to the appropriate bit in the GPIO register (pointer byte = 0b00000110) as shown in Table 22.
read configuration register and the GPIO write configuration register
using the 4-byte I2C write shown in Figure 36. POWER-DOWN/REFERENCE CONTROL

Setting Pins as Outputs The AD5593R has a power-down/reference control register (pointer
byte = 0b00001011) that reduces the power consumption when
To set a pin as a general-purpose output, set the appropriate bit in certain functions are not needed. The power-down register allows
the GPIO write configuration register (pointer byte = 0b00001000) any channels set as DACs to be placed in a power-down state
to 1. For example, setting Bit 0 to 1 enables I/O0 as a general-pur- individually. When in power-down, the DAC outputs are three-stat-
pose output. ed. When a DAC channel is returned into normal mode, the DAC
output returns to its previous value. The internal reference and its
The outputs can be independently configured as push/pull or open- buffer are powered down by default and are enabled by setting
drain outputs. When in push/pull configuration, the output is driven the EN_REF bit in the power-down/reference control register. The
to VDD or GND as determined by the data in the GPIO write internal reference voltage then appears at the VREF pin.
data register (pointer byte = 0b00001001). When in open-drain
configuration (pointer byte = 0b00001100), the output is driven to There is no dedicated power-down function for the ADC, but the
GND when a data bit in the GPIO write data register sets the pin ADC is automatically powered down if none of the I/Ox pins are
low. When the pin is set high, the output is not driven and must be selected as ADCs. The ADC powers up if a read of the tempera-
pulled high by an external resistor. This allows multiple output pins ture indicator is initiated. The PD_ALL bit powers down all the
to be tied together. If all the pins are normally high, it allows one pin DACs, the reference, its buffer, and the ADC. The PD_ALL bit also
to pull down the others. This is commonly used where multiple pins overrides the settings of Bits[9:0]. Table 27 shows the power-down
are used to trigger an alarm or interrupt pin. The state of the output register.
pin is controlled by setting or clearing the bits in the GPIO write
data register (pointer byte = 0b00001001). A data bit is ignored if it RESET FUNCTION
is written to a location that is not configured as an output. The AD5593R can be reset to its default conditions by writing
0x0DAC to the software reset register (pointer byte = 0b00001111).
Setting Pins as Inputs This resets all registers to their default values and reconfigures the
I/Ox pins to their default values (85 kΩ pull-down to GND). The
To set an I/Ox pin as a general-purpose input, set the appropri-
reset function is triggered on the SCL falling edge of the eighth bit
ate bit in the GPIO read configuration register (pointer byte =
of the least significant byte (Bit 0 of Frame 4 in Figure 36), and the
0b00001010) to 1. For example, setting Bit 0 to 1 enables I/O0 as a
AD5593R does not generate an ACK signal for this byte of data.
general-purpose input. To read the state of general-purpose inputs,
The AD5593R has a RESET pin that performs the same function.
set the pointer byte to 0b01100000 (see Table 9) using any of the
For normal operation, RESET is tied high. A falling edge on RESET
read operations shown in Figure 37, Figure 38, and Figure 39. The
triggers the reset function. Both the hardware and the software
status of any I/O pin set as a general-purpose input appears in the
reset functions take 250 µs maximum and there must be no activity
appropriate bit location in the least significant data byte.
on the SCL pin of the AD5593R during this time.
THREE-STATE PINS
The I/Ox pins can be set to three-state by writing to the three-state
configuration register (pointer byte = 0b00001101) as shown in
Table 29.

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Data Sheet AD5593R
APPLICATIONS INFORMATION

MICROPROCESSOR INTERFACING LAYOUT GUIDELINES

Microprocessor interfacing to the AD5593R is via a serial bus using In any circuit where accuracy is important, careful consideration
a standard I2C protocol. The communications channel requires a of the power supply and ground return layout helps to ensure the
2-wire interface consisting of a clock signal and a data signal. rated performance. The printed circuit board (PCB) on which the
AD5593R is mounted must be designed so that the AD5593R lies
AD5593R TO ADSP-BF537 INTERFACE on the analog plane.
The I2C interface of the AD5593R is designed to be easily con- The AD5593R must have ample supply bypassing of 10 µF in
nected to industry-standard DSPs and microcontrollers. Figure 43 parallel with 0.1 µF on each supply, located as close to the pack-
shows the AD5593R connected to the Analog Devices Blackfin® age as possible, ideally right up against the device. The 10 µF
DSP. The Blackfin has an integrated I2C port that can be connected capacitors are the tantalum bead type. The 0.1 µF capacitor must
directly to the I2C pins of the AD5593R. have low effective series resistance (ESR) and low effective series
inductance (ESI) such as the common ceramic types, which provide
a low impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.

Figure 43. ADSP-BF537 Interface

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Data Sheet AD5593R
REGISTER MAP

The AD5593R has programmable user configuration registers that See the Register Details: AD5593R Control Register Map section
are used to configure the device. Table 8 shows a complete list of for details about the functions of each of the bits.
the pointer byte registers that select the operation to be executed.
See Table 9 and the Register Details: AD5593R Pointer Byte Map The Register Details: AD5593R ADC and DAC Readback section
section for details about the functions of each of the bits. provides data formats for the ADC and the DAC readback.

Table 10 shows a complete list of the control registers that config-

ure the I/O pins and various operating parameters in the AD5593R.
REGISTER SUMMARY: AD5593R POINTER BYTE MAP

Table 8. POINTER_BYTE Register Summary

Pointer Byte Bits[7:4] Name Description
0x0 CONFIG_MODE_POINTER Configuration mode.
0x1 DAC_WR_POINTER DAC write mode.
0x4 ADC_RD_POINTER ADC readback mode.
0x5 DAC_RD_POINTER DAC readback mode.
0x6 GPIO_RD_POINTER GPIO readback mode.
0x7 REG_RD_POINTER Register readback mode.

REGISTER SUMMARY (BIT-WISE): AD5593R POINTER BYTE MAP

Table 9. AD5593R_POINTER MAP Register Summary

Mode Bits Mode Bits Mode Dependent Data Bits
Bits[7:4] Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0 CONFIG_MODE_POINTER [7:0] CONFIG_MODE_SEL CONFIG_MODE_BITS
0x1 DAC_WR_POINTER [7:0] DAC_WR_SEL DAC_CH_SEL_WR
0x4 ADC_RD_POINTER [7:0] ADC_RD_SEL RESERVED
0x5 DAC_RD_POINTER [7:0] DAC_RD_SEL DAC_CH_SEL_RD
0x6 GPIO_RD_POINTER [7:0] GPIO_RD_SEL RESERVED
0x7 REG_RD_POINTER [7:0] REG_RD_SEL REG_SEL_RD

REGISTER SUMMARY: AD5593R CONTROL REGISTER MAP

Table 10. AD5593R_CORE Register Summary

Pointer Byte Bits[7:0] Name Description Reset Data Bits[15:0]
0x00 NOP NOP. 0x0000
0x02 ADC_SEQ ADC Sequence Register. 0x0000
0x03 GEN_CTRL_REG General-Purpose Control Register. 0x0000
0x04 ADC_CONFIG ADC Pin Configuration Register. 0x0000
0x05 DAC_CONFIG DAC Pin Configuration Register. 0x0000
0x06 PULLDWN_CONFIG Pull-Down Configuration Register. 0x00FF
0x07 LDAC_MODE LDAC Mode Register. 0x0000
0x08 GPIO_CONFIG GPIO Write Configuration Register. 0x0000
0x09 GPIO_OUTPUT GPIO Write Data Register. 0x0000
0x0A GPIO_INPUT GPIO Read Configuration Register. 0x0000
0x0B PD_REF_CTRL Power-Down/Reference Control Register. 0x0000
0x0C GPIO_OPENDRAIN_CONFIG GPIO Open-Drain Configuration Register. 0x0000
0x0D IO_TS_CONFIG Three-State Configuration Register. 0x0000

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Data Sheet AD5593R
REGISTER MAP

Table 10. AD5593R_CORE Register Summary (Continued)

Pointer Byte Bits[7:0] Name Description Reset Data Bits[15:0]
0x0F SW_RESET Software Reset. 0x0000
0x10 DAC_WR DAC Write Register. 0x0000

REGISTER DETAILS: AD5593R POINTER BYTE MAP

Configuration Mode Register

Reset: 0x00, Name: CONFIG_MODE_POINTER
Pointer byte configuration register.

Table 11. Bit Descriptions for CONFIG_MODE_POINTER

Bits Bit Name Description Reset Access
[7:4] CONFIG_MODE_SEL Configuration mode address. 0x0 W
[3:0] CONFIG_MODE_BITS Configuration mode dependent data bits. 0x0 W
0000: NOP. No operation.
0010: ADC sequence register. Selects ADCs for conversion.
0011: General-purpose control register. DAC and ADC control register.
0100: ADC pin configuration. Selects which pins are ADC inputs.
0101: DAC pin configuration. Selects which pins are DAC outputs.
0110: Pull-down configuration. Selects which pins have an 85 kΩ pull-down resistor to GND.
0111: LDAC mode. Selects the operation of the load DAC.
1000: GPIO write configuration. Selects which pins are general-purpose outputs.
1001: GPIO write data. Writes data to general-purpose outputs.
1010: GPIO read configuration. Selects which pins are general-purpose inputs.
1011: Power-down/reference control. Powers down the DACs and enables/disables the reference.
1100: Open-drain configuration. Selects open-drain or push-pull for general-purpose outputs.
1101: Three-state pins. Selects which pins are three-stated.
1111: Software reset. Resets the AD5593R.

DAC Write Mode Register

Reset: 0x10, Name: DAC_WR_POINTER

Table 12. Bit Descriptions for DAC_WR_POINTER

Bits Bit Name Description Reset Access
[7:4] DAC_WR_SEL DAC write mode address. 0x1 W

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Data Sheet AD5593R
REGISTER MAP

Table 12. Bit Descriptions for DAC_WR_POINTER (Continued)

Bits Bit Name Description Reset Access
[3:0] DAC_CH_SEL_WR Select DAC channel for input register write. 0x0 W
000: DAC0.
001: DAC1.
010: DAC2.
011: DAC3.
100: DAC4.
101: DAC5.
110: DAC6.
111: DAC7.

ADC Readback Mode Register

Reset: 0x40, Name: ADC_RD_POINTER

Table 13. Bit Descriptions for ADC_RD_POINTER

Bits Bit Name Description Reset Access
[7:4] ADC_RD_SEL ADC readback mode address. 0x4 W
[3:0] RESERVED Reserved. 0x0 R

DAC Readback Mode Register

Reset: 0x50, Name: DAC_RD_POINTER

Table 14. Bit Descriptions for DAC_RD_POINTER

Bits Bit Name Description Reset Access
[7:4] DAC_RD_SEL DAC readback mode address. 0x5 W
[3:0] DAC_CH_SEL_RD Select DAC channel for input register readback. 0x0 W
000: DAC0.
001: DAC1.
010: DAC2.
011: DAC3.
100: DAC4.
101: DAC5.
110: DAC6.
111: DAC7.

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Data Sheet AD5593R
REGISTER MAP

GPIO Readback Mode Register

Reset: 0x60, Name: GPIO_RD_POINTER

Table 15. Bit Descriptions for GPIO_RD_POINTER

Bits Bit Name Description Reset Access
[7:4] GPIO_RD_SEL GPIO readback mode address. 0x6 W
[3:0] RESERVED Reserved. 0x0 R

Register Readback Mode

Reset: 0x70, Name: REG_RD_POINTER

Table 16. Bit Descriptions for REG_RD_POINTER

Bits Bit Name Description Reset Access
[7:4] REG_RD_SEL Register readback mode address. 0x7 W
[3:0] REG_SEL_RD Select control register for register readback. 0x0 W
0000: NOP.
0010: ADC sequence register.
0011: General-purpose control register.
0100: ADC pin configuration.
0101: DAC pin configuration.
0110: Pull-down configuration.
0111: LDAC mode.
1000: GPIO write configuration.
1001: GPIO write data.
1010: GPIO read configuration.
1011: Power-down/reference control.
1100: Open-drain configuration.
1101: Three-state pins.

REGISTER DETAILS: AD5593R CONTROL REGISTER MAP

NOP Register
Reset: 0x0000, Name: NOP
No operation.

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Data Sheet AD5593R
REGISTER MAP

Table 17. Bit Descriptions for NOP

Bits Bit Name Description Reset Access
[15:11] RESERVED Reserved. 0x0 R
[10:0] NOP No operation. 0x0 R/W

ADC Sequence Register

Reset: 0x0000, Name: ADC_SEQ
Selects ADCs for conversion.

Table 18. Bit Descriptions for ADC_SEQ

Bits Bit Name Description Reset Access
[15:10] RESERVED Reserved. 0x0 R
9 REP ADC sequence repetition. 0x0 R/W
0: Sequence repetition disabled.
1: Sequence repetition enabled.
8 TEMP Include temperature indicator in ADC sequence. 0x0 R/W
0: Disable temperature indicator readback.
1: Enable temperature indicator readback.
7 ADC7 Include the ADC7 channel in conversion sequence. 0x0 R/W
0: The selected ADC channel is not included in the conversion sequence.
1: Include the selected ADC channel in the conversion sequence.
6 ADC6 Include the ADC6 channel in conversion sequence. 0x0 R/W
0: The selected ADC channel is not included in the conversion sequence.
1: Include the selected ADC channel in the conversion sequence.
5 ADC5 Include the ADC5 channel in conversion sequence. 0x0 R/W
0: The selected ADC channel is not included in the conversion sequence.

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Data Sheet AD5593R
REGISTER MAP

Table 18. Bit Descriptions for ADC_SEQ (Continued)

Bits Bit Name Description Reset Access
1: Include the selected ADC channel in the conversion sequence.
4 ADC4 Include the ADC4 channel in conversion sequence. 0x0 R/W
0: The selected ADC channel is not included in the conversion sequence.
1: Include the selected ADC channel in the conversion sequence.
3 ADC3 Include the ADC3 channel in conversion sequence. 0x0 R/W
0: The selected ADC channel is not included in the conversion sequence.
1: Include the selected ADC channel in the conversion sequence.
2 ADC2 Include the ADC2 channel in conversion sequence. 0x0 R/W
0: The selected ADC channel is not included in the conversion sequence.
1: Include the selected ADC channel in the conversion sequence.
1 ADC1 Include the ADC1 channel in conversion sequence. 0x0 R/W
0: The selected ADC channel is not included in the conversion sequence.
1: Include the selected ADC channel in the conversion sequence.
0 ADC0 Include the ADC0 channel in conversion sequence. 0x0 R/W
0: The selected ADC channel is not included in the conversion sequence.
1: Include the selected ADC channel in the conversion sequence.

General-Purpose Control Register

Reset: 0x0000, Name: GEN_CTRL_REG
DAC and ADC control register.

Table 19. Bit Descriptions for GEN_CTRL_REG

Bits Bit Name Description Reset Access
[15:10] RESERVED Reserved. 0x0 R
9 ADC_BUF_PRECH ADC buffer precharge. 0x0 R/W
0: ADC buffer is not used to precharge the ADC. If the ADC buffer is enabled, it is always powered up.
1: ADC buffer is used to precharge the ADC. If the ADC buffer is enabled, it is powered up while the
conversion takes place and then powered down until the next conversion takes place.
8 ADC_BUF_EN ADC buffer enable. 0x0 R/W
0: ADC buffer is disabled.
1: ADC buffer is enabled.
7 IO_LOCK Lock configuration. 0x0 R/W
0: The contents of the I/Ox pin configuration register can be changed.
1: The contents of the I/Ox pin configuration register cannot be changed.
6 ALL_DAC Write all DACs. 0x0 R/W

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Data Sheet AD5593R
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Table 19. Bit Descriptions for GEN_CTRL_REG (Continued)

Bits Bit Name Description Reset Access
0: For future DAC writes, the DAC address bits determine which DAC is written to.
1: For future DAC writes, the DAC address bits are ignored, and all channels configured as DACs are
updated with the same data.
5 ADC_RANGE ADC input range select. 0x0 R/W
0: ADC gain is 0 V to VREF.
1: ADC gain is 0 V to 2 × VREF.
4 DAC_RANGE DAC output range select. 0x0 R/W
0: DAC output range is 0 V to VREF.
1: DAC output range is 0 V to 2 × VREF.
[3:0] RESERVED Reserved. 0x0 R

ADC Pin Configuration Register

Reset: 0x0000, Name: ADC_CONFIG
Selects which pins are ADC inputs.

Table 20. Bit Descriptions for ADC_CONFIG

Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved. 0x0 R
7 ADC7 Select the I/O7 pin as ADC input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is an ADC input.
6 ADC6 Select the I/O6 pin as ADC input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is an ADC input.
5 ADC5 Select the I/O5 pin as ADC input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is an ADC input.
4 ADC4 Select the I/O4 pin as ADC input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is an ADC input.
3 ADC3 Select the I/O3 pin as ADC input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is an ADC input.

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Data Sheet AD5593R
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Table 20. Bit Descriptions for ADC_CONFIG (Continued)

Bits Bit Name Description Reset Access
2 ADC2 Select the I/O2 pin as ADC input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is an ADC input.
1 ADC1 Select the I/O1 pin as ADC input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is an ADC input.
0 ADC0 Select the I/O0 pin as ADC input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is an ADC input.

DAC Pin Configuration Register

Reset: 0x0000, Name: DAC_CONFIG
Selects which pins are DAC outputs.

Table 21. Bit Descriptions for DAC_CONFIG

Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved. 0x0 R
7 DAC7 Select the I/O7 pin as DAC output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a DAC output.
6 DAC6 Select the I/O6 pin as DAC output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a DAC output.
5 DAC5 Select the I/O5 pin as DAC output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a DAC output.
4 DAC4 Select the I/O4 pin as DAC output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a DAC output.
3 DAC3 Select the I/O3 pin as DAC output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a DAC output.
2 DAC2 Select the I/O2 pin as DAC output. 0x0 R/W

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Data Sheet AD5593R
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Table 21. Bit Descriptions for DAC_CONFIG (Continued)

Bits Bit Name Description Reset Access
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a DAC output.
1 DAC1 Select the I/O1 pin as DAC output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a DAC output.
0 DAC0 Select the I/O0 pin as DAC output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a DAC output.

Pull-Down Configuration Register

Reset: 0x00FF, Name: PULLDWN_CONFIG
Selects which pins have an 85 kΩ pull-down resistor to GND.

Table 22. Bit Descriptions for PULLDWN_CONFIG

Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved. 0x0 R
7 PULL_DWN_7 Set the I/O7 pin as weak pull-down output. 0x1 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor.
6 PULL_DWN_6 Set the I/O6 pin as weak pull-down output. 0x1 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor.
5 PULL_DWN_5 Set the I/O5 pin as weak pull-down output. 0x1 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor.
4 PULL_DWN_4 Set the I/O4 pin as weak pull-down output. 0x1 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor.
3 PULL_DWN_3 Set the I/O3 pin as weak pull-down output. 0x1 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor.

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Data Sheet AD5593R
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Table 22. Bit Descriptions for PULLDWN_CONFIG (Continued)

Bits Bit Name Description Reset Access
2 PULL_DWN_2 Set the I/O2 pin as weak pull-down output. 0x1 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor.
1 PULL_DWN_1 Set the I/O1 pin as weak pull-down output. 0x1 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor.
0 PULL_DWN_0 Set the I/O0 pin as weak pull-down output. 0x1 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor.

LDAC Mode Register

Reset: 0x0000, Name: LDAC_MODE
Selects the operation of the load DAC (LDAC) function.

Table 23. Bit Descriptions for LDAC_MODE

Bits Bit Name Description Reset Access
[15:2] RESERVED Reserved. 0x0 R
[1:0] LDAC_MODE Determines how data written to an input register of a DAC is handled. 0x0 R/W
00: Data written to an input register is immediately copied to a DAC register, and the DAC output updates.
01: Data written to an input register is not copied to a DAC register. The DAC output is not updated.
10: Data in the input registers is copied to the corresponding DAC registers. When the data has been
transferred, the DAC outputs are updated simultaneously.

GPIO Write Configuration Register

Reset: 0x0000, Name: GPIO_CONFIG
Selects which pins are general-purpose outputs.

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Data Sheet AD5593R
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Table 24. Bit Descriptions for GPIO_CONFIG

Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved. 0x0 R
7 GPIO7 Select the I/O7 pin as GPIO output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose output pin.
6 GPIO6 Select the I/O6 pin as GPIO output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose output pin.
5 GPIO5 Select the I/O5 pin as GPIO output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose output pin.
4 GPIO4 Select the I/O4 pin as GPIO output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose output pin.
3 GPIO3 Select the I/O3 pin as GPIO output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose output pin.
2 GPIO2 Select the I/O2 pin as GPIO output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose output pin.
1 GPIO1 Select the I/O1 pin as GPIO output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose output pin.
0 GPIO0 Select the I/O0 pin as GPIO output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose output pin.

GPIO Write Data Register

Reset: 0x0000, Name: GPIO_OUTPUT
Writes data to the general-purpose outputs.

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Data Sheet AD5593R
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Table 25. Bit Descriptions for GPIO_OUTPUT

Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved. 0x0 R
7 GPIO7 Set the GPIO7 output pin as logic high or low. 0x0 R/W
0: The I/O pin is a Logic 0 output.
1: The I/O pin is a Logic 1 output.
6 GPIO6 Set the GPIO6 output pin as logic high or low. 0x0 R/W
0: The I/O pin is a Logic 0 output.
1: The I/O pin is a Logic 1 output.
5 GPIO5 Set the GPIO5 output pin as logic high or low. 0x0 R/W
0: The I/O pin is a Logic 0 output.
1: The I/O pin is a Logic 1 output.
4 GPIO4 Set the GPIO4 output pin as logic high or low. 0x0 R/W
0: The I/O pin is a Logic 0 output.
1: The I/O pin is a Logic 1 output.
3 GPIO3 Set the GPIO3 output pin as logic high or low. 0x0 R/W
0: The I/O pin is a Logic 0 output.
1: The I/O pin is a Logic 1 output.
2 GPIO2 Set the GPIO2 output pin as logic high or low. 0x0 R/W
0: The I/O pin is a Logic 0 output.
1: The I/O pin is a Logic 1 output.
1 GPIO1 Set the GPIO1 output pin as logic high or low. 0x0 R/W
0: The I/O pin is a Logic 0 output.
1: The I/O pin is a Logic 1 output.
0 GPIO0 Set the GPIO0 output pin as logic high or low. 0x0 R/W
0: The I/O pin is a Logic 0 output.
1: The I/O pin is a Logic 1 output.

GPIO Read Configuration Register

Reset: 0x0000, Name: GPIO_INPUT
Selects which pins are general-purpose inputs.

Table 26. Bit Descriptions for GPIO_INPUT

Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved. 0x0 R

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Table 26. Bit Descriptions for GPIO_INPUT (Continued)

Bits Bit Name Description Reset Access
7 GPIO7 Set the I/O7 pin as GPIO input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose input pin.
6 GPIO6 Set the I/O6 pin as GPIO input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose input pin.
5 GPIO5 Set the I/O5 pin as GPIO input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose input pin.
4 GPIO4 Set the I/O4 pin as GPIO input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose input pin.
3 GPIO3 Set the I/O3 pin as GPIO input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose input pin.
2 GPIO2 Set the I/O2 pin as GPIO input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose input pin.
1 GPIO1 Set the I/O1 pin as GPIO input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose input pin.
0 GPIO0 Set the I/O0 pin as GPIO input. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a general-purpose input pin.

Power-Down/Reference Control Register

Reset: 0x0000, Name: PD_REF_CTRL
Powers down DACs and enables/disables the reference.

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Table 27. Bit Descriptions for PD_REF_CTRL

Bits Bit Name Description Reset Access
[15:11] RESERVED Reserved. 0x0 R
10 PD_ALL Power down DACs and Internal Reference. 0x0 R/W
0: The reference and DACs power-down states are determined by EN_REF and PD7 to PD0 bits.
1: The reference, DACs and ADC are powered down.
9 EN_REF Enable internal reference. Set this bit to 0 if an external reference is used. 0x0 R/W
0: The reference and its buffer are powered down.
1: The reference and its buffer are powered up. The reference is available on the VREF pin.
8 RESERVED Reserved. 0x0 R
7 PD7 Power down the DAC7 channel. 0x0 R/W
0: The channel is in normal operating mode.
1: The channel is powered down if it is configured as a DAC.
6 PD6 Power down the DAC6 channel. 0x0 R/W
0: The channel is in normal operating mode.
1: The channel is powered down if it is configured as a DAC.
5 PD5 Power down the DAC5 channel. 0x0 R/W
0: The channel is in normal operating mode.
1: The channel is powered down if it is configured as a DAC.
4 PD4 Power down the DAC4 channel. 0x0 R/W
0: The channel is in normal operating mode.
1: The channel is powered down if it is configured as a DAC.
3 PD3 Power down the DAC3 channel. 0x0 R/W
0: The channel is in normal operating mode.
1: The channel is powered down if it is configured as a DAC.
2 PD2 Power down the DAC2 channel. 0x0 R/W
0: The channel is in normal operating mode.
1: The channel is powered down if it is configured as a DAC.
1 PD1 Power down the DAC1 channel. 0x0 R/W
0: The channel is in normal operating mode.
1: The channel is powered down if it is configured as a DAC.
0 PD0 Power down the DAC0 channel. 0x0 R/W
0: The channel is in normal operating mode.
1: The channel is powered down if it is configured as a DAC.

GPIO Open-Drain Configuration Register

Reset: 0x0000, Name: GPIO_OPENDRAIN_CONFIG
Selects open-drain or push/pull for general-purpose outputs. The selected I/Ox pin must be set as digital output pin in the GPIO_CONFIG
register.

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Table 28. Bit Descriptions for GPIO_OPENDRAIN_CONFIG

Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved. 0x0 R
7 GPIO7 Set the I/O7 pin as open-drain. 0x0 R/W
0: The I/O pin is a push/pull output pin.
1: The I/O pin is an open-drain output pin.
6 GPIO6 Set the I/O6 pin as open-drain. 0x0 R/W
0: The I/O pin is a push/pull output pin.
1: The I/O pin is an open-drain output pin.
5 GPIO5 Set the I/O5 pin as open-drain. 0x0 R/W
0: The I/O pin is a push/pull output pin.
1: The I/O pin is an open-drain output pin.
4 GPIO4 Set the I/O4 pin as open-drain. 0x0 R/W
0: The I/O pin is a push/pull output pin.
1: The I/O pin is an open-drain output pin.
3 GPIO3 Set the I/O3 pin as open-drain. 0x0 R/W
0: The I/O pin is a push/pull output pin.
1: The I/O pin is an open-drain output pin.
2 GPIO2 Set the I/O2 pin as open-drain. 0x0 R/W
0: The I/O pin is a push/pull output pin.
1: The I/O pin is an open-drain output pin.
1 GPIO1 Set the I/O1 pin as open-drain. 0x0 R/W
0: The I/O pin is a push/pull output pin.
1: The I/O pin is an open-drain output pin.
0 GPIO0 Set the I/O0 pin as open-drain. 0x0 R/W
0: The I/O pin is a push/pull output pin.
1: The I/O pin is an open-drain output pin.

Three-State Configuration Register

Reset: 0x0000, Name: IO_TS_CONFIG
Selects which pins are three-state.

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Data Sheet AD5593R
REGISTER MAP

Table 29. Bit Descriptions for IO_TS_CONFIG

Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved. 0x0 R
7 TS7 Set the I/O7 pin as three-state output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a three-state output pin.
6 TS6 Set the I/O6 pin as three-state output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a three-state output pin.
5 TS5 Set the I/O5 pin as three-state output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a three-state output pin.
4 TS4 Set the I/O4 pin as three-state output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a three-state output pin.
3 TS3 Set the I/O3 pin as three-state output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a three-state output pin.
2 TS2 Set the I/O2 pin as three-state output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a three-state output pin.
1 TS1 Set the I/O1 pin as three-state output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a three-state output pin.
0 TS0 Set the I/O0 pin as three-state output. 0x0 R/W
0: The I/O pin function is determined by the pin configuration registers.
1: The I/O pin is a three-state output pin.

Software Reset Register

Reset: 0x0000, Name: SW_RESET
Resets the AD5593R.

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Data Sheet AD5593R
REGISTER MAP

Table 30. Bit Descriptions for SW_RESET

Bits Bit Name Description Reset Access
[15:11] RESERVED Reserved. 0x0 R
[10:0] SW_RESET Write to RESET register. 0x0 R/W
10110101100: Reset the AD5593R.

DAC Write Register

Reset: 0x0000, Name: DAC_WR
Writes to addressed DAC register.

Table 31. Bit Descriptions for DAC_WR

Bits Bit Name Description Reset Access
[15:12] RESERVED Reserved. 0x0 R
[11:0] DAC_DATA_WR 12-bit DAC data. 0x0 R/W

REGISTER DETAILS: AD5593R ADC AND DAC READBACK

DAC Data Readback Register

Name: DAC_DATA_RD
Read back the 12-bit DAC input register data.

Table 32. Bit Descriptions for DAC_DATA_RD

Bits Bit Name Description Reset
15 MSB MSB. 0x1
[14:12] DAC_ADDR DAC Address. 0x0
000: DAC0.
001: DAC1.
010: DAC2.
011: DAC3.
100: DAC4.
101: DAC5.
110: DAC6.
111: DAC7.
[11:0] DAC_DATA 12-bit DAC Input Register Data. 0x0

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Data Sheet AD5593R
REGISTER MAP

ADC Conversion Result Register

Name: ADC_RESULT
ADC conversion result.

Table 33. Bit Descriptions for ADC_RESULT

Bits Bit Name Description Reset
15 MSB MSB. 0x0
[14:12] ADC_ADDR ADC address. 0x0
000: ADC0.
001: ADC1.
010: ADC2.
011: ADC3.
100: ADC4.
101: ADC5.
110: ADC6.
111: ADC7.
[11:0] ADC_DATA 12-bit ADC result. 0x0

Temperature Reading Register

Name: TMP_SENSE_RESULT
Temperature reading.

Table 34. Bit Descriptions for TMP_SENSE_RESULT

Bits Bit Name Description Reset
[15:12] TMPSENSE_ADDR Temperature Indicator Address. 0x8
[11:0] ADC_DATA 12-bit ADC Result. 0x0

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Data Sheet AD5593R
OUTLINE DIMENSIONS

Figure 44. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)
Dimensions shown in millimeters

Figure 45. 16-Lead Lead Frame Chip Scale Package [LFCSP]

3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-32)
Dimensions shown in millimeters

Figure 46. 16-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-16-3)
Dimensions shown in millimeters

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Data Sheet AD5593R
OUTLINE DIMENSIONS

Updated: May 31, 2023

ORDERING GUIDE
Package
Model1 Temperature Range Package Description Packing Quantity Option Marking Code
AD5593RBCBZ-RL7 -40°C to +105°C 16-Ball WLCSP (1.96mm x 1.96mm) Reel, 3000 CB-16-3
AD5593RBCPZ-RL7 -40°C to +105°C 16-Lead LFCSP (3mm x 3mm x 0.75mm) Reel, 1500 CP-16-32 DM6
AD5593RBRUZ -40°C to +105°C 16-Lead TSSOP RU-16
AD5593RBRUZ-RL7 -40°C to +105°C 16-Lead TSSOP Reel, 1000 RU-16
1 Z = RoHS Compliant Part.

EVALUATION BOARDS
Model1 Description
EVAL-AD5593RSDZ Evaluation Board
EVAL-SDP-CB1Z Controller Board
1 Z = RoHS Compliant Part.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

©2014-2023 Analog Devices, Inc. All rights reserved. Trademarks and Rev. H | 47 of 47
registered trademarks are the property of their respective owners.
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