Physics
Project Report
On
“Logic Gates”
(OR, AND, NOT GATE)
Session: 2019-20
Under Supervision of Submitted by
Ms. Preeti Harshmeep
Lecturer in Physics Class XII
(Medical )
Roll No.
Giandeep Public School,
Kurukshetra
CERTIFICATE
Certified that the investigatory project entitled “To Study Logic Gates
(OR, AND, NOT GATES)” was carried out in Physics by
Harshmeep , a student of XII (Medical ) Roll No. ,
Giandeep Public School, Kurukshetra as a partial fulfillment of the
practical work conducted by the Central Board of Secondary Education,
New Delhi.
Ms. Preeti
Lecturer in Physics
ACKNOWLEDGEMENT
I take this opportunity to thank and express my sincere gratitude to
Ms. Preeti, Lecturer in Physics who guided me for this project and without
whose efforts, this project would not have been completed. I put my sincere
efforts to make this project interesting. I fully consulted all the available
books on this subject and I am thankful to esteemed authors. I also want to
mention the Physics Laboratory Assistant who also helped me a lot.
In the end, I am thankful to all those who took interest in the
successful completion of the project.
Harshmeep
XII (Medical )
Roll No.
PROJECT: To Study the Logic Gates
(OR, AND, NOT GATES)
Logic Gates: A digital circuit which either allows a signal to pass
through or stops it, is called a gate. Such gate allows the signal to pass
through only when some logic conditions are satisfied. Hence they are
called logic gates.
The basic logic gates are of three types:
1. OR gate
2. AND gate
3. NOT gate
1. The OR GATE
In Boolean Algebra the term OR is represented by addition symbol
(+). It means that Boolean expression Y = A+B ‘Y” equals A or B”.
The OR gate is a digital circuit arrangement which combines A
and B so as to give Y given by Y = A+B as the result. The OR gate is
device having two inputs and one output. Logic symbol, Truth table,
Boolean expression for a two input. OR gate is given in fig. (1). Here A
and B are two inputs and Y is output.
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
(a) Logic Symbol of OR Gate (b) Truth Table
In practice and OR gate may be realized by two ideal p-n junction
diodes D1 and D2 as shown in Fig. (2). The input voltages which can
be applied at A or B is either 0 or a finite value (+5V in Fig. 2). The -ve
terminal of the battery in figure, thus, represents the o state and the ±ve
corresponds to the 1 state.
A D1
1
Y
B D2
+
R
-
There are four possible cases in it:
Fig. 2
i When both A and B are connection to earth, none of the diodes
conduct and hence no voltage developed across the resistor and
consequently the output y is 0. In truth table first line represent
this possibility.
ii When A is connected to earth and b is connected to +ve terminal
of batter, junction diode D1 does not conduct but D2 conducts. If
the diode is an ideal on then output voltage at Y will also be 5 V.
Second line of truth table represents this possibility.
iii When A is in 1 state and B in 0 state, D1 conducts but D2 does
not conduct and the output y is in 1 state. Third line of truth table
represents is possibility.
iv When A as well as B both are in 1 state, both the diodes conduct.
As the output of both the diodes obtained across the resistor R are
in parallel, the net output even this case will be same as in (ii) or
(iii). It means that the output Y is in I state. Last line of truth
table represents this possibility.
2. The AND Gate
In Boolean algebra the term AND is represented by dot (.) and the
Boolean expression A.B = Y implies that Y equals A and B. The AND
Gate is an electronic circuit arrangement which combines A and B so
as to give Y A.B as the results. The AND Gate is a device having two
inputs and one output. Fig. 3 shows the logic symbol, truth table and
the Boolean expression for a two input AND gate.
A A B Y
Y
0 0 0
0 1 0
B
1 0 0
1 1 1
(a) Logic Symbol of AND Gate (b) Truth Table
To realise AND Gate we complete and electronic circuit shown
in Fig. by making use of two ideal p-n junction diodes. The resistor R is
connected to the +ve terminal of a battery having same voltage as that
of battery connected to input A or B.
Fig. 3
There are our following situations in AND Gate:
i When both A and B are at 0 state, the diodes D1 and D2 both
conduct. The voltage output at Y will be the voltage across either
diodes D1 and D2 and for ideal diodes there is no voltage drop
across either diode. Thus, the output Y is at 0.
ii When A is 0 state but B in 1 state, only D 1 diode conducts and D2
does not conduct. Now the output Y equals the voltage across D 1
and is 0.
iii When A is in 1 state but B in 0 state, only D 2 conducts and D1 does
not conduct. Now the output Y equals the voltage across D 2 and is
0.
iv When A and B both are in 1 state, none of them conducts. The
output voltage at Y equals the battery voltage and, thus it is 1.
The NOT Gate
In Boolean algebra the term NOT is represented by bar symbol
(-) and the Boolean expression A = Y implies that Y equals not A.
The bar over A means we change A to the alternative digit. As in
binary system, there are only two digits 0 and 1, we have
0 = 1 and T = 0
Thus, the NOT operation is also called inversion. The NOT gate
is a device which inverts the input. If the input is 0, the output is 1 and
if the input is 1, the output is 0.
The NOT gate is an electronic device having one input and one
output, which inverts the input i.e. which fulfils the condition A = Y.
the logic symbol, truth table and the Boolean expression for a NOT
gate is shown in Fig. 5.
A Y
0 1
1 0
(a) Logic Symbol of NOT Gate (b) Truth Table
A NOT gate cannot be realised by diodes and to realise a NOT
gate we make use of a transistor.
A simple circuit of NOT gate using an n-p-n transistor is being
shown in Fig. 6. The base of the transistor is connected to the input A
through a resistor Rb and the emitter is earthed. The collector is earthed
through a resistor R and a Battery having the same voltage as that
supplied to input A.
5V
Rc
Y
Rb
1
Fig. 6
The operation of the NOT gate maybe considered by the
following two cases:
i When input terminal A is in 0 state, the Base of the transistor also
gets earthed. It means the base emitter in is not forward biased and
the base collector i is reverse biased, therefore the base current is
Zero. Under these conditions the transistor is said to be in cut off
mode and the output Y is in 1 state.
ii When input A is in 1 state, the base-emitter jn gets forward biased.
Value of resistor Rb and R and adjusted so that in this arrangement a
large collector current flows. In this state the transistor is said to
have gone to saturation. The voltage drop across Rc is almost equal
5v and the output Y is very nearly equal to 0 V corresponding to 0
state of the truth table.
