PRELIMINARY
6.18.57 Transmit Total Collision Counter (TNCL)
GE0 Address: 0x1900010C This register is used to count transmitted total
GE1 Address: 0x1A00010C collision packets.
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:13 RES Reserved. Must be written with zero. Contains zeros when read.
12:0 TNCL Transmit total collision counter. Incremented by the number of collisions
experienced during the transmission of a frame as defined as the simultaneous
presence of signals on the DO and RD circuits (i.e., transmitting and receiving at
the same time). Note, this register does not include collisions that result in an
excessive collision condition).
6.18.58 Transmit Pause Frames Honored Counter (TPFH)
GE0 Address: 0x19000110 This register is used to count honored
GE1 Address: 0x1A000110 transmitted pause frames.
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:12 RES Reserved. Must be written with zero. Contains zeros when read.
11:0 TPFH Transmit pause frames honored counter. Incremented each time a valid pause
MAC control frame is transmitted and honored.
6.18.59 Transmit Drop Frame Counter (TDRP)
GE0 Address: 0x19000114 This register is used to count transmitted drop
GE1 Address: 0x1A000114 frames.
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:12 RES Reserved. Must be written with zero. Contains zeros when read.
11:0 TDRP Transmit drop frame counter. Incremented each time input PFH is asserted.
6.18.60 Transmit Jabber Frame Counter (TJBR)
GE0 Address: 0x19000118 This register is used to count transmitted jabber
GE1 Address: 0x1A000118 frames.
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:12 RES Reserved. Must be written with zero. Contains zeros when read.
11:0 TJBR Transmit jabber frame counter. Incremented for each oversized transmitted frame
with an incorrect FCS value.
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PRELIMINARY
6.18.61 Transmit FCS Error Counter (TFCS)
GE0 Address: 0x1900011C This register is used to count transmitted FCS
GE1 Address: 0x1A00011C errors.
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:12 RES Reserved. Must be written with zero. Contains zeros when read.
11:0 TFCS Transmit FCS error counter. Incremented for every valid sized packet with an
incorrect FCS value.
6.18.62 Transmit Control Frame Counter (TXCF)
GE0 Address: 0x19000120 This register is used to count transmitted
GE1 Address: 0x1A000120 control frames.
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:12 RES Reserved. Must be written with zero. Contains zeros when read.
11:0 TXCF Transmit control frame counter. Incremented for every valid size frame with a
type field signifying a control frame.
6.18.63 Transmit Oversize Frame Counter (TOVR)
GE0 Address: 0x19000124 This register is used to count transmitted
GE1 Address: 0x1A000124000128 oversize frames.
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:12 RES Reserved. Must be written with zero. Contains zeros when read.
11:0 TOVR Transmit oversize frame counter. Incremented for each oversized transmitted
frame with an correct FCS value.
6.18.64 Transmit Undersize Frame Counter (TUND)
GE0 Address: 0x19000128 This register is used to count transmitted
GE1 Address: 0x1A000128 undersize frames.
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:12 RES Reserved. Must be written with zero. Contains zeros when read.
11:0 TUND Transmit undersize frame counter. Incremented for every frame less then 64
bytes, with a correct FCS value.
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PRELIMINARY
6.18.65 Transmit Fragment Counter (TFRG)
GE0 Address: 0x1900012C This register is used to count transmitted
GE1 Address: 0x1A00012C fragments.
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:12 RES Reserved. Must be written with zero. Contains zeros when read.
11:0 TFRG Transmit fragment counter. Incremented for every frame less then 64 bytes, with
an incorrect FCS value.
6.18.66 Carry Register 1 (CAR1)
GE0 Address: 0x19000130 Carry register bits are cleared on carry register
GE1 Address: 0x1A000130 write while the respective bit is asserted.
Access: Read-Only
Reset: 0x0
Bit Bit Name Description
31 C1_64 Carry register 1 TR64 counter carry bit
30 C1_127 Carry register 1 TR127 counter carry bit
29 C1_255 Carry register 1 TR255 counter carry bit
28 C1_511 Carry register 1 TR511 counter carry bit
27 C1_1K Carry register 1 TR1K counter carry bit
26 C1_MAX Carry register 1 TRMAX counter carry bit
25 C1_MGV Carry register 1 TRMGV counter carry bit
24:17 RES Reserved. Must be written with zero. Contains zeros when read.
16 C1_RBY Carry register 1 RBYT counter carry bit
15 C1_RPK Carry register 1 RPKT counter carry bit
14 C1_RFC Carry register 1 RFCS counter carry bit
13 C1_RMC Carry register 1 RMCA counter carry bit
12 C1_RBC Carry register 1 RBCA counter carry bit
11 C1_RXC Carry register 1 RXCF counter carry bit
10 C1_RXP Carry register 1 RXPF counter carry bit
9 C1_RXU Carry register 1 RXUO counter carry bit
8 C1_RAL Carry register 1 RALN counter carry bit
7 C1_RFL Carry register 1 RFLR counter carry bit
6 C1_RCD Carry register 1 RCDE counter carry bit
5 C1_RCS Carry register 1 RCSE counter carry bit
4 C1_RUN Carry register 1 RUND counter carry bit
3 C1_ROV Carry register 1 ROVR counter carry bit
2 C1_RFR Carry register 1 RFRG counter carry bit
1 C1_RJB Carry register 1 RJBR counter carry bit
0 C1_RDR Carry register 1 RDRP counter carry bit
220 • AR9331 802.11n 1x1 2.4 GHz SoC for AP and Router Platforms Atheros Communications, Inc.
220 • December 2010 COMPANY CONFIDENTIAL
PRELIMINARY
6.18.67 Carry Register 2 (CAR2)
GE0 Address: 0x19000134 Carry register bits are cleared on a carry
GE1 Address: 0x1A000134 register write while the respective bit is
Access: Read-Only asserted.
Reset: 0x0
Bit Bit Name Description
31:20 RES Reserved. Must be written with zero. Contains zeros when read.
19 C2_TJB Carry register 2 TJBR counter carry bit
18 C2_TFC Carry register 2 TFCS counter carry bit
17 C2_TCF Carry register 2 TXCF counter carry bit
16 C2_TOV Carry register 2 TOVR counter carry bit
15 C2_TUN Carry register 2 TUND counter carry bit
14 C2_TFG Carry register 2 TFRG counter carry bit
13 C2_TBY Carry register 2 TBYT counter carry bit
12 C2_TPK Carry register 2 TPKT counter carry bit
11 C2_TMC Carry register 2 TMCA counter carry bit
10 C2_TBC Carry register 2 TBCA counter carry bit
9 C2_TPF Carry register 2 TXPF counter carry bit
8 C2_TDF Carry register 2 TDFR counter carry bit
7 C2_TED Carry register 2 TEDF counter carry bit
6 C2_TSC Carry register 2 TSCL counter carry bit
5 C2_TMA Carry register 2 TMCL counter carry bit
4 C2_TLC Carry register 2 TLCL counter carry bit
3 C2_TXC Carry register 2 TXCL counter carry bit
2 C2_TNC Carry register 2 TNCL counter carry bit
1 C2_TPH Carry register 2 TPFH counter carry bit
0 C2_TDP Carry register 2 TDRP counter carry bit
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PRELIMINARY
6.18.68 Carry Mask Register 1 (CAM1)
GE0 Address: 0x19000138 When one of these mask bits is set to zero, the
GE1 Address: 0x1A000138 corresponding interrupt bit is allowed to cause
Access: Read/Write interrupt indications on output CARRY.
Reset: 0x1
Bit Bit NaM1e Description
31 M1_64 Mask register 1 TR64 counter carry bit
30 M1_127 Mask register 1 TR127 counter carry bit
29 M1_255 Mask register 1 TR255 counter carry bit
28 M1_511 Mask register 1 TR511 counter carry bit
27 M1_1K Mask register 1 TR1K counter carry bit
26 M1_MAX Mask register 1 TRMAX counter carry bit
25 M1_MGV Mask register 1 TRMGV counter carry bit
24:17 RES Reserved. Must be written with zero. Contains zeros when read.
16 M1_RBY Mask register 1 RBYT counter carry bit
15 M1_RPK Mask register 1 RPKT counter carry bit
14 M1_RFC Mask register 1 RFCS counter carry bit
13 M1_RMC Mask register 1 RMCA counter carry bit
12 M1_RBC Mask register 1 RBCA counter carry bit
11 M1_RXC Mask register 1 RXCF counter carry bit
10 M1_RXP Mask register 1 RXPF counter carry bit
9 M1_RXU Mask register 1 RXUO counter carry bit
8 M1_RAL Mask register 1 RALN counter carry bit
7 M1_RFL Mask register 1 RFLR counter carry bit
6 M1_RCD Mask register 1 RCDE counter carry bit
5 M1_RCS Mask register 1 RCSE counter carry bit
4 M1_RUN Mask register 1 RUND counter carry bit
3 M1_ROV Mask register 1 ROVR counter carry bit
2 M1_RFR Mask register 1 RFRG counter carry bit
1 M1_RJB Mask register 1 RJBR counter carry bit
0 M1_RDR Mask register 1 RDRP counter carry bit
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