PRELIMINARY
6.18.78 Ethernet Tx FIFO Throughput (ETH_TXFIFO_TH)
GE0 Address: 0x190001A4 This Ethernet register has a 2 KB Tx FIFO. It is
GE1 Address: 0x1A0001A4 use to determine the minimum and maximum
Access: Read/Write levels of the transfer FIFO and correspondingly
Reset: See field description keep the transmit levels within the range to
keep a continuous data transfer flowing.
Bit Bit Name Reset Description
31:26 RES 0x0 Reserved. Must be written with zero. Contains zeros when read.
25:16 TXFIFO_MAXTH 0x1D8 This bit represents the maximum number of double words in the Tx
FIFO, and once this limit is surpassed, this bit should be de-asserted
15:10 RES 0x0 Reserved. Must be written with zero. Contains zeros when read.
9:0 TXFIFO_MINTH 0x160 This bit specifies the minimum number of double words in the Tx FIFO,
and if it is less than this value, this bit needs to be asserted.
6.18.79 Current Tx and Rx FIFO Depth (ETH_XFIFO_DEPTH)
GE0 Address: 0x190001A8
GE1Address: 0x1A0001A8
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:26 RES Reserved
25:16 CURRENT_RX_FIFO_DEPTH Current Rx FIFO depth
15:10 RES Reserved
9:0 CURRENT_TX_FIFO_DEPTH Current Tx FIFO depth
6.18.80 Ethernet Rx FIFO Threshold (ETH_RXFIFO_TH)
GE0 Address: 0x190001AC This Ethernet register has a 2 KB Rx FIFO. It is
GE1 Address: 0x1A0001AC used to determine the minimum and
Access: Read/Write maximum levels of the transfer FIFO and
Reset: See field description correspondingly keep the transmit levels
within the range to keep a continuous data
transfer flowing.
Bit Bit Name Reset Description
31:10 SCRATCHREG_0 0x28 This bit is a pure scratch pad register that can be used by the CPU for any
general purpose.
9:0 RCVFIFO_MINTH 0x0 The minimum number of double words in the Rx FIFO. Once this
number is reached, this bit needs to be asserted.
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PRELIMINARY
6.18.81 Ethernet Free Timer
GE0 Address: 0x190001B8 This register updates the Ethernet descriptors
GE1 Address: 0x1A0001B8 with time stamps
Access: Read/Write
Reset: See field description
Bit Bit Name Reset Description
31 TIMER_UPDATE 0x1 0 Timer update at the AHB_CLK
1 Free timer at the AHB_CLK/4
30:21 SCRATCHREG_1 0x0 The pure general purpose register for use by the CPU
20:0 FREE_TIMER 0x3FFFFF Free timer
6.18.82 DMA Transfer Control for Queue 1 (DMATXCNTRL_Q1)
GE0 Address: 0x190001C0
GE1 Address: 0x1A0001C0
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:1 RES Reserved. Must be written with zero. Contains zeros when read.
0 TX_ENABLE Enables queue 1
6.18.83 Descriptor Address for Queue 1 Tx (DMATXDESCR_Q1)
GE0 Address: 0x190001C4
GE1 Address: 0x1A0001C4
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:2 DESCR_ ADDR The descriptor address to be fetched for queue 1
1:0 RES Reserved. Must be written with zero. Contains zeros when read.
6.18.84 DMA Transfer Control for Queue 2 (DMATXCNTRL_Q2)
GE0 Address: 0x190001C8
GE1 Address: 0x1A0001C8
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:1 RES Reserved. Must be written with zero. Contains zeros when read.
0 TX_ENABLE Enables queue 2
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PRELIMINARY
6.18.85 Descriptor Address for Queue 2 Tx (DMATXDESCR_Q2)
GE0 Address: 0x190001CC
GE1 Address: 0x1A0001CC
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:2 DESCR_ ADDR The descriptor address to be fetched for queue 2
1:0 RES Reserved. Must be written with zero. Contains zeros when read.
6.18.86 DMA Transfer Control for Queue 3 (DMATXCNTRL_Q3)
GE0 Address: 0x190001D0
GE1 Address: 0x1A0001D0 Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:1 RES Reserved. Must be written with zero. Contains zeros when read.
0 TX_ENABLE Enables queue 3
6.18.87 Descriptor Address for Queue 3 Tx (DMATXDESCR_Q3)
GE0 Address: 0x190001D4
GE1 Address: 0x1A0001D4
Access: Read/Write
Reset: 0x0
Bit Bit Name Description
31:2 DESCR_ ADDR The descriptor address to be fetched for queue 3
1:0 RES Reserved. Must be written with zero. Contains zeros when read.
6.18.88 DMA Transfer Arbitration Configuration (DMATXARBCFG)
GE0 Address: 0x190001D8 This register is used to select the type of
GE1 Address: 0x1A0001D8 arbitration used for the QoS feature and the
Access: Read/Write weight to be assigned to a particular queue.
Reset: See field description Note that a weight of zero is not permitted and
causes the hardware to misbehave.
Bit Bit Name Reset Description
31:26 WGT3 0x1 The weight for Queue 3, if WRR has been selected
25:20 WGT2 0x2 The weight for Queue 2, if WRR has been selected
19:14 WGT1 0x4 The weight for Queue 1, if WRR has been selected
13:8 WGT0 0x8 The weight for Queue 0, if WRR has been selected
7:1 RES 0x0 Reserved. Must be written with zero. Contains zeros when read.
0 RRMODE 0x4 Round robin mode
0 Simple priority (Q0 highest priority)
1 Weighted round robin (WRR)
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PRELIMINARY
6.19 USB Controller Registers
Table 6-20 summarizes the USB controller
registers and the modes they support.
Table 6-20. USB Controller Registers [1]
Offset Access Name Description DEV SPH Page
Identification Registers
Declare the slave interface presence
0x1B000000 RO ID Identification X X page 233
0x1B000004 RO HWGENERAL General Hardware Parameters X X page 233
0x1B000008 RO HWHOST Host Hardware Parameters X page 233
0x1B00000C RO HWDEVICE Device Hardware Parameters X page 234
0x1B000010 RO HWTXBUF Tx Buffer Hardware Parameters X X page 234
0x1B000014 RO HWRXBUF Rx Buffer Hardware Parameters X X page 234
Device/Host Timer Registers
Measure time-related activities
0x1B000080 RW GPTIMER0LD General Purpose Timer 0 Load X X page 234
0x1B000084 Varies GPTIMER0CTRL General Purpose Timer 0 Control X X page 235
0x1B000088 RW GPTIMER1LD General Purpose Timer 1 Load X X page 235
0x1B00008C RW GPTIMER1CTRL General Purpose Timer 1 Control X X page 236
Device/Host Capability Registers
Specify the software limits, restrictions, and capabilities of the host/device controller implementation
0x1B000100 RO CAPLENGTH Capability Register Length X X page 236
0x1B000102 RO HCIVERSION Host Interface Version Number X X page 236
0x1B000104 RO HCSPARAMS Host Control Structural Parameters X X page 237
0x1B000108 RO HCCPARAMS Host Control Capability Parameters X page 238
0x1B000120 RO DCIVERSION Device Interface Version Number X page 238
0x1B000122 RO DCCPARAMS Device Control Capability X page 239
Parameters
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PRELIMINARY
Table 6-20. USB Controller Registers (continued)[1]
Offset Access Name Description DEV SPH Page
Device/Host Operational Registers
0x1B000140 Varies USBCMD USB Command X X page 239
0x1B000144 Varies USBSTS USB Status X X page 242
0x1B000148 RW USBINTR USB Interrupt Enable X X page 244
0x1B00014C Varies FRINDEX USB Frame Index X X page 246
0x1B000154 RW PERIODICLISTBASE Frame List Base Address X page 247
— RW DEVICEADDR USB Device Address X page 247
0x1B000158 RW ASYNCLISTADDR Next Asynchronous List Address X page 247
— RW ENDPOINTLIST_ Address at Endpoint List in Memory X page 248
ADDR
0x1B00015C RW TTCTRL TT Status and Control X page 248
0x1B000160 RW BURSTSIZE Programmable Burst Size X X page 248
0x1B000164 RW TXFILLTUNING Host Tx Pre-Buffer Packet Tuning X page 249
0x1B000174 RWC ENDPTNAK Endpoint NAK X page 250
0x1B00017C RW ENDPTNAKEN Endpoint NAK Enable X page 250
0x1B000180 RO CONFIGFLAG Configured Flag X page 251
0x1B000184 Varies PORTSC0 Port/Status Control X X page 251
0x1B0001A8 RW USBMODE USB Mode X X page 255
0x1B0001AC RWC ENDPTSETUPSTAT Endpoint Setup Status X page 256
0x1B0001B0 RWC ENDPTPRIME Endpoint Initialization X page 257
0x1B0001B4 WC ENDPTFLUSH Endpoint De-Initialization X page 257
0x1B0001B8 RO ENDPTSTATUS Endpoint Status X page 258
0x1B0001BC RWC ENDPTCOMPLETE Endpoint Complete X page 258
0x1B0001C0 RW ENDPTCTRL0 Endpoint Control 0 X page 259
0x1B0001C4 RW ENDPTCTRL1 Endpoint Control 1 X page 260
0x1B0001C8 RW ENDPTCTRL2 Endpoint Control 2 X page 260
0x1B0001CC RW ENDPTCTRL3 Endpoint Control 3 X page 260
0x1B0001D0 RW ENDPTCTRL4 Endpoint Control 4 X page 260
0x1B0001D4 RW ENDPTCTRL5 Endpoint Control 5 X page 260
[1]DEV = Device Mode
SPH = Single-Port Host
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PRELIMINARY
6.19.1 Identification (ID)
Offset: 0x1B000000 Provides a simple way to determine whether
Access: Read-Only the system provides the USB-HS USB 2.0 core
Reset Value: 0x42FA05 and identifies the USB-HS USB 2.0 core and
revision number.
Bit Name Description
31:24 RES Reserved. Must be set to 0.
23:16 REVISION[7:0] Core revision number
15:14 RES Reserved. Must be set to 1.
13:8 NID[5:0] Complement version of ID bits [5:0]
7:6 RES Reserved. Must be set to 0.
5:0 ID Configuration number; Set to 0x05
Indicates that the peripheral is the USB-HS USB 2.0 core.
6.19.2 General Hardware Parameters (HWGENERAL)
Offset: 0x1B000004
Access: Read-Only
Reset Value: 0x22
Bit Name Description
31:10 RES Reserved. Must be set to 0.
9 SM VUSB_HS_PHY_SERIAL
8:6 PHYM VUSB_HS_PHY_TYPE
5:4 PHYW VUSB_HS_PHY16_8
3 RES Reserved
2:1 CLKC VUSB_HS_CLOCK_CONFIGURATION
0 RT VUSB_HS_RESET_TYPE
6.19.3 Host Hardware Parameters (HWHOST)
Offset: 0x1B000008
Access: Read-Only
Reset Value: 0x1002001
Bit Name Description
31:24 TTPER VUSB_HS_TT_PERIODIC_CONTEXTS
23:16 TTASY VUSB_HS_TT_ASYNC_CONTEXTS
15:4 RES Reserved. Must be set to 0.
3:1 NPORT VUSB_HS_NUM_PORT – 1
0 HC VUSB_HS_HOST
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