Declaration:

We, the undersigned students of B. Tech. of Computer Science Engineering (CSE)

Department hereby declare that we own the full responsibility for the information, results etc.
provided in this PROJECT titled (Design a circuit using 8x1multiplexer.G(A,B,C,D) is iff
the chairs on the ends are both empty) submitted to Siksha ‘O’ Anusandhan Deemed to
be University, Bhubaneswar for the partial fulfillment of the subject Digital Logic Design
(EET 1211). We have taken care in all respect to honor the intellectual property right and
have acknowledged the contribution of others for using them in academic purpose and further
declare that in case of any violation of intellectual property right or copyright we, as the
candidate(s), will be fully responsible for the same.

NAME : SUBHANGI PANDA. NAME : PRIYANSU PANDA.

REG.NO. : 2341016101. REG.NO. : 2341016084.

NAME : SMRITI PANDA. NAME:SOHAM PARMANIK.

REG.NO. : 2341016095. REG.NO. : 231016167.

DATE : 13/12/2024.

PLACE : BHUBANESWAR.
Abstract:
This project focuses on designing a circuit for a specific logic function using an 8x1
multiplexer. The input variables and represent the states of chairs placed in a row, where 1
denotes an occupied chair and 0 denotes an empty chair. The function is defined such that
it outputs 1 if and only if both chairs on the ends (A and D) are empty, irrespective of the
states of the middle chairs and .

Key Contributions:

1. Truth Table Analysis: The truth table for was derived to determine the relationship

between the input variables and the output.

2. Logic Simplification: Boolean algebra was used to simplify the function, resulting in the
expression .

3. Multiplexer Implementation: An 8x1 multiplexer was configured to implement the logic

function using and as select lines and appropriately assigning and constant logic values
(0 or 1) to the data inputs.

This work demonstrates how to efficiently utilize multiplexer circuits to design custom
logic functions, offering insights into digital design techniques and optimization strategies.
 Contents:
Serial No. Title of the Content: Page No.:

1. Introduction

2. Problem Statement

3. Methodology

4. Implementation

5. Results and interpretation

6. Conclusion

7. References

8. Appendices
Introduction:
In this problem, we analyze a logical arrangement of four chairs, represented as A, B, C, and
D, placed in a row. Each chair can either be occupied (1) or empty (0). Our goal is to design a
circuit for the logic function G(A, B, C, D) , which evaluates to 1 if and only if the chairs at the
ends of the row (A and D) are both empty (0).

To achieve this, we utilize an 8x1 multiplexer, leveraging its functionality to represent and
implement the given logic function. The 8x1 multiplexer simplifies the circuit design by using
combinations of control signals (inputs) to select the appropriate output based on the
desired conditions.

The logic function G(A, B, C, D) is evaluated based on the

following criteria:

• G(A, B, C, D) = 1 if A = 0 and D = 0 , regardless of B and C .

• G(A, B, C, D) = 0 otherwise.

This introduction lays the foundation for understanding the problem and highlights the
role of the 8x1 multiplexer in simplifying the implementation of the logic function.
PROBLEM STATEMENT:
To design the logic circuit for using an 8x1 multiplexer, let’s break the problem into clear steps:

Problem Recap:
 Inputs:
• represent the chairs in a row.

• is the leftmost chair, is the rightmost chair.

 Logic Function:
• if both and (chairs at the ends are empty).

• otherwise.

 Truth Table:
The truth table for G(A,B,C,D):

A: B: C: D: G(A,B,C,D):
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

 Logic Function Derivation:

From the truth table, observe that G(A,B,C,D) depends only on A and D :

• G(A,B,C,D) when A=0 and D=0 .

• So the logic function simplifies to:

G(A,B,C,D) = A’.D’.

 Implementing Using 8x1 Multiplexer:

An 8x1 multiplexer has:

• 3 Select Lines (S2, S1, S0): These will determine the input combinations.

• Inputs (I0, I1, …, I7): Represent the outputs based on select line combinations.

Here’s the mapping for the implementation:

1. Assign B and C as don’t care variables, so they are ignored.

2. Use A and D as the select inputs:

• Let S2 = A1 , S1=D1 and use any constant S0 for simplification.

3. Define the multiplexer inputs ( I0, I1, …, I7) based on G(A,B,C,D):

• I0 : A = 0, D = 0 : 1.

• I1 : A = 0, D = 1 : 0.

• I2 : A = 1, D = 0 : 0.

• I3 : A = 1, D = 1 : 0.

• Remaining inputs can also be since and are ignored.

Thus, the multiplexer inputs are:

I0 = 1, I1 = 0, I2 = 0, I3 = 0, I4 = 0, I5 = 0, I6 = 0, I7 = 0.

 Conclusion:
• Connect S2 = A1 , S1 = D1 and any constant S0 (e.g., tie to 0 or ground).

• Use the multiplexer inputs I0, I1, …, I7 as derived above.

• This configuration will implement G(A,B,C,D) = A’.D’.

METHODOLOGY:
To design the circuit for G(A, B, C, D) using an 8x1 multiplexer, we follow these steps:

 Step 1: Understand the Problem

• The inputs A, B, C, D represent the occupancy of four chairs:

• A : Leftmost chair.

• D : Rightmost chair.

• B, C : Middle chairs (don’t affect the condition directly).

• Logic Function:

• G(A, B, C, D) = 1 if both A = 0 and D = 0 .

• G(A, B, C, D) = 0 otherwise.

 Step 2: Simplify the Logic Expression

From the problem:

• G(A, B, C, D) depends only on A and D , while B and C are irrelevant.

• Truth Table for G(A, D) :

A B G(A, D)

0 0 1

0 1 0

1 0 0

1 1 0

• Logic Expression:

G(A, B, C, D) = A’.D’.
 Step 3: Configure the 8x1 Multiplexer
An 8x1 multiplexer has:

1. 3 Select Lines (S2, S1, S0): These determine which input is passed to the output.

2. 8 Inputs (I0, I1,.....,I7 ): Each corresponds to a specific combination of the select lines.

We use the truth table of G(A, B, C, D) to determine the inputs ( I0,...., I7 ) for the multiplexer.

 Step 4: Assign Select Lines

• Use two variables ( A and D ) as the primary selectors.

• Assign:

S2 = A

• S1 = D

• Use S0 as a constant (e.g., S0 = 01 , or connect to ground).

 Step 5: Determine Multiplexer Inputs ( I0, I1,...., I7 )

For each possible value of S2, S1, S0 (i.e., A, D, and a constant), assign the inputs I_0 to I_7 based
on the simplified truth table.

Select Lines : S2(A) : S1(D) : OUTPUT G : Multiplexer Input ( I ):

000 0 0 1 I0 = 1

001 0 1 0 I1 = 0

010 1 0 0 I2 = 0
011 1 1 0 I3 = 0

100 Irreleva Irreleva 0 I4 = 0

nt nt

101 Irreleva Irreleva 0 I5 = 0

nt nt

110 Irreleva Irreleva 0 I6 = 0

nt nt

111 Irreleva Irreleva 0 I7 = 0

nt nt
 Step 6: Implement the Circuit :
1. Connect:

• A and D to S2 and S1 , respectively.

• Use a constant (e.g., ground) for S0 .

2. Set the multiplexer inputs:

• I0 = 1 , I1 = 0 , I2 = 0 , I3 = 0 , I4 = 0 , I5 = 0 , I6 = 0 , I7 = 0 .

4. The output of the multiplexer directly represents G(A, B, C, D) = A’.D’.

 Step 7: Verify the Circuit:

• Test for all combinations of A and D :

• If A = 0 and D = 0 , G = 1 .

• Otherwise, G = 0 .

This completes the design of the circuit using an 8x1 multiplexer!

IMPLEMENTATION:
Logic Diagram of the 8*1 Multiplexer using different logic gates:

The VHDL code is as follows:

RESULTS AND INTERPRETATION:
We get the following timing diagrams -
CONCLUSION:

We have successfully designed a combinational circuit using an 8-to-1 multiplexer for

the logic function G(A,B,C,D) which is 1 if and only if the chairs on the ends (A and
D) are both empty (0).

Key Steps:

1. Truth Table Construction:

o We created a truth table to understand the relationship between the
inputs A,B,C,D and the output G.
2. Function Definition:
o The function G is defined as G=1 when A=0 & D = 0.
3. Multiplexer Configuration:
o We used an 8-to-1 multiplexer and assigned the inputs A,B,C as select
lines.
o We configured the multiplexer data inputs based on the truth table to
achieve the desired output.
Final Logic:

The final circuit ensures that the output G is 1 if and only if both ends A and D are 0
(empty), otherwise, G is 0.

This elegant use of a multiplexer simplifies the design process and demonstrates the
power of combinational logic in creating specific functional requirements.

APPENDICES:
REFERENCES:
 S.M.Turkane, N.V.Ambedkar, S.V.Kaname, T.V.Kharde, “Performance Analysis of
different MUX for FPGA”, IJARIIE-ISSN(O)-2395-4396, Vol-2 Issue-3 2016
http://ijariie.com/AdminUploadPdf/Performance_A
nalysis_of_different_MUX_for_FPGA_ijariie2070.pdf
 Multiplexing in Computer Networks
https://www.tutorialspoint.com/data_communication_computer_network/
physical_layer_multiplexing.htm#:~:text=Multiplexing%20is%20a%20techniqu e
%20by, then%20shared%20by%20different%20streams.
 Verilog Design Tutorial
 Digital design by M. Morris Mano, Pearson publications.
 www.google.com
 www.circuitrydesign.com
 www.indiastudychannel.com
THANK
YOU