TMS370

PCB Design Guidelines for Reduced EMI

PCB Design Guidelines for Reduced EMI,

Including cMCU370-Specific Guidelines

Robert DeMoor
Microcontroller Applications
Texas Instruments, Inc.
12203 Southwest Freeway, MS 728
Stafford, TX 77477

Version 1.60
8/7/95

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Important Notice

Texas Instruments Incorporated (TI) assumes no liability for applications assistance, customer
product design, software performance, or infringement of patents or services described herein.
Nor does TI warrant or represent that any license, either express or implied, is granted under any
patent right, copyright, mask work right, or other intellectual property right of TI covering or
relating to any combination, machine, or process in which such semiconductor products or
services might be or are used. TI reserves the right to make improvements to this document.

The information and/or drawings set forth in this document and all rights in and to inventions
disclosed herein and patents which might be granted thereon disclosing or employing the
materials, methods, techniques, or apparatus described herein are the exclusive property of
Texas Instruments. No disclosure of information or drawings shall be made to any other person
or organization without the prior consent of Texas Instruments.

Copyright © 1994-1995, Texas Instruments Incorporated

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Contents

1.0) Overview

2.0) Background and Theory

2.1) EMI sources, paths, and receivers
2.2) Loops and Antennas
2.2.1) Loop Areas
2.2.2) The Loop: Current Flow Path
2.3) Differential Mode and Common Mode Radiation
2.3.1) Differential-mode Noise
2.3.2) Common-mode Noise
2.4) Coupling
2.5) High-frequency Characteristics of Passive Devices
2.6) Reciprocity of Emissions and Susceptibility

3.0) PCB Design Implementation

3.1) Floor-Plan PCB First
3.1.1) Board Zoning
3.1.2) Space for Ground Structures
3.1.3) Minimize Routing Distances
3.1.4) Short routes for High-frequency Signals
3.2) Grounding
3.2.1) Digital: Grid the Ground
3.2.2) Analog Ground
3.2.3) Noisy Ground
3.2.4) Low Impedance Ground Node
3.2.5) Ground Width
3.2.6) Connector Grounds
3.2.7) Power Routing
3.2.8) Clock Lines
3.2.9) Multi-layer Boards
3.3) Bypassing
3.3.1) Power Bypassing
3.3.2) Signal Bypassing
3.3.3) Connector Bypassing

4.0) Summary
4.1) Priority of Guidelines

5.0) PCB Layout Example

Revision History

1.00 (9/26/94) Preliminary release.

1.50 (6/28/95) Minor revisions to multiple sections. Added use of ferrites to section 3.2.7.
1.60 (8/7/95) Revised graphics in Section 5.0.

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 TMS370
PCB Design Guidelines for Reduced EMI

PCB Design Guidelines for Reduced EMI,

Including cMCU370-Specific Guidelines

1.0) Overview
Electromagnetic interference (EMI) often seems like a mysterious phenomenon. EMI can be
difficult to control, and even the results of EMI testing can vary from day to day and from test
facility to test facility. At times, the act of controlling EMI has been called "black magic" or
"voodoo." However, EMI has been researched for many years, and guidelines have been
established that can improve the electromagnetic compatibility (EMC) of a system to which they
are applied.

Designing for low EMI from the start of a project results in much easier and less expensive
solutions than attempting to fix (or “Band-Aid,”) EMI problems after a design has reached the
testing phase of development. Consequently, following a few guidelines for printed circuit board
(PCB) design at the beginning of a project can help to minimize the system’s EMI while adding
little or no cost to the system.

2.0) Background and Theory

Knowledge and understanding of a few fundamental concepts can be exercised toward the
design of an electronic system in order to improve electromagnetic compatibility (EMC)
performance.

This document concentrates on methods for reducing radiated EMI emissions. For Texas
Instruments’ microcontroller (MCU) devices with an integrated phase-locked loop oscillator (PLL)
module, the PLL-Based Clock Module Application Note, also available from Texas Instruments
(TI), should be used for guidelines concerning PCB layout and component recommendations for
optimum noise immunity for the PLL circuitry.

2.1) EMI sources, paths, and receivers

EMI requires a source, a path, and a receiver. In today’s electronics, clocked CMOS integrated
circuits often supply the source, and the printed circuit board (PCB), as well as its associated
cabling and wire harness, acts as the conductive and radiating part of the path, otherwise called
the antenna.

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EMI
Sources Paths Receivers

Oscillators Radiated IC's, Ckt boards

Digital IC's Conducted Radio tuners
Switching Cellular Phones
regulators Antennas
Resonant (Screen room)
components
ESD

Figure 1: EMI Sources, Paths, and Receivers

The receiver can be a sensitive electronic module, such as a radio, or it can be an antenna
specifically designed to receive electromagnetic emissions in a test environment. Depending on
its design and layout, a PCB can either amplify or suppress the emissions of an IC.

2.2) Loops and Antennas

The amount of radiation produced by an electronic system is to a large extent proportional to the
efficiency of its radiating antennas. Antennas on a PCB include all traces, components,
component leads, connectors, and wiring harnesses. In other words, any conductive element on
or connected to a PCB can act as an antenna. The challenge is to reduce the efficiency of these
antennas. If a radio station has a source broadcasting power of 100 megawatts, but has no
antenna to broadcast from, nobody will hear it. In much the same way, a well-designed PCB can
minimize the amount of radiation that is transmitted from its sources.

2.2.1) Loop Areas

Loop areas can be the most serious EMI threat. A loop can transmit as well as receive
electromagnetic energy. Thus, the loop areas associated with a PCB directly affect the
emissions and immunity of the system. A PCB can have many loops, and each loop contributes
to the radiated emissions from the system. As the size of a loop increases (up to 1/4 wavelength
of the signal), so does the efficiency of the loop as a radiator. Thus, to minimize radiated EMI,
loops must be made as small as possible.

2.2.2) The Loop: Current Flow Path

Current must flow in a loop. If the loop is broken, the same current will no longer flow. Current
flowing through a loop generates electric and magnetic fields, with field strength proportional to
loop size and to the square of the frequency for loops that are smaller than 1/4 of the wavelength
of the frequency of interest (Ott, 1988, p. 299). Loops also receive emissions from other devices
and thus allow an increased susceptibility of the circuit to disturbances.

Current must return to the point from which it originated via the path of least impedance. The
path of least impedance, however, is usually not the path of least resistance at high frequencies.
In Figure 2, Paths A and B represent two different possible current return paths, either within a

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ground plane or on a ground grid network. Path A is the lowest resistance current return path for
the output signal from the MCU since its path is the shortest. However, at frequencies over
about 10 kHz, the inductive reactance of a wire is larger than the resistance of the wire.
Therefore, any signal faster than about 10 kHz will return through Path B since this path is less
inductive than Path A. On a PCB, the return current may not have a choice of which path to take.
If Path B was removed, then a very large signal/return loop would be created. This would
undesirably provide a more efficient radiating (and receiving) antenna for high-frequency EMI
than if Path B was there. Loops of this nature can and must be avoided.

Loop Area # 2
OUTPUT
Signal OUTPUT
Signal
uC uC
GND GND

Loop Area # 1
A A B

GND GND
INPUT INPUT

A = Low-frequency B = High-frequency
signal-return path signal-return path

Loop Area #1 = loop of Loop Area #2 = loop of

least resistance least impedance at
high-frequency
(Assumes conductor B
is present)

Figure 2: Paths of least impedance VS. paths of least resistance

Harmonics from a microcontroller’s system clocks tend to couple onto the device’s inputs and
outputs. Then, the coupled high-frequency EMI uses the antennas provided by the routing of the
I/O and its return path in order to radiate. Since system clocks usually operate faster than 1
MHz, system clock noise and harmonics will take the path of least impedance (Path B).

Every signal has a signal return path associated with it. Most often, this signal return path is
called "ground." The term, "ground," however, is a misnomer. A true ground is a node at a
constant potential through which no current flows under normal conditions, like the safety ground
connection on a computer chassis. If current flows through ground, then two points on the
ground will not be at the same potential due to the resistance of the conductor. If "ground" is no
longer at a constant voltage, then it is more accurately called a "current return" path. Thus, the
loop area associated with a signal and its return is the loop between the signal and its lowest-
impedance ground path. This area must be carefully controlled.

PCB traces carrying high frequencies, large voltage swings, or large amounts of current are the
most serious EMI offenders. In microcontrollers with a divide-by-2 clock module, the oscillator
supplies the highest frequency content of the device. For devices using 32768 Hz PLL-based
clocking, the oscillator is not the most serious radiated EMI threat. For these devices, in which
the primary emissions source (high-frequency oscillator) has been removed, the system clock
(SYSCLK) generates the highest frequency content. The external VCCD to VSSD path carries
the largest amount of radiation energy in such a system. Proper decoupling is necessary to keep
the EMI close to the source and off of the other PCB traces (antennas), as will be discussed in

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section 3.3. Nevertheless, every pin on a MCU is a high frequency source if SYSCLK is greater
than 1 MHz. The SYSCLK fundamental and its harmonics are coupled to the I/Os and can
radiate throughout the PCB. Consequently, care must be used to minimize the loop areas
associated with all signals and returns. The most attention should be paid to power, clocks,
connectors, and fast switching signals, as will be explained in section 3.3.

Since system clock harmonics are difficult to control, it is desirable to run a microcontroller as
slow as possible while still maintaining sufficient throughput for all of the required system
operations. Harmonics of a 1 MHz system clock are less severe than harmonics of an 8 MHz
system clock.

2.3) Differential Mode and Common Mode Radiation

Differential mode and common mode noise provide the means for radiation to spread throughout
a PCB, onto connecting cables, and out into the environment.

2.3.1) Differential-mode Noise

Differential-mode noise is created by a signal traveling to a load and the return current traveling
back to the source. The currents in the signal and the return are traveling in "different," or
opposite, directions.

Radiation

Signal
Loop
Load
Source Area
Return

Figure 3: Differential-mode Radiation

Differential-mode noise increases with increasing loop area of the signal path. Thus, controlling
loop areas significantly helps to control differential mode emissions.

2.3.2) Common-mode Noise

Common mode noise is the result of unwanted voltage drops within a circuit which are usually
the result of ground noise. Typically, the predominant source of common-mode noise is the
cabling attached to a PCB. These cables look like monopole antennas in the EMI world. In fact,
they look like capacitor-plate monopole antennas, having a relatively uniform current distribution
along their length (Ott 1988, p. 313). The cables radiate electric fields and are driven by the
noise on the PCB's ground system.

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I/O Cable
I/O

VN I CM

Figure 4: Common-mode Radiation

Common mode noise can be controlled by lowering the source potential, which usually is that of
the ground system. Thus, gridding the ground (discussed in section 3.2) is also an effective
measure against common mode noise. Additional measures include placing common-mode
impedance (ferrites/chokes) in series with cabling attached to the PCB and shunting the noise
current to ground with bypass capacitors (See section 3.2.6).

2.4) Coupling
Coupling provides the path for a source to radiate to a receptor. Both differential-mode noise
and common-mode noise are forms of coupling. Another concern, however, is the occurrence of
hidden coupling effects. One signal can couple noise onto another signal which may be routed
over a long distance. Power, oscillator (for non-PLL based devices), and clock signals carry
particularly potent supplies of radiation that can be coupled into nearby I/Os. These I/Os can
then carry the noise throughout the circuit, as illustrated in the following figure. Once this
happens, the loop area associated with the coupled noise can grow enormously. In the following
figure, the “coupling effect” capacitor is not part of the design schematic, but represents an
actual path of high-frequency noise between the OSCOUT signal and the I/O. The capacitive
coupling represented in the figure is caused by the close proximity of the OSCOUT and I/O PCB
trace routes.

I/O
OSCOUT Coupling effect Load
OSCIN
XTAL
VSSD

Heavy lines indicate path (and loop area) of noise coupled onto I/O.

Figure 5: Oscillator coupling onto I/O signal

When a Divide-by-two Clock Oscillator Module is used on a device, the oscillator contains the
highest frequency of the MCU and can be the worst EMI threat of coupling noise onto nearby
I/Os. If a 32768 Hz PLL Clock Module is used, then the reverse case is true: noise from the
I/Os can challenge the immunity of the PLL circuitry and its ability to maintain phase-lock.
Additionally, if the CLKOUT pin is used to supply ECLK or SYSCLK to other circuitry, that signal
can supply potent radiation and coupling to other signals. The solution, however, is relatively
simple: keep oscillator, power, and clock signal loops small, and avoid running I/Os next to those
noisy sources, especially for long distances.

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2.5) High-frequency Characteristics of Passive Devices

A fallacy of PCB design is that the location of components does not matter as long as they are
connected according to the schematic. Unfortunately, circuit elements are not always what they
seem to be. For instance, at high frequencies, a capacitor becomes more inductive than
capacitive due to the inductance of the leads and the PCB trace. The high-frequency schematic
of a capacitor and a PCB trace is an RLC circuit. When noise is introduced into that circuit, it
can resonate. In fact, a capacitor intended to decouple noise can actually become self-resonant
and radiate noise if it is not placed close to the noise source. The absence of a low-impedance
ground (signal return) path will cause the same effect. A low-impedance ground path means a
path with minimal loop area between itself and the signal since trace inductance dominates trace
resistance at high frequencies. The following figure illustrates the high-frequency characteristics
of some common passive circuit elements.

Impedance VS Frequency
Low-Frequency High-Frequency Characteristics

Resistor Z
F

Capacitor
Z
F Ideal
Real
Inductor Z
F

or
Z
Wire (PCB
trace) F

or

Figure 6: Hidden schematic effects of common passive circuit elements (EDN,

p.3)

The pitfalls of the high-frequency schematic can be avoided with careful attention to the
placement of passive circuit elements.

2.6) Reciprocity of Emissions and Susceptibility

Generally, PCB design guidelines which reduce EMI emissions also reduce susceptibility to
outside sources of EMI. If the antennas (i.e., PCB traces and wiring harnesses) of a system are
reduced in radiating efficiency, they are also less efficient at receiving interference from other
sources.

However, this reciprocity applies only to the antennas and not to the source/sink capabilities of
the pins connected to the antennas. Consequently, the signals that are the worst emitters are
usually not the most susceptible signals. For instance, clock output signals and high-frequency
oscillators are some of the worst EMI producers. However, reset and control signals (and low-
frequency PLL oscillators) can cause the most damage when corrupted by interference. These
signals should get high priority for EMC when routed on a PCB.

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3.0) PCB Design Implementation

The implementation of PCB design guidelines to circuit board layout is critical for achieving
electromagnetic compatibility (EMC). Furthermore, it is most cost-effective to design a PCB for
EMC at the beginning of the design cycle. Once a PCB has been designed, changes to improve
EMC become more difficult and costly. However, there is little or no cost involved with
implementing PCB design guidelines for reduced EMI at the beginning of the design cycle.

The three most important aspects of PCB design are floor-planning, grounding, and bypassing,
as will be discussed in the following sections. The PLL-Based Clock Module Application Note
should also be used for guidelines concerning PCB layout and components recommended for
optimum noise immunity for the PLL circuitry.

3.1) Floor-Plan PCB First

Floor-planning a PCB is the first step toward designing for EMC. Floor-planning consists of
creating zones on the PCB for analog, digital, and noisy components and providing proper space
for grounding. Also, devices should be arranged to minimize routing distances of EMI-critical
signals, such as clocks, power, cabling, and control signals.

3.1.1) Board Zoning

Board zoning allows the grounding structures to be optimized for different types of circuitry. For
instance, digital circuits should be grouped together, and analog circuits should be grouped in
another location. This configuration will reduce coupling of digital noise onto sensitive analog
circuitry. Noisy components, like relays, motors, and high-current consumption-devices, should
be separated from both digital and analog circuitry.

Analog Noisy

uC

Digital

Figure 7: PCB Zoning

3.1.2) Space for Ground Structures

An important aspect of board zoning is to allow space for proper grounding. Space for grounding
should be provided before the placement of IC's and components is finalized. Grounding is an
extremely important facet of PCB design, but its importance is sometimes overlooked.

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3.1.3) Minimize Routing Distances

The placement locations of IC’s on the PCB should minimize routing distances between IC’s and
other components.

3.1.4) Short Routes for High-frequency Signals

IC’s and components producing and/or receiving fast signals (i.e., CLKOUT or an SPICLK of 50+
KHz) should be placed near each other to minimize routing distances associated with these
signals, which tend to generate EMI. Also, a low-impedance (minimal loop area) signal return
(ground) should be provided for fast signals. Moreover, routing ground on both sides of a high-
frequency signal serves to provide some shielding for other nearby signals.

3.2) Grounding
Along with board zoning and IC placement, proper grounding is of fundamental importance to
achieving electromagnetic compatibility. Since a "ground" is really a current return path in most
cases, the goal of grounding is to provide the lowest impedance current return path possible
without generating additional noise. A ground plane will accomplish this task for all high-
frequency noise and signals since the return current for the high frequencies will follow a path
directly under the signal and back to the source. While a ground plane is ideal for minimizing
loop area and impedance, it will not always solve capacitive or inductive coupling problems.

A ground grid for digital circuitry can provide low-impedance signal return paths for high-
frequency noise on a two-layer board and does not require the additional cost of a ground plane,
which usually requires at least a four-layer PCB. For analog circuitry, a single-point grounding
scheme is often better in order to avoid the presence of ground loops. Single-point grounding is
also preferred for noisy or high-power circuitry.

To protect sensitive analog circuitry from digital noise and to protect both analog and digital
circuitry from even noisier components, such as relays and motors, the analog, digital, and noisy
parts of a system should be separated from each other and connected only at a low-impedance
ground node.

In a mixed-signal environment, the divisions between analog and digital ground may seem
unclear. However, the analog sections of a mixed-signal IC (i.e., ADC, Gauge Drivers) should
be provided with an analog grounding scheme, and digital sections of the same IC (i.e., CMOS
digital I/O, Power), including its signals and routing, should be provided with a digital grounding
scheme.

3.2.1) Digital: Grid the Ground

Ideally, each signal should be routed next to a ground (signal return). Since this is not usually
possible on a 2-layer board, gridding the ground is the next best alternative. A four-layer PCB
often includes a ground plane which provides a low-impedance signal return path for each signal,
as will be discussed in Section 3.2.9. On a two-layer board, a ground grid provides a low-
impedance signal return path that resembles that of a four-layer board. Thus, digital ground
should be in the form of a grid on a two layer board in order to keep loop areas small and thus to
minimize the impedance of the ground structure. Following is an example of what a ground grid
on a 2-layer PCB can look like.

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Top-side Copper
Bottom-side Copper
Via

Figure 8: Ground Grid

A ground grid can be created by running ground lines horizontally on one side of the PCB and
vertically on the other side. Where the lines cross, they should be tied together with vias (feed-
through connections) to form a grid. The size of the grid should be kept small, preferably no
larger than 1 square inch, and smaller grids are better. Signals can then be routed between the
ground lines, horizontally on one side, and vertically on the other side through a via. It is usually
more effective to lay down the ground grid before routing signals. Otherwise, space for a ground
grid rarely is provided.

With this technique, signals can still be routed to any area on the board, and each signal is never
more than one half inch from a current return path.

Additionally, a localized VSSD plane can be placed under the microcontroller to provide
shielding.

The significance of a ground grid should not be under-emphasized. To this end, a few quotes
from respected EMC experts have been included:

• “The ground system is the foundation of a digital logic printed wiring board. Therefore all
digital printed wiring boards must have either a ground plane or a ground grid” [Ott, p. 285].
• “It is important to put the ground grid on the board first, before locating the signal paths” [Ott,
p. 284].
• “Critical traces need a return path less than 0.1” away” [Van Doren, p. 10-6].
• “With regard to noise control, the single most important consideration in the layout of a
digital logic system is the minimization of the ground inductance. Ground inductance in
digital systems can be minimize by using a ground plane or ground grid” [Ott, p. 296].
• “An effective and well-designed ground grid is one of the most important aspects in the ability
of the product to meet the regulatory limits and avoid functional problems” [Paul, p. 731].
• “...there are data that indicate a correlation between reduced ground drop on a PCB (high-
frequency voltage differences between two points on the ground conductor) and a reduction
in the radiated emissions of that PCB” [Paul, p. 731].
• “The design of an effective ground grid on a PCB is a critical aspect to the regulatory
compliance of the PCB and its host system” [Paul, p. 731].

3.2.2) Analog Ground

It is important to distinguish between analog and digital grounds. Digital grounds should be
designed to return high frequencies through a low impedance path, and analog grounds should

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normally be designed to return low frequency current or DC to its origin through a low-resistance
path.

Parallel or series ground connections provide the cleanest current return paths for analog
signals. Parallel ground connections are best, but this scheme is cumbersome to design on a
PCB. Series ground connections are less desirable, but easier to design. Thus, a parallel
connection scheme should be used for the most sensitive analog signals, and series grounds can
be used for less sensitive analog circuitry. The following figure illustrates series and parallel
ground schemes.

VSSA VSSA
R1
R2
R3

R1 R2 R3

uC uC

VSSA VSSA

A A

Parallel Connection Scheme

Series Connection Scheme

Figure 9: Series and Parallel Ground Connection Schemes (Ott, p.76)

The shortcoming of series ground connections is that more current flows through the ground
closest to the beginning of the chain than through the ground toward the end of the chain. Thus,
according to Ohm’s law, the series resistance of the ground trace will cause the analog circuitry
at one end of the series ground connections to be at a different ground potential than the analog
circuitry at the other end of the series ground connections. Moreover, common-mode rejection
between IC’s is worse with a series connection scheme than with a parallel scheme.
Consequently, parallel grounds are better for sensitive analog circuits.

For devices which have an on-board 32768 Hz PLL module, the PLL circuitry uses VSSA as its
reference and current return path. To enhance the immunity of the PLL circuitry, a copper shield
plane should be placed under and extending beyond the edges of the crystal and tied directly to
the VSSA pin. Except for the crystal resonator and its load capacitors and/or resistor, no other
components or traces should be connected to this shield except directly at the VSSA pin. This
avoids currents flowing through the shield which could inject noise into the PLL module. The
PLL-Based Clock Module Application Note should be referenced for additional guidelines
concerning PCB layout and component recommendations for optimum noise immunity for the
PLL circuitry.

3.2.3) Noisy Ground

“Noisy” grounds support circuitry that generates a significant amount of ground bounce, such as
relays and motors. This ground should be isolated from the digital and analog grounds in order
to keep high levels of ground noise away from analog and digital circuitry, which may be
susceptible to such noise.

3.2.4) Low Impedance Ground Node

The digital, analog, and noisy grounds should be connected together at a low impedance ground
point. This is often the point at which ground enters a circuit board and where the bulk
decoupling capacitor is located.

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3.2.5) Ground Width

Ground traces should be as wide as possible in order to provide the lowest impedance path for
current. However, in cases where wide ground traces are unacceptable, thin ground traces are
better than no ground traces at all. Thin ground traces can still reduce loop areas, whereas an
absence of ground traces can result in large loops. One approach for designing a two-layer
board is to lay down a thin-traced ground grid, making routes wider along high-current paths, and
to increase the width of the traces, where possible, after routing all of the other signals.

3.2.6) Connector Grounds

Improper grounding between IC’s and connectors (to off-board wiring or cable harnesses) can
result in serious common-mode radiation and can even cause bypass capacitors to resonate.
Thus, grounding between digital components and connectors is of paramount importance toward
keeping noise off of a wiring harness.

There should be a low-impedance ground between a microcontroller and a connector so that

bypass capacitors, located at the connector, can return noise to its source without allowing the
noise to travel onto the wiring harness.

3.2.7) Power Routing

Power should be routed over (under) or next to ground whenever possible. The power lines
typically contain the most high-frequency noise in a digital system. Therefore, their routing on a
PCB should receive special attention. Routing power directly over ground results in a path with
low inductance and minimized radiating loop area. Routing power and ground next to each other
is the next best alternative.

Additionally, series filters, such as ferrites or inductors, often prove helpful for reducing noise on
power supply routes. A π configuration can be used on the PVRPWR pin, for MCUs with the
primary voltage regulator (PVR) module, or on each of the VCC pins, for devices without an
integrated supply voltage regulator. An example of a π filter appears in the figure below.

MCU
VCC
PWR/VCC ferrite/inductor
VSS VSS

Figure 10: π filter configuration

The importance of choosing the right ferrite or inductor should not be underemphasized. For
example, the element should exhibit a high impedance at frequencies near 100MHz if that is the
part of the spectrum of most importance for the application. An inductor with a high impedance
at 10MHz may do nothing to filter noise at 100MHz.

Also, the ferrite should be located very close to the pin of the MCU in order to obtain the greatest
benefit of suppressing noise at the MCU and keeping the noise off of the PCB trace.

3.2.8) Clock Lines

Clock lines can contain high frequencies with 5V rail-to-rail switching. This optimizes their ability
to radiate EMI. Fast signals, such as an SPI with a 50K+ Baud rate also provide ample energy
for radiating. Thus, special precaution should be taken for fast signals. Clock lines and fast

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signals should be routed over or next to digital ground in order to minimize differential-mode
radiation from these sources. If fact, routing ground on each side of these fast signals provides a
good signal return while also providing some shielding for the nearby signals. Additionally,
routing fast signals to connectors (and wiring harnesses), or adjacent to other signals that are
routed to connectors, should be avoided. The fast signal lines should also be properly bypassed,
as discussed later.

3.2.9) Multi-layer Boards

Multi-layer boards can provide many EMC benefits over two-layer boards. Sometimes, providing
adequate grounding for EMC on a two-layer board is extremely difficult due to space, routing,
and component placement constraints. If this is the case, then a multi-layer board can improve
the system EMC performance with less time required for finding EMC fixes.

Multi-layer boards can provide several weapons against radiated EMI. First, multi-layer boards
provide low-impedance return paths for all signals. Since the high-frequency component of
every signal will return to its source via the path of least impedance, every signal will be returned
on the ground plane directly under the path of the signal. For this reason, the ground plane is
sometimes called an “image plane.” Consequently, the loop area associated with each signal will
correspond to the length of the trace and the thickness of the PCB between the signal layer and
the ground layer. On a board without a ground plane, the loop area corresponds to the area
between the signal and the return trace (usually ground), and this can be quite large.

Also, multi-layer boards can take advantage of the shielding capabilities of a ground plane if the
plane is on the outside of the board. In fact, imbedding the signal layers in the center of the
board, with ground planes on the outsides of the board, will provide shielding for much of the
system. This configuration is very good for EMC; however, it may add difficulty for circuit debug
since all of the signals will be covered over. Nevertheless, a generous number of test points and
vias as well as a copy of the board layout should provide an engineer with the necessary tools for
circuit debug for a board with buried signals.

Sometimes only one layer of ground plane is available. If that is the case, it usually should be
on the outside of the board, on the side with the fewest components, in order to provide the best
shielding effectiveness. If the ground plane is buried between two signal layers, its potential
shielding effectiveness is reduced. If the only ground plane is located on the side of the board
with the most components, the space required for the components (especially surface mount)
tends to create many holes or gaps in the ground plane, thus reducing its shielding effectiveness
and its image plane effect. Therefore, if locating a ground plane on the outer layer of a
multilayer PCB results in a “chopped up” ground plane, it should probably be implemented on an
inner layer instead. Regardless of where the ground plane is located, however, the image plane
effect usually provides a reduction of common-mode and differential-mode emissions.

Even when designing a PCB with a ground plane, good two-layer board design practices should
still be followed. Ground planes do not cure EMI, they just help to reduce it. Following are a few
points that are often overlooked when designing multi-layer PCBs:
• Routing clock lines or other high-speed signals near connectors or wiring harnesses should
be avoided. Routing these high-speed signals near other signals which are routed to
connectors or wiring harnesses should also be avoided. Noise may couple from one signal
to another which may be routed to a connector and wiring harness, providing several feet of
antenna for the radiated noise to propagate from.
• If clocks or high-frequency signals are exposed on the outer layer of the PCB, GND should
be routed on each side of the signal to couple noise back to the source and to provide some
shielding for other nearby signals.

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• Components (i.e., resistors and small capacitors) which filter emissions from the IC should
be kept as near to the pins as possible in order to suppress the noise within a minimal area.
These components should not be confused with circuitry designed to keep voltage spikes
from entering the PCB (i.e., diodes, MOVs, and large capacitors), which usually should be
located near the power and/or signal connectors on the PCB.
• “Chopping up” (making gaps) in the ground plane by placing signal traces on it should be
avoided. When the return current (GND current) cannot follow the path of least impedance
(the same path as the associated signal), radiating loops are created. The following figure
illustrates how a slot in a ground plane creates a less direct path for ground current and
creates a larger signal-to-return loop area.

Bottom-side Copper
Return Path Slot in GND Plane
On GND
IC Top-side Route
Plane
(Top- (Top-
Bottom-side Route
side) side)
Signal Return Path On GND Plane
Via
Slot in
Bottom-side
GND Plane

Figure 11: Slot in a ground plane

Sometimes, the placement of connectors, DIP devices, or multiple vias (feed-through holes)
inadvertently chops up a ground plane when copper is not allowed to flow between the holes.
These gaps should be avoided since they deteriorate the benefits of a ground plane.
• Signal layer connections to ground planes (i.e., a route from the GND side of a capacitor to a
via connecting it to GND) should be kept as short as possible in order to take advantage of
the low-impedance properties of the ground plane.
• Private-line VSSA traces can be routed on a signal layer in order to assure clean analog
ground and to avoid ground loops, which may detrimentally affect analog circuitry. This may
or may not be necessary, depending on the desired accuracy of the analog circuitry and also
the levels of noise on the ground planes.
• An VSSA peninsula should still be placed directly under the 32768 Hz crystal resonator and
its associated capacitors and/or resistor (for devices with the 32768 Hz PLL module only)
and connected to the VSSA pin. No current should be allowed to flow through the peninsula
except for the oscillator currents. The PLL-Based Clock Module Application Note should be
referenced for additional guidelines concerning PCB layout and component
recommendations for optimum noise immunity for the PLL circuitry.

3.3) Bypassing
Bypass capacitors serve several functions for digital logic. When used on power pins, they
supply current for digital switching. When used on I/O pins, bypass capacitors provide current
return paths for high-frequency noise. They also help to round the edges of a digital signal and
thus reduce the harmonic content of the signal.

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3.3.1) Power Bypassing: VCCD/VSSD (VCCD1/VSSD1 & VCCD2/VSSD2), VCCA/VSSA, and

PLLENA
Inside cMCU370 devices, VCCD is not connected internally to VCCA. Likewise, VSSD is not
directly connected internally to VSSA. Some devices have the core digital logic power supply
(VCCD1/VSSD1) routed to different pins than the I/O buffer power supply (VCCD2/VSSD2) in
order to help keep noise from the core logic isolated from the I/O pins, and vise-versa. Other
devices have the core digital logic power supply and the I/O buffer power supply connected only
at the package leadframe. In any case, the analog power supply is always separate from the
digital supplies. The following table shows the functions of power/gnd pins on cMCU370
devices.

VCCD/VSSD Digital power/gnd.

VCCD is a combination of VCCD1 and VCCD2,
which are routed separately inside of the cMCU370
Device and connected at the leadframe. Similarly,
VSSD is a combination of VSSD1 and VSSD2.
VCCD1/VSSD1 Core digital logic power/gnd
VCCD2/VSSD2 Digital CMOS I/O buffer power/gnd
VCCA/VSSA Analog circuitry power/gnd
PLLENA/VSSA PLL circuitry power/gnd

If both the core logic power and the I/O buffer power are present on separate pins on the Device,
then they should have separate bypass capacitors.

VCCD1 should be bypassed to VSSD1, and VCCD2 should be bypassed to VSSD2. Similarly,
the analog supply (VCCA) should be bypassed only to analog ground (VSSA). Since the
PLLENA pin supplies the power to the PLL (Phase-Locked Loop) circuitry, this pin should have a
bypass capacitor to VSSA, which is the ground reference for the PLL.

Since VCCD and VSSD supply the current to the digital logic, they contain the most high-
frequency electromagnetic energy of any pins on a device. Thus, the loop created by VCCD and
VSSD should receive the most attention with regards to placement of the capacitors and the
loops created by their connections. Therefore, the VCCD bypass capacitor (0.1uF) should
always be attached as close as possible to the device’s VCCD and VSSD pins, and should
provide minimal loop areas for the high-frequency currents. For devices with the Primary
Voltage Regulator (PVR) module, the load capacitor (22uF) and its associated routing should
also be located very close to the VCCD and VSSD pins, and the routing should create minimal
loop area.

The locations and routing of the bypass and load capacitors for the analog circuitry
(VCCA/VSSA) should take next priority after the digital supply capacitors. For devices with
VCCD2 and VSSD2 pins, the capacitors for these pins should receive priority only after
VCCD1/VSSD1 and VCCA/VSSA pins.

A 0.1uF ceramic chip-type bypass capacitor should be used with each power/ground
combination. However, VCCD should not be bypassed to VSSA, and conversely, VCCA should
not be bypassed to VSSD. 22uF tantalum capacitors, preferably in surface-mount packages,
should be used to load the PVR on its regulated digital and analog supply pins. The PLLENA pin
should be bypassed with a 0.01uF ceramic chip-type capacitor to VSSA.

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3.3.2) Signal Bypassing

Ideally, every I/O on the device should have an RC filter attached close to the pin. This would
provide both wave-shaping for the signal and smaller return paths for high-frequency noise.
However, this is usually not necessary or practical.

On the other hand, some pins that have high-frequency signals should have at least a small
bypass capacitor connected to digital ground (VSSD2, if available, otherwise VSSD). SPI pins
with 50K+ Baud rates and the CLKOUT pin, if SYSCLK or ECLK is active on the pin, are good
candidates for bypass capacitors of 0.001uF to VSSD (or VSSD2 if available) and series
resistors. The value of the series resistor depends on the loading and current drive capability of
the output; however, 100 ohms is a good value to start with.

Any filter components attached to a device pin should be located as close as possible in order to
keep any noise close to the microcontoller and off of the rest of the circuit board. Moreover, a
proper return path for a bypass capacitor, from the capacitor’s ground to the microcontroller’s
ground, is essential for returning high-frequency noise to its source while providing minimal
radiating loop area.

3.3.3) Connector Bypassing

Signals which are routed to a connector should also be bypassed at the connector with a 0.001uF
capacitor. This will help to keep high frequencies off of the cables and/or wiring harness by
providing a high-frequency path for any noise to get back to its source before entering the wiring
harness. Proper grounding must be supplied between the microcontroller and the connector in
order to keep the bypass capacitors from radiating rather than filtering noise.

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4.0) Summary
By understanding and applying a few fundamental PCB design guidelines, a designer can reduce
the radiated EMI of a system inexpensively at the beginning of the design cycle. Following is a
summary of PCB design guidelines for reduced EMI:

1) Floor-plan PCB first

• Analog, Digital, and Noisy components should be located on PCB by category.
• Allow space for grounding.
• Minimize routing distances.
• IC’s that have high-frequency signals (i.e. CLKOUT or SPICLK of 50+ KHz)
should be placed near each other to minimize routing distances of clocks and
fast signals.
2) Grounding
• Digital: Grid the ground.
• Analog: Use parallel grounding scheme for sensitive analog circuitry, and use
series grounding scheme for less sensitive analog circuitry.
• Noisy: Isolate from analog and digital grounds.
• Low impedance ground node: Connect Digital, Analog, and Noisy grounds
together at the lowest impedance ground node on the PCB.
• Connectors: Provide low-impedance ground between IC’s and connectors.
• Fast signals: Run digital ground next to fast signals (or over if possible).
3) Bypassing
• Power: Capacitors should be located as near as possible to VCCD and VSSD
pins (VCCD should not be bypassed to VSSA) and conversely, capacitors should
be located as near as possible to VCCA and VSSA pins (VCCA should not be
bypassed to VSSD). If VCCD2 and VSSD2 pins are available, capacitors should
be located as near as possible to these pins also.
• Signal: Capacitors should be located as near as possible to the associated pins.
• Connector: Proper grounding between the microcontroller and a connector is
necessary for the bypass capacitors at the connector to keep noise off of the
wiring harness.

4.1) Priority of Guidelines

a) Locate devices on PCB for EMC optimization of: 1) grounds, 2) power, and 3) routing
(especially clocks and high-speed signals).
b) Place VSSA peninsula for 32768 Hz crystal and load circuitry, and route that circuitry (only
for devices with 32768 Hz PLL module). This step helps to ensure conformance to
susceptibility requirements and is not a major factor for reducing radiated emissions.
c) Provide a ground grid for a two-layer board or a ground plane(s) for a multi-layer board.
d) Route power, and place filter components.
e) Route clocks and high-speed signals, and place filter components.
f) Route other noise-making or noise-susceptible signals. Also give attention to Reset and
control signals.
g) Route all other circuitry.

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5.0) PCB Layout Example

Following is an example of PCB layout near the microcontroller on a 2-layer PCB using
cMCU370 devices with a PVR and a 32768 Hz PLL module.

Example Layout for Device with PVR and 32768 Hz PLL

On a 2-Layer PCB With Components on Both Sides

22pF 10 Meg
32768Hz

OSCIN
OSCOUT
Always route 22uF Top-side
power and ground
22pF PLLENA .1uF VSSD plane
over or near VSSD under chip
each other. 10uH
IGNITION PRIGN
VSSA Low impedance point
.01uF VCCD on ground node
GND
+12 Volts PVRPWR GND
VCCA
Top-side
VSSA plane
22uF under chip
.1uF
Gray = Top-side Cu
Black = Back-side Cu

Figure 12: Example layout for Device with PVR and 32768 Hz PLL Modules

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References

Ott, Henry W., Noise Reduction Techniques In Electronic Systems, second edition, John Wiley &
Sons, New York, 1988.

Gerke, Daryl and Bill Kimmel, EDN: The Designer’s Guide to Electromagnetic Compatibility,
Cahners Publishing Company, 1994.

Paul, Clayton R., Introduction to Electromagnetic Compatibility, John Wiley & Sons, Inc., 1992.

Van Doren, Tom, Grounding and Shielding Electronic Systems, T. Van Doren, 1993.

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