National University of Sciences and Technology
College of Electrical and Mechanical Engineering
Digital Logic Design
Department of Electrical Engineering
Assignment 4 – FALL 2024 (DE-45-EE(B & C))
Deadline : 29th December ,2024
No late submission will be accepted.
Problem 1 [CLO3]
1)A PN flip-flop has four operations, clear to 0,no change, complement, and set to 1,when inputs
P and N are 00,01, 10, and 11, respectively.
a) Tabulate the characteristic table.
b) Tabulate the excitation table
2)Design the mentioned the PN flip-flop
a) Using a T flip flop.
b) Using a D flip flop.
c) Using a SR flip flop
Problem 2 [CLO3]
Design a JK flip-flop
a) Using a T flip-flop and logic gates.
b) Using SR flip-flop and logic gates
c) Using a D flip-flop, a two-to -one-line multiplexer, and an inverter.
Problem 3 [CLO3]
Design a network which adds 4 to the contents of a 4bit register after a single input pulse (C) is
applied to the network. Use JK flip flops and assume the number in the 4-bit register, N is
0000 <= N <= 1011.
Problem 4 [CLO3]
Design a counter, which counts in the following manner 0000, 1000, 1100, 1010, 1110, 0001,
1001, 1101, 1011, 1111, 0000
a) Using T flip flops and AND and OR gates.
b) Using D flip flops and NOR gates.
c) Using SR flip flops and AND and OR gates.
d) Using JK flip flops and NAND gates.
Problem 5 [CLO3]
Design the following counters
a) Mod 9 synchronous up counter using JK Flip flop and synchronous reset
b) Mod 9 synchronous up counter using JK flip flop and Asynchronous reset
Problem 6 [CLO3]
Design a three-bit up/down counter using T flip-flops. It should include a control input called
Up/Down. If Up/Down =0 , then the circuit should add two the existing state. If Up/Down = 1,
then the circuit should subtract 3 from existing state.
