Hardware Description Language

Lab Submitted Report

Indian Institute of Information Technology, Surat.

For
Bachelor of Technology

In
Electronics and Communication Engineering Department

Submitted by
Reg. No. UI21EC63
Name: Shubham yadav

Course Faculty
Ms. Sejal Rathod

Department of Electronics and Communication

Engineering.

Indian Institute of Information Technology, Surat.

Gujarat – 394190.
 India 2024.
Indian Institute of Information
Technology, Surat.

Certificate

This is to certify that Mr. Shubham yadav of

3rd Year - 5th Semester, class roll no. UI21EC63
has satisfactory completed the course in
Hardware Description Language Laboratory
Practical During year 2024.
Ms. Sejal Rathod (Subject
Coordinator and Lab Instructor)
Table of Contents
Lab No. Name of The Experiment

1 Task 1. Intro to Simulation Software.

Task 2. Write HDL description in Verilog for basic logic gates using (a)
Boolean-Equations, ,(b) Structural-Objects. Write testbench and
verify their functionality using simulation.
2 Task: Write HDL description in VHDL for all basic gate using Boolean-
Equations. Write test-bench and verify their functionality using
simulation.
3 Consider the given circuit below:

Task 1: Write HDL description using Verilog for the given circuit
using (a) Boolean-Equations With and Without gate delays, (b)
Structural-Objects With and Without gate delays, (c) Truth-Table.
Write testbench and verify their functionality using simulation.
Task 2: Write HDL description using VHDL for the given circuit.

4 Task 1: Write HDL description in Verilog for Half-Adder and

HalfSubtractor using (a) Data Flow Modeling, (b) Structural
Modeling, (c) User Define Primitives (UDP) and write Test-bench and
Verify their functionality using simulation.
Task 2: Write HDL description in VHDL for Half-Adder and
HalfSubtractor using (a) Data Flow Modeling, (b) Structural
Modeling.
Write Test-bench and Verify their functionality using simulation.
5 Task 1: Write HDL description in Verilog using data flow modeling for
(a) 1-bit magnitude comparator circuit without predefined
operators, (b) 4-bit magnitude comparator circuit with predefined
operators, (c) A circuit which receives 3-bit inputs A and B and
produces results for A
* B where * is various bit-wise operators and logical operators. Write
testbench and verify their functionality using simulation.
Task 2: Write HDL description in VHDL using data flow modeling &
predefined operators for (a) 1-bit magnitude comparator circuit
without predefine operator, (b) 4-bit magnitude comparator circuit
with predefined operators, (c) A circuit which receives 3-bit inputs A

and B and produces results for A * B where * is various bit-wise

operators and logical operators. Write testbench and verify their
functionality using simulation.
6 Task: Write HDL description in VHDL using structural modeling for
Full-Adder circuit Write testbench and verify their functionality
using simulation.
7 Task 1: Write HDL description for 2x4 Decoder using Verilog in (a)
Boolean-Equations, (b) Structural Method.
Task 2: Write HDL description for 2x4 Decoder using VHDL in (a)
Boolean-Equations, (b) Structural Method (c) with-select-when Data
flow, (d) when-else Data Flow.
8 Task 1: Write HDL description for Binary to Gray in Verilog using (a)
Boolean-Equations, (b) Structural Method.
Task 2: Write HDL description for Binary to Gray in VHDL using (a)
Boolean-Equations, (b) Structural Method, (c) with-select-when, (d)
when-else.
Task 3: Write HDL description for Gray to Binary in Verilog using (a)
Boolean-Equations, (b) Structural Method.
Task 4: Write HDL description for Gray to Binary in VHDL using (a)
Boolean-Equations, (b) Structural Method, (c) with-select-when, (4)
when-else.
9 Task 1:Write HDL Description for 4x1 Multiplexer in Verilog Behavior
Method (a) If-else conditional, (b) Case conditional.
Task 2: Write HDL Description for 4x1 Multiplexer in VHDL using (a)
with-select-when, (b) when-else, (c) Behavior Method, (d) If-else
conditional, (e) Case conditional.
10 Task 1: Write HDL description for SR latch with nor VHDL and
Verilog.
Task 2: Write HDL description for D, JK, T flip flop in VHDL and
Verilog.
11 Task 1: Write HDL description for 4 bit binary up counter using if
statement in Verilog Behavior Method
Task 2: Write HDL description for 3 bit binary up counter using case
statement in VHDL Behavior Method
 Lab1

A) Verilog code for basic logic gates using Boolean Equations

B) Code –
Test bench code

// Code your testbench here // Code your design here

`timescale 1ns/1ps `timescale 1ns/1ps
module ec_63(); module ec_63_db(output
wire AND_63,OR_63,NOT_63,NAND_63,NOR_63,XOR_63,XNOR_63; AND63,OR63,NAND63,NOR63,XOR63,XNOR63,NOT6
reg P_63,Q_63; input A63,B63);
ec_63_db assign AND63 = A63 && B63;
assign OR63 = A63 || B63;
I1(AND_63,OR_63,NOT_63,NAND_63,NOR_63,XOR_63,XNOR_63,P_63,Q_63); assign NAND63 = ~(A63 && B63);
initial begin assign NOR63 = ~(A63 || B63);
$dumpfile("dump.vcd"); assign XOR63 = A63 ^ B63;
$dumpvars(1); assign XNOR63 = ~(A63 ^ B63);
P_63 = 1'b0; Q_63 = 1'b0; assign NOT63 = ~A63;
#10 P_63 = 1'b0; Q_63 = 1'b1; endmodule
#10 P_63 = 1'b1; Q_63 = 1'b0;
#10 P_63 = 1'b1; Q_63 = 1'b1;
#10 P_63 = 1'b0; Q_63 = 1'b0;
end
initial #50 $finish;
endmodule

output graph:-
 B) Verilog code for basic logic gates using Structural
Object

Code -
testbench Design code
// Code your testbench here // Code your design here
// or browse Examples `timescale 1ns/1ps
`timescale 1ns/1ps module ec_63_db(output
module ec_63(); AND63,OR63,NAND63,NOR63,XOR63,XNOR63,NOT63, input
wire A63,B63);
AND_63,OR_63,NOT_63,NAND_63,NOR_63,XOR_63,XNOR_63; and(AND63,A63,B63);
reg P_63,Q_63; or(OR63,A63,B63);
ec_63_db I1(AND_63,OR_63,NOT_63,NAND_63,NOR_63, nand(NAND63, A63, B63);
XOR_63,XNOR_63,P_63,Q_63); nor (NOR63, A63, B63);
initial begin xor (XOR63, A63, B63);
$dumpfile("dump.vcd"); xnor (XNOR63, A63, B63);
$dumpvars(1); not (NOT63, A63);
P_63 = 1'b0; Q_63 = 1'b0; endmodule
#10 P_63 = 1'b0; Q_63 = 1'b1;
#10 P_63 = 1'b1; Q_63 = 1'b0;
#10 P_63 = 1'b1; Q_63 = 1'b1;
#10 P_63 = 1'b0; Q_63 = 1'b0;
end
initial #50 $finish;
endmodule
 LAB – 2
Aim – Write HDL description in VHDL for basic logic gates
using Boolean-Equations. Write testbench and verify their
functionality using simulation.

Code -
testbench code

library IEEE; -- Code your design here

use IEEE.std_logic_1164.all; library IEEE;
entity db_ec_63 is use IEEE.std_logic_1164.all;
end db_ec_63; entity kc_63 is

architecture db_63 of db_ec_63 port(A63,B63 : in std_logic;

is
component kc_63 AND63,OR63,NAND63,NOR63,XOR63,XNOR63,NOT63:
port(A63,B63 : in std_logic; out std_logic);
AND63,OR63,NAND63,NOR63,XOR63,XNOR63,NOT63: end kc_63;
out std_logic); architecture kc_logic_63 of
end component; kc_63 is
signal begin
A_63,B_63,AND_63,OR_63,NAND_63,NOR_63,XOR_63, AND63 <= A63 AND B63;
XNOR_63,NOT_63 : std_logic; OR63 <= A63 OR B63;
begin NAND63 <= A63 NAND B63;
DUT :kc_63 port NOR63 <= A63 NOR B63;
map (A_63,B_63, XOR63 <= A63 XOR B63;
AND_63,OR_63,NAND_63,NOR_63,XOR_63,XNOR_63,NOT_63); XNOR63 <= A63 XNOR B63;
A_63 <='0','0' after 10 ns, '1' after 20 ns, '1' after 30 ns,'0' after NOT63 <= NOT A63;
40 ns; end kc_logic_63;
B_63 <= '0','1' after 10 ns,'0' after 20 ns, '1' after 30 ns , '0'
after 40 ns;
end db_63;
 LAB – 3
Aim – A) Write HDL description using Verilog for the circuit
given above using a) Boolean-Equations: With and without
gate delays b) Structural-Objects: With and without gate
delays c) Truth-Table. Write testbench and verify their
functionality using simulation.

B) Write HDL description using VHDL for the circuit given above
using
Boolean-Equations: With and without gate delays

A) 1) Verilog code for the given circuit using Boolean

Equations
testbench Code without delay
// Code your testbench here // Code your design here
// or browse Examples `timescale 1ns/1ps
`timescale 1ns/1ps module ec_63(output E63,input A63,B63,C63);
module tb_ec_63(); wire D63;
wire E_63; assign D63 = A63 || B63;
reg A_63,B_63,C_63; assign E63 = C63 && D63;
ec_63 I1 (E_63,A_63,B_63,C_63); endmodule
initial begin
$dumpfile("dump.vcd");
$dumpvars(1); code with delay
A_63 = 1'b0; B_63 = 1'b0; C_63 = 1'b0;
#20 A_63 =1'b0; B_63 = 1'b0; C_63 =1'b1; // Code your design here
#20 A_63 =1'b0; B_63 = 1'b1; C_63 =1'b0; `timescale 1ns/1ps
#20 A_63 =1'b0; B_63 = 1'b1; C_63 =1'b1; module ec_63(output E63,input A63,B63,C63);
#20 A_63 =1'b1; B_63 = 1'b0; C_63 =1'b0; wire D63;
#20 A_63 =1'b1; B_63 = 1'b0; C_63 =1'b1; assign #5 D63 = A63 || B63;
#20 A_63 =1'b1; B_63 = 1'b1; C_63 =1'b0; assign #10 E63 = C63 && D63;
#20 A_63 =1'b1; B_63 = 1'b1; C_63 =1'b1; endmodule
#20 A_63 =1'b0; B_63 = 1'b0; C_63 =1'b0;
end
initial #170 $finish;
endmodule
 2) Verilog code for the given circuit using
StructuralObjects: With and without gate

Code –
testbench code
// Code your testbench here // Code your design here
// or browse Examples `timescale 1ns/1ps
`timescale 1ns/1ps module ec_63(output E63,input A63,B63,C63);
module tb_ec_63(); wire D63;
wire E_63; or #5 (D63,A63,B63);
reg A_63,B_63,C_63; and #10 (E63,C63,D63);
ec_63 I1 (E_63,A_63,B_63,C_63); endmodule
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
A_63 = 1'b0; B_63 = 1'b0; C_63 = 1'b0;
#20 A_63 =1'b0; B_63 = 1'b0; C_63 =1'b1;
#20 A_63 =1'b0; B_63 = 1'b1; C_63 =1'b0;
#20 A_63 =1'b0; B_63 = 1'b1; C_63 =1'b1;
#20 A_63 =1'b1; B_63 = 1'b0; C_63 =1'b0;
#20 A_63 =1'b1; B_63 = 1'b0; C_63 =1'b1;
#20 A_63 =1'b1; B_63 = 1'b1; C_63 =1'b0;
#20 A_63 =1'b1; B_63 = 1'b1; C_63 =1'b1;
#20 A_63 =1'b0; B_63 = 1'b0; C_63 =1'b0;
end
initial #170 $finish;
endmodule

Witout delay
// Code your design here
`timescale 1ns/1ps
module ec_63(output E63,input A63,B63,C63);
wire D63;
or (D63,A63,B63);
and (E63,C63,D63);
endmodule

using Dataflow modeling.

 LAB – 4
Aim – A) Write HDL description in Verilog for Half-
Adder & Half - Subtractor circuits using a)

Dataflow modeling, b) Structural modeling & c) UDP

(User-Defined-Primitives). Write testbench and
verify their functionality using simulation.

B) Write HDL description in VHDL for Half-Adder &

Half-Subtractor circuits using a) Dataflow
modeling & b) Structural modeling. Write testbench
and verify their functionality using simulation.
 Half Adder Half Subtractor

A) 1) Verilog code for the Half Adder and Half Subtractor

Testbench halfadd Testbench halfsub

// Code your testbench here // Code your testbench here

// or browse Examples // or browse Examples

`timescale 1ns/1ps `timescale 1ns/1ps

module ec_ui_63; module ec_ui_63;

reg reg
A_63,B_63,SUM_63,CARRY_63; A_63,B_63,DIFF_63,BORROW_63;

half_sub_63

half_adder_63
I1(SUM_63,CARRY_63,A_63,B_63); I1(DIFF_63,BORROW_63,A_63,B_63);

initial begin initial begin

$dumpfile("dump.vcd"); $dumpfile("dump.vcd");

$dumpvars(1); $dumpvars(1);
 A_63 = 1'b0; B_63 = 1'b0; A_63 = 1'b0; B_63 = 1'b0;

#20 A_63 = 1'b0; B_63 #20 A_63 = 1'b0; B_63 =1'b1;

=1'b1;
#20 A_63 = 1'b1; B_63 = 1'b0;
#20 A_63 = 1'b1; B_63 =
#20 A_63 = 1'b1; B_63 = 1'b1;
1'b0;
#20 A_63 = 1'b0; B_63 = 1'b0;
#20 A_63 = 1'b1; B_63 =
1'b1; end
#20 A_63 = 1'b0; B_63 = initial #80 $finish;
1'b0;
endmodule
end

initial #80 $finish;

endmodule

halfadd halfsub

// Code your design here // Code your design here

`timescale 1ns/1ps `timescale 1ns/1ps

module module
half_adder_63(output half_sub_63(output
SUM63,CARRY63,input DIFF63,BORROW63,input
A63,B63); A63,B63);

assign SUM63 = A63^B63; assign DIFF63 =

A63^B63;
assign CARRY63 = A63 &&
B63; assign BORROW63 = A63
&& B63;
endmodule
endmodule
 2) Verilog code for the Half Adder and Half Subtractor
using Structural modelling

Testbench halfadd Testbench halfsub

// Code your testbench here // Code your testbench here

// or browse Examples // or browse Examples

`timescale 1ns/1ps `timescale 1ns/1ps

module ec_ui_63; module ec_ui_63;

reg A_63,B_63; reg A_63,B_63;

wire SUM_63,CARRY_63; wire DIFF_63,BORROW_63;

half_add_63 half_sub_63
I1(SUM_63,CARRY_63,A_63,B_63); I1(DIFF_63,BORROW_63,A_63,B_63);

initial begin initial begin

$dumpfile("dump.vcd"); $dumpfile("dump.vcd");

$dumpvars(1); $dumpvars(1);

A_63 = 1'b0; B_63 = 1'b0; A_63 = 1'b0; B_63 = 1'b0;

 #20 A_63 = 1'b0; B_63 =1'b1; #20 A_63 = 1'b0; B_63 =1'b1;

#20 A_63 = 1'b1; B_63 = 1'b0; #20 A_63 = 1'b1; B_63 = 1'b0;

#20 A_63 = 1'b1; B_63 = 1'b1; #20 A_63 = 1'b1; B_63 = 1'b1;

#20 A_63 = 1'b0; B_63 = 1'b0; #20 A_63 = 1'b0; B_63 = 1'b0;

end end

initial #80 $finish; initial #80 $finish;

endmodule endmodule

halffadd halffsub

// Code your design here // Code your design here

`timescale 1ns/1ps `timescale 1ns/1ps

module half_add_63(output module half_sub_63(output

SUM63,CARRY63, input A63,B63); DIFF63,BORROW63, input A63,B63);

xor(SUM63,A63,B63); xor(DIFF63,A63,B63);

and(CARRY63, A63,B63); and (BORROW63,~A63,B63);

endmodule endmodule
3) Verilog code for the Half Adder and Half Subtractor
using UDP (User-Defined-Primitives).

Half Adder Half Subtractor

// Code your design here // Code your design here

primitive primitive
HALFADDER_SUM_63 HALFSUB_DIFF_63
(SUM_63,A_63,B_63); (DIFF_63,A_63,B_63);
output SUM_63; output DIFF_63;
input A_63,B_63; input A_63,B_63;
table table
// a63 b63 : sum63 // a63 b63 : diff63
0 0 : 0; 0 0 : 0;
0 1 : 1; 0 1 : 1;
1 0 : 1; 1 0 : 1;
1 1 : 0; 1 1 : 0;
endtable endtable
endprimitive endprimitive

primitive primitive
HALFADDER_CARRY_63 HALFSUB_BORROW_63
 (CARRY_63,A_63,B_63); (BORROW_63,A_63,B_63);
output CARRY_63; output BORROW_63;
input A_63,B_63; input A_63,B_63;
table table
// a63 b63 : // a63 b63 :
carry63 carry63
0 0 : 0; 0 0 : 0;
0 1 : 0; 0 1 : 1;
1 1 : 1; 1 1 : 0;
1 0 : 0; 1 0 : 0;
endtable endtable
endprimitive endprimitive
`timescale 1ns/1ps `timescale 1ns/1ps
module module
half_adder_63(output half_sub_63(output
SUM_63,CARRY_63,input SUM_63,BORROW_63,input
A_63,B_63); A_63,B_63);
HALFADDER_SUM_63 HALFSUB_DIFF_63
U1(SUM_63,A_63,B_63); U1(SUM_63,A_63,B_63);
HALFADDER_CARRY_63 HALFSUB_BORROW_63
U2(CARRY_63,A_63,B_63); U2(CARRY_63,A_63,B_63);
endmodule endmodule
B) 1) VHDL code for the Half Adder and Half Subtractor using
Dataflow modeling.

halfsub Half add

--Code your testbench here -- Code your testbench here

--or browse Examples library IEEE;

library IEEE; use IEEE.std_logic_1164.all;

use IEEE.std_logic_1164.all; entity ec_ui_63 is

entity ec_ui_63 is end ec_ui_63;

end ec_ui_63; architecture ec_63 of ec_ui_63 is

architecture ec_63 of ec_ui_63 is component cb_63 is

component cb_63 is port (A63,B63 : in std_logic;

SUM63,CARRY63 : out std_logic);
port (A63,B63 : in std_logic;
end component;
DIFF63,BORROW63 : out std_logic);
signal A63,B63,SUM63,CARRY63 :
end component; std_logic;

signal A63,B63,DIFF63,BORROW63 : begin

std_logic;
DUT: cb_63 port
begin map(A63,B63,SUM63,CARRY63);

DUT: cb_63 port A63 <= '0', '0' after 20 ns , '1' after 40 ns,
map(A63,B63,DIFF63,BORROW63); '1' after 60 ns, '0' after 80 ns ;

A63 <= '0', '0' after 20 ns , '1' after 40 ns, B63 <= '0', '1' after 20 ns , '0' after 40 ns,
'1' after 60 ns, '0' after 80 ns ; '0' after 60 ns, '1' after 80 ns ;

B63 <= '0', '1' after 20 ns , '0' after 40 ns,

'0' after 60 ns, '1' after 80 ns ;
end ec_63;

end ec_63;
Code halfsub halfadd

// Code your design here -- Code your design here

library IEEE; library IEEE;

use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity cb_63 is entity cb_63 is

port (A63,B63 : in std_logic ; DIFF63,BORROW63 : port (A63,B63 : in std_logic ; SUM63,CARRY63 :

out std_logic); out std_logic);

end cb_63; end cb_63;

architecture db_63 of cb_63 is architecture db_63 of cb_63 is

begin begin

DIFF63 <= A63 XOR B63; SUM63 <= A63 XOR B63;

BORROW63 <= NOT(A63) AND B63; CARRY63 <= A63 AND B63;

end db_63; end db_63;

2) Verilog code for the Half Adder and Half Subtractor
using UDP (User-Defined-Primitives).

Half Adder Half Subtractor

// Code your testbench here // Code your testbench here

// or browse Examples // or browse Examples

`timescale 1ns/1ps `timescale 1ns/1ps

module ec_ui_63; module ec_ui_63;

reg A_63,B_63; reg A_63,B_63;

wire SUM_63,CARRY_63; wire DIFF_63,BORROW_63;

half_adder_63 half_sub_63
I1(SUM_63,CARRY_63,A_63,B_63); I1(DIFF_63,BORROW_63,A_63,B_63);

initial begin initial begin

$dumpfile("dump.vcd"); $dumpfile("dump.vcd");

$dumpvars(1); $dumpvars(1);

A_63 = 1'b0; B_63 = 1'b0; A_63 = 1'b0; B_63 = 1'b0;

#20 A_63 = 1'b0; B_63 =1'b1; #20 A_63 = 1'b0; B_63 =1'b1;

#20 A_63 = 1'b1; B_63 = 1'b0; #20 A_63 = 1'b1; B_63 = 1'b0;

#20 A_63 = 1'b1; B_63 = 1'b1; #20 A_63 = 1'b1; B_63 = 1'b1;

#20 A_63 = 1'b0; B_63 = 1'b0; #20 A_63 = 1'b0; B_63 = 1'b0;

end end

initial #80 $finish; initial #80 $finish;

endmodule endmodule
Half Adder Half Subtractor
// Code your design here // Code your design here

primitive HALFADDER_SUM_63 primitive HALFSUB_DIFF_63

(SUM_63,A_63,B_63); (DIFF_63,A_63,B_63);

output SUM_63; output DIFF_63;

input A_63,B_63; input A_63,B_63;

table table

// a63 b63 : sum63 // a63 b63 : diff63

0 0 : 0; 0 0 : 0;

0 1 : 1; 0 1 : 1;

1 0 : 1; 1 0 : 1;

1 1 : 0; 1 1 : 0;

endtable endtable

endprimitive endprimitive

primitive HALFADDER_CARRY_63 primitive HALFSUB_BORROW_63

(CARRY_63,A_63,B_63); (BORROW_63,A_63,B_63);

output CARRY_63; output BORROW_63;

input A_63,B_63; input A_63,B_63;

table table

// a63 b63 : carry63 // a63 b63 : carry63

0 0 : 0; 0 0 : 0;

0 1 : 0; 0 1 : 1;

1 1 : 1; 1 1 : 0;

1 0 : 0; 1 0 : 0;
endtable endtable

endprimitive endprimitive

`timescale 1ns/1ps `timescale 1ns/1ps

module half_adder_63(output module half_sub_63(output

SUM_63,CARRY_63,input A_63,B_63); SUM_63,BORROW_63,input A_63,B_63);

HALFADDER_SUM_63 HALFSUB_DIFF_63
U1(SUM_63,A_63,B_63); U1(SUM_63,A_63,B_63);

HALFADDER_CARRY_63 HALFSUB_BORROW_63
U2(CARRY_63,A_63,B_63); U2(CARRY_63,A_63,B_63);

endmodule endmodule
 LAB – 5
Aim – A) Write HDL description in Verilog using dataflow modeling
for a) 1-bit magnitude comparator circuit {w/o predefined
operators}. b) 4-bit magnitude comparator circuit {with
predefined operators}. c) a circuit which receives 3-bit inputs
A and B and produces results for A * B where * is various bit-
wise operators and logical operators. Write testbench and verify
their functionality using simulation.

B) Write HDL description in VHDL using dataflow modeling &

predefined operators for a) 1-bit magnitude comparator circuit
b) 4-bit magnitude comparator circuit {with predefined
operators} c) a circuit which receives 3-bit inputs A and B and
produces results for A * B where * is various bit-wise operators
and logical operators. Write testbench and verify their
functionality using simulation.

A) 1) Write HDL description in Verilog using dataflow

modeling for 1-bit magnitude comparator circuit {w/o
predefined operators}.

Testbench code
 // Code your testbench here // Code your design here
// or browse Examples `timescale 1ns/1ps
`timescale 1ns/1ps module bit_comp_63(input
module mc_ec_63(); A63,B63, output
LESS63,EQUAL63,GREATER63);
reg
A63,B63,LESS63,EQUAL63,GREATER63; assign LESS63= ~A63 & B63;
bit_comp_63 I1(A63,B63,LESS63, assign EQUAL63 = A63 &
EQUAL63, GREATER63); ~B63;
initial begin
assign GREATER63 = ~((~A63 &
$dumpfile("dump.vcd"); B63) | A63 & ~B63);
$dumpvars(1); endmodule
A63 = 1'b0 ; B63= 1'b0;

#20 A63 = 1'b0; B63 = 1'b1;

#20 A63 = 1'b1; B63 = 1'b0;
#20 A63 = 1'b1; B63 = 1'b1;
#20 A63 = 1'b0; B63 = 1'b0;
end
initial #80 $finish;
endmodule

2) Write HDL description in Verilog for 4-bit magnitude

comparator circuit {with predefined operators}.

testbench code

// Code your testbench here // Code your design here

// or browse Examples `timescale 1ns/1ps

`timescale 1ns/1ps module bit_comp_63(input A63,B63,

output GREATER63,EQUAL63,LESS63);
module bit4_ec_63;
assign GREATER63 = (A63 >B63);
reg [3:0] A63,B63;
assign EQUAL63 = (A63 == B63);
reg GREATER63,EQUAL63,LESS63;
assign LESS63 =(A63 < B63);
 bit_comp_63 endmodule
I1(A63,B63,GREATER63,EQUAL63,LESS63
);

initial begin

$dumpfile("dump.vcd");

$dumpvars(1);

A63 = 4'b0000 ; B63= 4'b0000;

#20 A63 = 4'b1000; B63 = 4'b0100;

#20 A63 = 4'b0111; B63 = 4'b1000;

#20 A63 = 4'b1110; B63 = 4'b0100;

#20 A63 = 4'b0000; B63 = 4'b1010;

end

initial #80 $finish;

endmodule
 3) Write HDL description in Verilog for a circuit which
receives 3-bit inputs A and B and produces results for
A * B where * is various bit-wise operators and logical
operators.

testbench code
// Code your testbench here // Code your design here
// or browse Examples `timescale 1ns/1ps
`timescale 1ns/1ps module bit_comp_63 (input [2:0] A63,B63, output [2:0]
module bit_comps_63; AND63,OR63,XOR63,NOT63,AND_L63,OR_L63,NOT_L63);
reg [2:0] assign AND63 = A63 & B63;
A63,B63,AND63,OR63,XOR63,NOT63,AND_L63,OR_L63,NOT_L63; assign OR63 = A63 | B63;
bit_comp_63 assign XOR63 = A63 ^ B63;
I1(A63,B63,AND63,OR63,XOR63,NOT63,AND_L63,OR_L63,NOT_L63); assign NOT63 = ~(A63);
initial begin
$dumpfile("dump.vcd"); assign AND_L63 = A63 && B63;
$dumpvars(1); assign OR_L63 = A63 || B63;
A63 = 3'b000 ; B63= 3'b000; assign NOT_L63 = !(A63);
endmodule
#20 A63 = 3'b110; B63 = 3'b010;
#20 A63 = 3'b011; B63 = 3'b100;
#20 A63 = 3'b111; B63 = 3'b010;
#20 A63 = 3'b000; B63 = 3'b101;
end
initial #80 $finish;
endmodule

B) 1) Write HDL description in VHDL using dataflow

modeling & predefined operators for 1-bit magnitude
comparator circuit.
testbench code
-- Code your testbench here -- Code your design here
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
entity mc_bit1_63 is entity mc_comp_63 is
end mc_bit1_63; port (A63,B63 : in std_logic ; LESS63,EQUAL63,GREATER63 :
out std_logic);
architecture bit1_63 of mc_bit1_63 is end mc_comp_63 ;
component mc_comp_63 is architecture bit1_ds_63 of mc_comp_63 is
port(A63,B63 : in std_logic ; LESS63,EQUAL63,GREATER63 : begin
out std_logic); LESS63 <= NOT(A63) AND B63;
end component; GREATER63 <= A63 AND NOT(B63);
EQUAL63 <= (NOT(A63) AND B63) NOR (A63 AND
signal A_63,B_63,LESS_63,EQUAL_63,GREATER_63 : std_logic; NOT(B63));
begin end bit1_ds_63;
DUT: mc_comp_63 port map (
A_63,B_63,LESS_63,EQUAL_63,GREATER_63);

A_63 <= '0', '0' after 20 ns , '1' after 40 ns , '0' after 60 ns , '1'
after 80 ns ;
B_63 <= '0', '1' after 20 ns , '0' after 40 ns , '1' after 60 ns , '0'
after 80 ns ;
end bit1_63;

2) Write HDL description in VHDL using dataflow modeling &

predefined operators for 4-bit magnitude comparator
circuit.
 testbench code
-- Code your testbench here -- Code your design here
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all; --use ieee.numeric_std.all;
entity mc_bit4_63 is entity bit4_comp_63 is
end mc_bit4_63 ; port ( A63, B63 : in std_logic_vector(3
architecture bit4_63 of mc_bit4_63 is downto 0); LESS63,EQUAL63,GREATER63 :
component bit4_comp_63 is out std_logic);
port(A63,B63 : in std_logic_vector(3 downto 0); end bit4_comp_63;
LESS63,EQUAL63,GREATER63 : out std_logic); architecture bit4_logic_63 of bit4_comp_63
end component ; is
signal A_63,B_63 : std_logic_vector(3 downto 0); begin
signal LESS_63 , EQUAL_63, GREATER_63 : GREATER63 <= '1' when (A63 > B63) else '0';
std_logic; EQUAL63 <= '1' when (A63 = B63) else '0';
begin LESS63 <= '1' when (A63 < B63) else '0';
DUT :bit4_comp_63 port end bit4_logic_63 ;
map(A_63,B_63,LESS_63,EQUAL_63,GREATER_63);
A_63 <= "0000" after 0 ns, "1000" after 20 ns,
"0111" after 40 ns, "1110" after 60 ns, "0000"
after 80 ns;
B_63 <= "0000" after 0 ns, "0100" after 20 ns,
"1000" after 40 ns, "0100" after 60 ns, "1010"
after 80 ns;
end bit4_63;

3) Write HDL description in VHDL for a circuit which

receives 3-bit inputs A and B and produces results for
A * B where * is various bit-wise operators and logical
operators.

testbench code
-- Code your testbench here -- Code your design here
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
entity bit3_ec_63 is entity bit3_comp_63 is
end bit3_ec_63 ; port (A63,B63 : in std_logic_vector(2 downto 0);
architecture ec_arch_63 of bit3_ec_63 is AND63,OR63,NAND63,NOR63,XOR63,XNOR63,NOT63 : out
component bit3_comp_63 is std_logic_vector(2 downto 0));
port (A63,B63 : in std_logic_vector(2 downto 0); end bit3_comp_63 ;
AND63,OR63,NAND63,NOR63,XOR63,XNOR63,NOT63 : out std_logic_vector(2 architecture bit3_design_63 of bit3_comp_63 is
downto 0)); begin
end component; AND63 <= A63 AND B63; -- logical operator act as bitwise
signal A_63,B_63 : std_logic_vector(2 downto 0); OR63 <= A63 OR B63;
signal AND_63,OR_63,NAND_63,NOR_63,XOR_63,XNOR_63,NOT_63 : NAND63 <= A63 NAND B63;
std_logic_vector(2 downto 0); NOR63 <= A63 NOR B63;
begin XOR63 <= A63 XOR B63;
DUT:bit3_comp_63 XNOR63 <= A63 XNOR B63;
port NOT63 <= NOT(A63);
map(A_63,B_63,AND_63,OR_63,NAND_63,NOR_63,XOR_63,XNOR_63,NOT_63 end bit3_design_63;
);
A_63 <= "000" after 0 ns, "100" after 20 ns, "011" after 40 ns, "111" after 60 ns,
"000" after 80 ns ;
B_63 <= "000" after 0 ns, "010" after 20 ns, "100" after 40 ns, "010" after 60 ns,
"101" after 80 ns ;
end ec_arch_63;

LAB – 6
Aim – Write HDL description in VHDL using structural modeling
for A) Full-Adder circuit B) Full-Subtractor circuit C) Full-
Adder / FullSubtractor circuit using mode control input. Write
testbench and verify their functionality using simulation.

A) VHDL code for Full Adder circuit using structural

modeling.

Circuit –
Code –
testbench code
-- Code your testbench here -- Code your design here
library IEEE;
use IEEE.std_logic_1164.all; ---XOR GATE
entity ec_full_adder_ui_63 is library IEEE;
end ec_full_adder_ui_63 ; use IEEE.std_logic_1164.all;
architecture ec_ui_63 of ec_full_adder_ui_63
is entity xor_gate_63 is
component full_add_63 is port (A63,B63 : in std_logic ; D63 : out
port(A63,B63,Cin63 : in std_logic; std_logic);
SUM63,Cout63 : out std_logic); end xor_gate_63 ;
end component; architecture xor_63 of xor_gate_63 is
signal A63,B63,Cin63,SUM63,Cout63 : begin
std_logic; D63 <= A63 xor B63;
begin end xor_63 ;
DUT : full_add_63 port
map (A63,B63,Cin63,SUM63,Cout63);
A63 <= '0', '1' after 80 ns , '0' after 160 ns ; --AND GATE
B63 <= '0', '1' after 40 ns , '0' after 80 ns, '1' library IEEE;
after 120 ns , '0' after 160 ns ; use IEEE.std_logic_1164.all;

Cin63 <= '0', '1' after 20 ns , '0' after 40 ns , '1' entity and_gate_63 is
after 60 ns , '0' after 80 ns , '1' after 100 ns , '0' port(A63,B63 : in std_logic; D63 : out std_logic);
after 120 ns , '1' after 140 ns ,'0' after 160 ns ; end and_gate_63;
end ec_ui_63; architecture and_63 of and_gate_63 is
begin
D63 <= A63 and B63;
end and_63;

--OR GATE
library IEEE;
use IEEE.std_logic_1164.all;

entity or_gate_63 is
port(A63,B63 : in std_logic ; D63 : out
std_logic);
end or_gate_63;
architecture or_63 of or_gate_63 is
begin
D63 <= A63 or B63 ;
end or_63;

--FULL ADDER

library IEEE;
use IEEE.std_logic_1164.all;

entity full_add_63 is
port(A63, B63, Cin63 : in std_logic; Sum63,
Cout63 : out std_logic);
end full_add_63;
architecture full_adderr_63 of full_add_63 is
signal XOR1, XOR2,AND1,AND2,OR1 : std_logic;
component xor_gate_63
port(A63,B63 : in std_logic; D63 : out std_logic);
end component ;
component and_gate_63
port(A63,B63 : in std_logic; D63 : out std_logic);
end component;
component or_gate_63
port(A63,B63 : in std_logic; D63 : out std_logic);
end component;
begin
XOR1_gate : xor_gate_63 port map
(A63,B63,XOR1);
XOR2_gate : xor_gate_63 port map
(XOR1,Cin63,XOR2);
AND1_gate : and_gate_63 port map
(XOR1,Cin63,AND1);
AND2_gate : and_gate_63 port map (A63, B63,
AND2);
OR1_gate : or_gate_63 port map
(AND1,AND2,OR1);
Sum63 <= XOR2;
Cout63 <= OR1;
end full_adderr_63;
B) VHDL code for Full Subtractor circuit using
structural modeling.

Circuit –

Code –
testbench code
-- Code your testbench here -- Code your design here
library IEEE;
use IEEE.std_logic_1164.all; ---XOR GATE
library IEEE;
use IEEE.std_logic_1164.all;
entity ec_full_sub_ui_63 is library IEEE;
end ec_full_sub_ui_63 ; use IEEE.std_logic_1164.all;entity xor_gate_63
architecture ec_ui_63 of ec_full_sub_ui_63 is is
component full_sub_63 is port (A63,B63 : in std_logic ; D63 : out
port(A63,B63,Cin63 : in std_logic; std_logic);
DIFF63,BORROW63 : out std_logic); end xor_gate_63 ;
end component; architecture xor_63 of xor_gate_63 is
signal A63,B63,Cin63,DIFF63,BORROW63 : begin
std_logic ; D63 <= A63 xor B63;
begin end xor_63 ;
DUT : full_sub_63 port map
(A63,B63,Cin63,DIFF63,BORROW63); --AND GATE
A63 <= '0', '1' after 80 ns , '0' after 160 ns ; library IEEE;
B63 <= '0', '1' after 40 ns , '0' after 80 ns, '1' use IEEE.std_logic_1164.all;
after 120 ns , '0' after 160 ns ;
entity and_gate_63 is
Cin63 <= '0', '1' after 20 ns , '0' after 40 ns , '1' port(A63,B63 : in std_logic; D63 : out std_logic);
after 60 ns , '0' after 80 ns , '1' after 100 ns , '0' end and_gate_63;
after 120 ns , '1' after 140 ns ,'0' after 160 ns ; architecture and_63 of and_gate_63 is
end ec_ui_63; begin
D63 <= A63 and B63;
end and_63;

--OR GATE
library IEEE;
use IEEE.std_logic_1164.all;
entity or_gate_63 is
port(A63,B63 : in std_logic ; D63 : out
std_logic);
end or_gate_63;
architecture or_63 of or_gate_63 is
begin
D63 <= A63 or B63 ;
end or_63;

--NOT GATE
library IEEE;
use IEEE.std_logic_1164.all;
entity not_gate_63 is
port ( A63 : in std_logic; D63 : out std_logic );
end not_gate_63;
architecture not_63 of
not_gate_63 is
begin
D63 <= not(A63);
end not_63;

--FULL SUB

library IEEE;
use IEEE.std_logic_1164.all;

entity full_sub_63 is
port(A63, B63, Cin63 : in std_logic; DIFF63,
BORROW63 : out std_logic);
end full_sub_63;
architecture full_subb_63 of full_sub_63 is
signal
XOR1,XOR2,XOR3,A_NOT,AND1,AND2,OR1 :
std_logic;
component xor_gate_63
port(A63,B63 : in std_logic; D63 : out std_logic);
end component ;
component and_gate_63
port(A63,B63 : in std_logic; D63 : out std_logic);
end component;
component or_gate_63
port(A63,B63 : in std_logic; D63 : out std_logic);
end component;
component not_gate_63
port (A63 : in std_logic; D63 : out std_logic);
end component;
begin
XOR1_gate : xor_gate_63 port map
(A63,B63,XOR1);
XOR2_gate : xor_gate_63 port map
(XOR1,Cin63,XOR2);
NOT1_gate: not_gate_63 port map (A63 ,
A_NOT);
XOR3_gate : xor_gate_63 port map
(B63,Cin63,XOR3);
AND1_gate : and_gate_63 port map (A_NOT,
XOR3, AND1);
AND2_gate : and_gate_63 port map (B63,
Cin63, AND2);
OR1_gate : or_gate_63 port map
(AND1,AND2,OR1);
DIFF63 <= XOR2;
BORROW63 <= OR1;
end full_subb_63;
 LAB 7

Aim : A. Write HDL description using Verilog in (1) Boolean-Equations, (2) Structural Method

B. Write HDL description using VHDL in (1) Boolean-Equations, (2) Structural Method (3) with-select-
when Data flow, (4) w

hen-else Data Flow and

TESTBENCH CODE
// Test Bench
`timescale 1ns/1ps // Verilog Decoder, boolean equation
module TestBench(); `timescale 1ns/1ps
reg A, B; module Decoder(output [3:0] d, input A, B);
wire [3:0] d; assign d[0] = ~A && ~B;
Decoder I1 (d, A, B); assign d[1] = A && ~B;
initial begin assign d[2] = ~A && B;
$dumpfile("dump.vcd"); assign d[3] = A && B;
$dumpvars(1); endmodule
A = 1'b0; B = 1'b0;
#10 A = 1'b0; B = 1'b1;
#10 A = 1'b1; B = 1'b0;
#10 A = 1'b1; B = 1'b1;
#10 A = 1'b0; B = 1'b0;
end
initial #50 $finish;
endmodule
 testbench code
// Test Bench `timescale 1ns/1ps
`timescale 1ns/1ps module Decoder(output [3:0] d, input a, b);
module TestBench(); wire not_a, not_b;
reg a, b; not(not_a, a);
wire [3:0] d, not_a, not_b; not(not_b, b);
Decoder I1 (d, a, b); and(d[0], not_a, not_b);
initial begin and(d[2], not_a, b);
$dumpfile("dump.vcd"); and(d[1], a, not_b);
$dumpvars(1); and(d[3], a, b);
a = 1'b0; b = 1'b0; endmodule
#10 a = 1'b0; b = 1'b1;
#10 a = 1'b1; b = 1'b0;
#10 a = 1'b1; b = 1'b1;
#10 a = 1'b0; b = 1'b0;
end
initial #50 $finish;
endmodule

Code: B. VHDL

testbench code
-- Code your testbench here -- VHDL Decoder, Boolean Equation
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity Test is entity Decoder is

end Test; port(
d: out std_logic_vector(3 downto 0);
architecture Test_Decoder of Test is a, b: in std_logic
component Decoder is );
port( end Decoder;
d: out std_logic_vector(3 downto 0);
a, b: in std_logic architecture Arc_Decoder of Decoder is
); begin
end component; d(0) <= not(a) and not(b);
d(1) <= not(a) and b;
signal d: std_logic_vector(3 downto 0); d(2) <= a and not(b);
signal a, b: std_logic; d(3) <= a and b;
begin end Arc_Decoder;
DUT: Decoder port map (d, a, b);
a <= '0', '1' after 20 ns, '0' after 40 ns;
b <= '0', '1' after 10 ns, '0' after 20 ns, '1' after
30 ns, '0' after 40 ns;
end Test_Decoder;
testbench code
-- Test Bench -- VHDL, Decoder, Structural
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity test is entity and34 is

end test; port (
z: out std_logic;
architecture arc_test of test is x, y: in std_logic
component decoder );
port( end and34;
d: out std_logic_vector(3 downto 0);
a, b: in std_logic architecture AND34 of and34 is
); begin
end component; z <= x and y;
signal d:std_logic_vector(3 downto 0); end AND34;
signal a, b: std_logic;
begin library IEEE;
DUT: decoder port map (d, a, b); use IEEE.std_logic_1164.all;
a <= '0', '1' after 20 ns, '0' after 40 ns;
b <= '0', '1' after 10 ns, '0' after 20 ns, '1' after entity not34 is
30 ns, '0' after 40 ns; port (
end arc_test; y: out std_logic;
x: in std_logic
);
end not34;

architecture NOT34 of not34 is

begin
y <= not(x);
end NOT34;

library IEEE;
use IEEE.std_logic_1164.all;

entity decoder is
port (
d: out std_logic_vector(3 downto 0);
a, b: in std_logic
);
end decoder;

architecture arc_decoder of decoder is

component and34
port (
z: out std_logic;
x, y: in std_logic
);
end component;
component not34
port (
 y: out std_logic;
x: in std_logic
);
end component;
signal not_a, not_b: std_logic;
begin
NA: not34 port map (not_a, a);
NB: not34 port map (not_b, b);
D0: and34 port map (d(0), not_a, not_b);
D1: and34 port map (d(1), not_a, b);
D2: and34 port map (d(2), a, not_b);
D3: and34 port map (d(3), a, b);
end arc_decoder;

Test-bench 4. when-else

-- Test Bench -- VHDL, decoder, when-else

library IEEE; library IEEE;

use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity test is entity decoder is

end test; port(

d: out std_logic_vector(3 downto 0);

architecture arc_test of test is a: in std_logic_vector(1 downto 0)

component decoder );

port( end decoder;

d: out std_logic_vector(3 downto 0);

a: in std_logic_vector(1 downto 0) architecture arc_decoder of decoder is

); begin

end component; d <= "0001" when (a<="00") else

signal d:std_logic_vector(3 downto 0); "0010" when (a<="01") else

signal a: std_logic_vector(1 downto 0); "0100" when (a<="10") else

begin "1000" when (a<="11") else

DUT: decoder port map (d, a); "0000";

a <= "00", "01" after 10 ns, "10" after 20 ns, "11" end arc_decoder;
after 30 ns, "00" after 40 ns;

end arc_test;

Output for VHDL (when-else):

 Lab 8

Aim : Part 1: Write HDL description for Binary to Gray,

A. Verilog in (1) Boolean-Equations, (2) Structural Method

B. VHDL in (1) Boolean-Equations, (2) Structural Method, (3) with-select-when,

(4) when-else

Part 2: Write HDL description for Gray to Binary,

A. Verilog in (1) Boolean-Equations, (2) Structural Method

B. VHDL in (1) Boolean-Equations, (2) Structural Method, (3) with-select-when,

(4) when-else

Code Part 1:

A. In Verilog

Test-bench 1. Boolean-Equations

// Test-bench // Binary to Gray, Verilog Boolean Equation

`timescale 1ns/1ps `timescale 1ns/1ps

module test(); module btog (output [3:0] g, input [3:0] b);

reg [3:0] b; assign g[3] = b[3];

wire [3:0] g; assign g[2] = b[3] ^ b[2];

btog I1 (g, b); assign g[1] = b[2] ^ b[1];

initial begin assign g[0] = b[1] ^ b[0];

$dumpfile("dump.vcd"); endmodule

$dumpvars(1);

b = 4'b0000;

#10 b = 4'b0011;

#10 b = 4'b0110;

#10 b = 4'b1011;
 #10 b = 4'b1100;

#10 b = 4'b1111;

end

initial #60 $finish;

endmodule

Output:

Test-bench 2. Structural Method

// Test-bench // Verilog, Binary to Gray, Structural Method

`timescale 1ns/1ps module btog (output [3:0] g, input [3:0] b);

module test(); buf(g[3], b[3]);

reg [3:0] b; xor(g[2], b[3], b[2]);

wire [3:0] g; xor(g[1], b[2], b[1]);

btog I1 (g, b); xor(g[0], b[1], b[0]);

initial begin endmodule

$dumpfile("dump.vcd");

$dumpvars(1);

b = 4'b0000;

#10 b = 4'b0011;

#10 b = 4'b0110;

#10 b = 4'b1011;

#10 b = 4'b1100;

#10 b = 4'b1111;

end

initial #60 $finish;

endmodule

Output:

B. In VHDL

Test-bench 1. Boolean-Equations

-- Code your testbench here -- VHDL, binary to gray, boolean equation

library IEEE; library IEEE;

use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity test is entity btog is

end test; port(

g: out std_logic_vector(3 downto 0);

architecture TEST of test is b: in std_logic_vector(3 downto 0)

component btog );

port( end btog;

g: out std_logic_vector(3 downto 0);

b: in std_logic_vector(3 downto 0) architecture BTOG of btog is

); begin

end component; g(3) <= b(3);

g(2) <= b(3) xor b(2);

signal g, b: std_logic_vector(3 downto 0); g(1) <= b(2) xor b(1);

begin g(0) <= b(1) xor b(0);

DUT: btog port map(g, b); end BTOG;

b <= "0000", "0011" after 10 ns, "0110" after 20 ns,
"1011" after 30 ns, "1100" after 40 ns, "1111" after
50 ns;

end TEST;

Output:

Test-bench 2. Structural Method

-- Code your testbench here -- VHDL, binary to gray, Structure

library IEEE; library IEEE;

use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity test is entity buf34 is

end test; port(

y: out std_logic;

architecture TEST of test is x: in std_logic

component btog );

port( end buf34;

g: out std_logic_vector(3 downto 0);

b: in std_logic_vector(3 downto 0) architecture BUF34 of buf34 is

); begin

end component; y <= x;

end BUF34;

signal g, b: std_logic_vector(3 downto 0);

begin library IEEE;

DUT: btog port map(g, b); use IEEE.std_logic_1164.all;

b <= "0000", "0011" after 10 ns, "0110" after 20 ns,
"1011" after 30 ns, "1100" after 40 ns, "1111" after
entity xor34 is
50 ns;
port(
end TEST;
z: out std_logic;

x, y: in std_logic

);

end xor34;

architecture XOR34 of xor34 is

begin

z <= x xor y;

end XOR34;

library IEEE;

use IEEE.std_logic_1164.all;

entity btog is

port(

g: out std_logic_vector(3 downto 0);

b: in std_logic_vector(3 downto 0)

);

end btog;

architecture BTOG of btog is

component buf34

port(

y: out std_logic;

x: in std_logic);

end component;

component xor34
 port(

z: out std_logic;

x, y: in std_logic

);

end component;

begin

G3: buf34 port map(g(3), b(3));

G2: xor34 port map(g(2), b(3), b(2));

G1: xor34 port map(g(1), b(2), b(1));

G0: xor34 port map(g(0), b(1), b(0));

end BTOG;

Output:

Test-bench 3. with-select-when

-- Code your testbench here -- VHDL, binary to gray, with-select-when

library IEEE; library IEEE;

use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity test is entity btog is

end test; port(

g: out std_logic_vector(3 downto 0);

architecture TEST of test is b: in std_logic_vector(3 downto 0)

component btog );

port( end btog;

g: out std_logic_vector(3 downto 0);

b: in std_logic_vector(3 downto 0) architecture BTOG of btog is

); begin

end component; with b select

g <= "0000" when "0000",

signal g, b: std_logic_vector(3 downto 0); "0001" when "0001",

begin "0011" when "0010",

DUT: btog port map(g, b); "0010" when "0011",

b <= "0000", "0011" after 10 ns, "0110" after 20 ns, "0110" when "0100",
"1011" after 30 ns, "1100" after 40 ns, "1111" after
"0111" when "0101",
50 ns;
"0101" when "0110",
end TEST;
"0100" when "0111",

"1100" when "1000",

"1101" when "1001",

"1111" when "1010",

"1110" when "1011",

"1010" when "1100",

"1011" when "1101",

"1001" when "1110",

"1000" when OTHERS;

end BTOG;

Output:
Test-bench 4. when-else

-- Code your testbench here -- VHDL, binary to gray, when-else

library IEEE; library IEEE;

use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity test is entity btog is

end test; port(

g: out std_logic_vector(3 downto 0);

architecture TEST of test is b: in std_logic_vector(3 downto 0)

component btog );

port( end btog;

g: out std_logic_vector(3 downto 0);

b: in std_logic_vector(3 downto 0) architecture BTOG of btog is

); begin

end component; g <= "0000" when (b <= "0000") else

"0001" when (b <= "0001") else

signal g, b: std_logic_vector(3 downto 0); "0011" when (b <= "0010") else

begin "0010" when (b <= "0011") else

DUT: btog port map(g, b); "0110" when (b <= "0100") else

b <= "0000", "0011" after 10 ns, "0110" after 20 ns, "0111" when (b <= "0101") else
"1011" after 30 ns, "1100" after 40 ns, "1111" after
"0101" when (b <= "0110") else
50 ns;
"0100" when (b <= "0111") else
end TEST;
"1100" when (b <= "1000") else

"1101" when (b <= "1001") else

"1111" when (b <= "1010") else

"1110" when (b <= "1011") else

"1010" when (b <= "1100") else

"1011" when (b <= "1101") else

"1001" when (b <= "1110") else

"1000";
 end BTOG;

Output:

Code Part 2:

A. In Verilog

Test-bench 1. Boolean-Equations

// Test-bench // Gray to Binary, Verilog Boolean Equation

`timescale 1ns/1ps `timescale 1ns/1ps

module test(); module gtob (output [3:0] b, input [3:0] g);

reg [3:0] g; assign b[3] = g[3];

wire [3:0] b; assign b[2] = b[3] ^ g[2];

gtob I1 (b, g); assign b[1] = b[2] ^ g[1];

initial begin assign b[0] = b[1] ^ g[0];

$dumpfile("dump.vcd"); endmodule

$dumpvars(1);

g = 4'b0000;

#10 g = 4'b0010;

#10 g = 4'b0101;

#10 g = 4'b1110;
 #10 g = 4'b1010;

#10 g = 4'b1000;

end

initial #60 $finish;

endmodule

Output:

Test-bench 2. Structural Method

// Test-bench // Verilog, Binary to Gray, Structural Method

`timescale 1ns/1ps module gtob (output [3:0] b, input [3:0] g);

module test(); buf(b[3], g[3]);

reg [3:0] g; xor(b[2], b[3], g[2]);

wire [3:0] b; xor(b[1], b[2], g[1]);

gtob I1 (b, g); xor(b[0], b[1], g[0]);

initial begin endmodule

$dumpfile("dump.vcd");

$dumpvars(1);

g = 4'b0000;

#10 g = 4'b0010;

#10 g = 4'b0101;

#10 g = 4'b1110;

#10 g = 4'b1010;

#10 g = 4'b1000;

end
 initial #60 $finish;

endmodule

Output:

B. In VHDL

Test-bench 1. Boolean-Equations

-- Code your testbench here -- VHDL, gray to binary, boolean equation

library IEEE; library IEEE;

use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity test is entity gtob is

end test; port(

b: inout std_logic_vector(3 downto 0);

architecture TEST of test is g: in std_logic_vector(3 downto 0)

component gtob );

port( end gtob;

b: inout std_logic_vector(3 downto 0);

g: in std_logic_vector(3 downto 0) architecture GTOB of gtob is

); begin

end component; b(3) <= g(3);

b(2) <= b(3) xor g(2);

signal g, b: std_logic_vector(3 downto 0); b(1) <= b(2) xor g(1);

begin b(0) <= b(1) xor g(0);

DUT: gtob port map(b, g); end GTOB;

g <= "0000", "0010" after 10 ns, "0101" after 20 ns,
"1110" after 30 ns, "1010" after 40 ns, "1000" after
50 ns;

end TEST;

Output:

Lab 9
Aim : Task 1:Write HDL Description for 4x1 Multiplexer in Verilog
Behavior Method (a) If-else conditional, (b) Case conditional.
Task 2: Write HDL Description for 4x1 Multiplexer in VHDL using (a)
withselect-when, (b) when-else, (c) Behavior Method, (d) If-else
conditional, (e) Case conditional.

Code:
Test-bench for Verilog
// Test Bench `timescale 1ns/1ps module test; wire Mux_Out; reg
[3:0] d; reg [1:0] s;
mux I1 (Mux_out, d, s); initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
d = 4'b0000; s = 2'b00; #10 d = 4'b1000; s = 2'b00;
#10 d = 4'b1100; s = 2'b01;
#10 d = 4'b1110; s = 2'b10; #10 d = 4'b1111; s = 2'b11; end
initial #50 $finish;
endmodule

Verilog (a) If-else conditional Verilog (b) case statement

// Verilog, If else conditionals // Verilog, 4x1 mux using case statement
`timescale 1ns/1ps `timescale 1ns/1ps
module mux(output reg Mux_Out, input module mux(output reg Mux_Out, input
[3:0] d, input [1:0] s); [3:0] d, input [1:0]s);
always @(*) begin always @(*) begin
if (s == 2'b00) case(s)
Mux_Out = d[0]; 2'b00: Mux_Out = d[0];
else if (s == 2'b01) 2'b01: Mux_Out = d[1];
Mux_Out = d[1]; 2'b10: Mux_Out = d[2];
else if (s == 2'b10) 2'b11: Mux_Out = d[3];
Mux_Out = d[2]; endcase
else end
Mux_Out = d[3]; endmodule
end endmodule

Output:
Test-bench VHDL
-- Code your testbench here
library IEEE; use
IEEE.std_logic_1164.all;

entity test is
end test;

architecture TEST of test is

component mux
port(
Mux_Out: out std_logic; d: in
std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0)
);
end component;
signal Mux_Out: std_logic; signal d:
std_logic_vector(3 downto 0); signal s:
std_logic_vector(1 downto 0); begin
DUT: mux port map (Mux_Out, d, s);
s <= "00", "01" after 20 ns, "10" after 30 ns, "11" after 40 ns, "00" after 50 ns;

d <= "0000", "1000" after 10 ns, "1100" after 20

ns, "1110" after 30 ns, "1111" after
40 ns, "0000" after 50 ns; end TEST;

VHDL with with-select-when VHDL when-else

-- VHDL, Mux using with-select-when -- VHDL mux using when-else
library IEEE; use library IEEE; use
IEEE.std_logic_1164.all; IEEE.std_logic_1164.all;

entity mux is entity mux is

port( port(
Mux_Out: out std_logic; d: in Mux_Out: out std_logic; d: in
std_logic_vector(3 downto 0); std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0) s: in std_logic_vector(1 downto 0)
); );
end mux; end mux;

architecture MUX of mux is architecture MUX of mux is

begin with s select begin
Mux_Out <= d(0) when "00", Mux_Out <= d(0) when (s <= "00") else
d(1) when "01", d(1) when (s <= "01") else
d(2) when "10", d(2) when (s <= "10") else
d(3) when "11", d(3) when (s <= "11") else
'0' when others; '0';
end MUX; end MUX;

Output:

if-else statement case statement

-- VHDL mux using behavior method -- VHDL, mux using behaviore, case
with 'if else conditions' statements library IEEE; use
library IEEE; IEEE.std_logic_1164.all;
use IEEE.std_logic_1164.all; entity
mux is entity mux is
port( port(
Mux_Out: out std_logic; d: in Mux_OUt: out std_logic; d: in
std_logic_vector(3 downto 0); std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0) s: in std_logic_vector(1 downto 0)
); );
end mux; end mux;

architecture MUX of mux is architecture MUX of mux is

begin process(d, s) begin begin process (d, s)
if s = "00" then begin
Mux_Out <= d(0); case(s) is
elsif s = "01" then when "00" => Mux_Out <= d(0); when
Mux_Out <= d(1); "01" => Mux_Out <= d(1); when "10"
elsif s = "10" then => Mux_Out <= d(2); when "11" =>
Mux_Out <= d(2); Mux_Out <= d(3); when others =>
else Mux_Out <= '0';
Mux_Out <= d(3); end case;
end if; end end
process; process;
end MUX; end MUX;

Output:

Conclusion: From the experiment we learn about Multiplexer and Implement

in Verilog/VHDL.
 Lab 10
Aim :Task 1: Write HDL description for SR latch with nor VHDL and
Verilog. Task 2: Write HDL description for D, JK, T flip flop in VHDL and
Verilog.

Code:
Test-bench
// Test Bench `timescale 1ns/1ps module test(); wire q, q_not;
reg s, r;
sr_latch I1 (q, q_not, s, r); initial begin
$dumpfile("dump.vcd");
$dumpvars(1); s = 1'b0; r = 1'b0; #10 s = 1'b0; r = 1'b1;
#10 s = 1'b1; r = 1'b0; #10 s = 1'b1; r = 1'b1;
end
initial #40 $finish;
endmodule

Data Flow Method Structural Method

// SR Latch with nor verilog // Verilog, SR Latch with nor verilog
`timescale 1ns/1ps `timescale 1ns/1ps;
module sr_latch(output q, q_not, input s, module sr_latch(output q, q_not, input s,
r); r);
assign q_not = ~(s|q); nor(q_not, s, q);
assign q = ~(r|q_not); nor(q, r, q_not);
endmodule endmodule
Output:
Test-bench
-- test bench library IEEE; use
IEEE.std_logic_1164.all;

entity test is end test;

architecture TEST of test is component

sr_latch port( q: inout std_logic; s, r: in
std_logic
);
end component;

signal q, q_not, s, r: std_logic; begin

DUT: sr_latch port map (q, s, r); s <= '0', '1' after 20 ns,
'0' after 40 ns;
r <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns; end TEST;

Data flow method Structural method

-- VHDL,SR Latch Nor Data flow -- VHDL, SR Latch structural method
library IEEE; use library IEEE; use
IEEE.std_logic_1164.all;
IEEE.std_logic_1164.all;
entity nor34 is
entity sr_latch is port( z: out
port( q: inout std_logic;
std_logic; s, r: in x, y: in std_logic
std_logic );
); end nor34;
end sr_latch; architecture SR_Latch architecture NOR34 of nor34 is
of sr_latch is begin
z <= not (x or y);

signal q_not: std_logic; end NOR34;

begin q <= r nor library IEEE; use
q_not; q_not <= IEEE.std_logic_1164.all;
s nor q; end
SR_Latch; entity sr_latch is
port( q: inout
std_logic; s, r: in
std_logic
);
end sr_latch;

architecture SR_Latch of sr_latch is

component
nor34 port( z:
out std_logic;
x, y: std_logic
);
end component;

signal q_not: std_logic;

begin
Q34: nor34 port map (q, r, q_not);
Q_NOT34: nor34 port map (q_not, s, q);
end SR_Latch;
Output:
Test-bench D flip flop in Verilog
// Test Bench D flip flop // Verilog Behavior Method
`timescale 1ns/1ps `timescale 1ns/1ps
module test(); module D_flip_flop(output reg Q, input
wire Q; rstn, clk, d);
reg rstn, clk, d; always@(posedge clk or negedge rstn)
D_flip_flop I1 (Q, rstn, clk, d); if (!rstn)
always begin Q <= 0;
#5 clk = ~clk; else
end Q <= 0;
initial begin endmodule;
$dumpfile("dump.vcd");
$dumpvars(1);
rstn = 0; #10
rstn = 1; clk =
0;
d = 0; #5 d = 1; #10 d = 0; #5 d = 1;
#10 d = 0;
end
initial #50 $finish;
endmodule
Output:
Test-bench JK flip flop in Verilog
// Test Bench JK Flip Flop in Verilog // JK Flip Flop in Verilog Behavior
`timescale Method
1ns/1ps module `timescale 1ns/1ps
test(); wire q, module jk_flip_flop(output reg q, q_not,
q_not; reg j, k, input j, k, clk);
clk; always @(posedge clk) begin
jk_flip_flop I1 (q, q_not, j, k, clk); initial if (j == 1 && k == 1)begin q
begin <= ~q;
$dumpfile("dump.vcd");
$dumpvars(1); q_not <= ~q_not;
clk = 0; end
forever #5 clk = ~clk; else if (j == 1) begin
end initial begin j = q <= 1; q_not = 0;
0; k = 1'b0; #10 j = 0; end
k = 1; else if (k == 1) begin
#10 j = 1; k = 0; q <= 0;
#10 j = 1; k = 1; q_not <= 1; end
#10 j = 0; k = 0; end else begin q <=
initial #50 $finish; q; q_not <=
endmodule q_not;
end
end
endmodule

Output:
Test-bench T flip flop in Verilog
// Test Bench for T Flip Flop in Verilog // T flip flop in Verilog Behavior method
`timescale 1ns/1ps `timescale 1ns/1ps
module test(); module T_flip_flop(output reg q, q_not,
wire q, q_not; reg input clk, rstn, t);
clk, rstn, t; always@(posedge clk)
T_flip_flop I1 (q, q_not, clk, rstn, t); begin if (!rstn) q
initial begin <= 0;
$dumpfile("dump.vcd");
$dumpvars(1); else
clk = 0; q <= (t ? ~q:q);
forever #5 clk = ~clk; end
end initial begin rstn assign q_not = ~q;
= 1; t = 0; #10 t = 1; endmodule
#5 rstn = 0; #5 rstn = 1;
#5 t = 1; #5 t = 0;
#5 rstn = 0; #5 rstn = 1;
#5 t = 1; #5 t = 0; #5 t = 1; #5 t = 0;
end
initial #50 $finish;
endmodule

Output:
Test-bench D Flip Flop in VHDL
-- Test Bench library IEEE; -- VHDL, D FF library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity test is entity D_flip_flop is

end test; port( q, q_not: out
std_logic;
architecture TEST of test is d, clk: in std_logic
component D_flip_flop );
port( end D_flip_flop;
q, q_not: out std_logic;

d, clk: in std_logic architecture D_FF of D_flip_flop is

); begin process (d, clk)
end component; begin
if clk'event and clk='1' then
signal q, q_not, clk, d: std_logic; q <= d; q_not
<= not d; end
begin if; end process;
DUT: D_flip_flop port map (q, q_not, clk, end D_FF;
d);
clk <= '0', '1' after 10 ns, '0' after 20 ns,
'1' after 30 ns, '0' after 40 ns;
d <= '0','0' after 10 ns, '1' after 20 ns,'1'
after 30 ns, '0' after 40 ns; end TEST;

Output:
Test-bench JK Flip Flop in VHDL
-- Test Bench library IEEE; -- VHDL, JK FF library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity test is entity jk_flip_flop is

end test; port( q, q_not: inout
std_logic; j, k, clk: in
architecture TEST of test is std_logic
component jk_flip_flop );
port( q, q_not: inout end jk_flip_flop; architecture JK_FF
std_logic; j, k, clk: in of jk_flip_flop is
std_logic

); begin
end component; process (j, k, clk)
signal q, q_not, j, k, clk: std_logic; begin
if rising_edge (clk) then
begin if j = '1' and k = '1' then
DUT: jk_flip_flop port map (q, q_not, j, q <= not(q); q_not <=
k, clk); clk <= '0', '1' after 5 ns, '0' after not (q_not); elsif j = '1'
10 ns, '1' after 15 ns, '0' after 20 ns, '1' then q <= '1'; q_not <=
after 25 ns, '0' after 30 ns, '1' after 35
'0'; elsif k = '0' then q
ns, '0' after 40 ns;
<= '0'; q_not <= '1'; end
j <= '0', '1' after 20 ns, '0' after 40 ns; k
if; end if; end process;
<= '0', '1' after 10 ns, '0' after 20 ns, '1'
end JK_FF;
after 30 ns, '0' after 40 ns; end TEST;

Output:
Test-bench T Flip Flop in VHDL
-- Test Bench library IEEE; use -- VHDL, T FF library IEEE; use
IEEE.std_logic_1164.all; IEEE.std_logic_1164.all;

entity test is end test; entity t_flip_flop is port(

 q, q_not: out std_logic;
t, clk: in std_logic
architecture TEST of test is );
component t_flip_flop end t_flip_flop;
port( q, q_not: out
std_logic; t, clk: in architecture T_FF of t_flip_flop is signal
std_logic tmp : std_logic := '0';
); begin process
(t, clk)
end component;
begin
signal q, q_not, t, clk: std_logic; if rising_edge(clk) then
begin if t = '1' then
DUT: t_flip_flop port map (q, q_not, t, tmp <= not tmp;
clk); clk <= '0','1' after 5 ns, '0' after 10 end if; end if; q
ns, '1' after 15 ns, '0' after 20 ns, '1' after <= tmp; q_not <=
25 ns,'0' after 30 ns,'1' after 35 ns, '0' not tmp; end
after 40 ns; process; end
T_FF;
t <= '0', '1' after 10 ns, '0' after 20 ns, '1'
after 30 ns, '0' after 40 ns;

end TEST;
Output:

Conclusion: From the experiment we learn about Latch and Flip Flop. Also
Implement them in Verilog/VHDL.
 Lab 11

Aim : Task 1: Write HDL description for 4 bit binary up counter using if
statement in Verilog Behavior Method
Task 2: Write HDL description for 3 bit binary up counter using case
statement in VHDL Behavior Method Code:
Test-bench 4 bit binary up counter
// Test Bench // Verilog 4bit up counter
`timescale `timescale 1ns/1ps
1ns/1ps module module counter (output reg [3:0]
test; wire [3:0] count, input clk, rstn);
count; reg clk,
rstn; always @(posedge clk) begin
counter I1 (count, clk, rstn); if (!rstn) begin count <=
4'h0; end else begin
initial begin clk count <= count + 1'b1;
= 0; rstn = 0; end
#5 rstn = 1; end
#70 $finish; endmodule
end
always #2 clk = ~clk;
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule
Output:
Test-bench 3-bit up counter in VHDL
-- Test Bench library IEEE; -- VHDL, 3 bit up counter
use IEEE.std_logic_1164.all; library IEEE; use
IEEE.std_logic_1164.all;
entity test is
end test; entity counter is
port(
architecture TEST of test is count: out std_logic_vector(2 downto 0);
component counter clk, rstn: in std_logic
port( );
count: out std_logic_vector(2 downto 0); end counter;
clk, rstn: in std_logic
); architecture COUNTER of counter is
end component; signal cnt: std_logic_vector(2 downto
signal count: std_logic_vector(2 downto 0) := "000";
0); signal clk, rstn: std_logic := '0'; begin
constant clk_period : time := 10 process(clk, rstn)
ns; begin

if rstn = '1' then

begin
cnt <= "000";
DUT: counter port map (count, clk, rstn);
elsif rising_edge(clk) then
process begin
case cnt is
while now < 250 ns loop
when "000" => cnt <= "001";
clk <= not clk; wait for
when "001" => cnt <= "010";
clk_period / 2;
when "010" => cnt <= "011";
end loop;
when "011" => cnt <= "100";
wait; end
when "100" => cnt <= "101";
process;
when "101" => cnt <= "110";
when "110" => cnt <= "111";
process begin rstn
when others => cnt <= "000";
<= '1'; wait for
end case; end if; end
clk_period;
process; count <= cnt;
rstn <= '0';
end COUNTER;
wait for 50 ns;

rstn <= '1'; wait for clk_period;

rstn <= '0'; wait for 180 ns; wait; end
process; end TEST;
Output:

Conclusion: From the experiment we learn about Counters and Implement

Them in Verilog/VHDL.