Lecture – Optical Lithography

What is photolithography?
➢ A series of process steps to transfer layout (design) from
masks to the wafer surface by means of light and a
photosensitive film
➢ This is the most important process step in IC manufacturing
➢ The ability to fabricate smaller and smaller features is mainly
attributed to the advances in lithography
➢ Lithography systems are the most expensive tools in a
modern FAB
▪ The cost of the litho tool that is being currently used is
~20 million USD. The next generation tool is expected to
be in the range of 100 million USD.
➢ The interface between process technologies and circuit
designers traditionally happen at this step
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Why lithography is challenging?

Pull-Down (NFET): M1, M3

Pass-Gate (NFET): M5, M6
Pull-Up (PFET): M2, M4

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Active layer, 0.12µm2 bitcell (28nm)
91nm

64nm
51nm
144nm

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Gate layer, 0.12µm2 bitcell (28nm)

30nm
54nm
96nm

For many layers, we

have to pattern very
small dimensions
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28nm CMOS technology

❖ HKMG CMOS Technology

❖ 60 masks
❖ 10-12 critical masks
❖ 1390 process steps
❖ 480 (35%) process steps related to lithography

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The basic concept

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CMOS inverter layout

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Active (RX) mask

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N-well (NW) mask

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Gate (PC) mask

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Contact mask

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Metal1 mask

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Photomasks for Semiconductors

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Manufacturing process of a Photomask
Source - http://www.toppan.co.jp

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Mask Materials
➢ Opaque films
Chromium (composite film with nitrogen, oxygen plus other
elements)
▪ film composition varies through its depth for different
characteristics, for example, good adhesion to substrate,
maximum attenuation in centre, antireflective surface at
top etc.
▪ film thickness ~ 100nm
Molybdenum Silicide (MoSi)
▪ for special applications such as phase shift masks
▪ film thickness ~ 80-100nm

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Photoresists
➢ Photoresists (PR) are photosensitive, etch-resistant transfer
agents
➢ PR consist of three components
▪ Photoactive compound (light absorbing group)
▪ Base resin (mechanical properties)
▪ Solvent system (liquid)
➢ PR is mainly used as mask for transferring pattern into underlying
layer by means of etching (wet/dry) or implantation (stable during
implantation process)
➢ Thickness of photoresist is typically 0.3-2 µm
➢ Positive photoresist – exposed photoresist removed during
development
➢ Negative photoresist – exposed resist polymerizes (hardens) so
unexposed photoresist is removed during developement
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Positive and Negative Photoresist

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Positive PR (DNQ-Novolac)

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PR Comparison

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Photolithography process sequence

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Photolithography process sequence
Prepare Wafer

Coat with Photoresist

Prebake

Align and Expose

Post-Exposure Bake

Develop

Etch, Implant, etc.

Strip Resist

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Photolithography process (flowchart)

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Photolithography process (gate etch)

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Photolithography process (gate etch)

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Lithography cluster or cell
UP

Illumination

Mask

Objective Lens

Coat Prebake Exposure PEB Development

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Photolithography – Surface preparation

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Application of PR

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 Application of PR
1.0

Resist Thickness (microns)

Spin Time Thickness α w0.5
 0.9

0.8
Spin Speed

High viscosity
0.7
Ramp
0.6
Spread
0.5
Time
 Low viscosity
0.4

Time 0.3
Dispense Resist
2000 2500 3000 3500 4000 4500 5000
Spin Speed (rpm)

➢ Speeds less than 1000rpm are harder to control and do not

produce uniform films
➢ If the spin speed is too high, turbulent airflow at the edge of the
wafer will limit uniformity
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Application of PR
Surface
Tension
Centrifugal

Frictional

Edge bead within

the outer 1-2mm
Wafer of the wafer

➢ The existence of edge bead is detrimental to the cleanliness of the

wafers
➢ Within the spin coat chamber and immediately after the resist spin
coating is complete, a stream of solvent (called EBR) is directed at
the edge of the wafer when it slowly spins. The resist is dissolved at
the edge and over the outer 1-2mm of the wafer surface
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Chemical removal of an edge bead

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Optical removal of an edge bead

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Lithography cluster or cell
UP

Illumination

Mask

Objective Lens

Coat Prebake Exposure PEB Development

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Mask alignment and Exposure

➢ Contact printing
➢ Proximity printing
➢ Projection printing

Contact Printing Proximity Printing

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Contact and Proximity Printing

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Disadvantages of Proximity Printing

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Projection Printing

Projection Printing

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Projection Printing – Wafer Scanner

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Projection Printing – Step/Scan and Repeat

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Step and Repeat imaging

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Step and Scan imaging

Wafer Slit
Pattern of
Exposure
Fields

Scan
Direction

Single Exposure Field

The step-and-scan approach uses a fraction of a normal

stepper field (for example 26 X 8 mm), then scans this field in
one direction to expose the entire 4X reduction mask
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Projection Printing – Step/Scan and Repeat

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Reduction projection optical lithography system

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Reduction projection optical lithography system

Mask

Light Source

Condenser Lens Objective Lens

Wafer

Block diagram of a generic projection imaging system

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Imaging tool basic architecture and the real tool

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 Table 1.2 The change in projection tool specifications over time.

First Stepper Immersion Scanner

(1978) (2006)

Wavelength 436 nm 193 nm

Numerical Aperture 0.28 1.2

Field Size 10 mm X 10 mm 26 mm X 33 mm

Reduction Ratio 10 4

Wafer size 4” (100 mm) 300 mm

Throughput 20 wafers per hour 120 wafers per hour

(0.44 cm2/s) (24 cm2/s)

The modern high performance imaging systems are incredibly complex and
costly
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The Diffraction of light
➢ Diffraction is the ability of waves to bend around obstacles.
➢ Diffraction effect depends upon the size of the obstacle. We can observe
diffraction if the size of the obstacle is comparable to the wavelength of
light.

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The Imaging basics - Diffraction

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The Imaging basics - Diffraction

Fraunhofer
Diffraction
Region
(z » w2/)

Kirchhoff Fresnel
Diffraction Region Diffraction
Region
(z > /2)
(z » w)

Comparison of the diffraction ‘regions’ where various approximations

become accurate. Diffraction is for a slit of width w illuminated by light of
wavelength l, and z is the distance away from the mask.
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The Imaging basics - Diffraction
mask

1
tm(x)
0

Tm(fx) fx
0 0

Two typical mask patterns, an isolated space and an array of equal lines
and spaces, and the resulting Fraunhofer diffraction patterns assuming
normally incident plane wave illumination. Both tm and Tm represent electric
fields.
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The Imaging basics - Diffraction
0.5
Amplitude

3 3
−
p p
fx
2 1 1 2
− − 0
p p p p

❖ For image formation you need to

capture at least two diffraction
orders
❖ The capture of more diffraction
order by the objective lens will
significantly improve the image
quality
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The Imaging basics - Diffraction
aperture

Collection lens

Collection lens

Collection lens

Collection lens

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Example of diffraction order loss

2% Freqs. 6% Freqs. 14% Freqs.

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The Imaging basics - Diffraction

Fourier Transform

Inv Fourier Transform

Wafer

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Resolution
Mask
(Object)

E n t r an ce Pupil

Objective
Lens

Exit Pupil

W a f er
( I mage)

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Numerical Aperature

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Depth of Focus (DOF)
Depth of Focus (DOF) is defined as the range of focus that can be tolerated before
the image quality is degraded beyond usefulness

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Depth of Focus (DOF)

-100nm Focus

Best Focus
+100nm Focus

- Focus Best Focus + Focus

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Why DOF matters?

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Resolution and Depth of Focus

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Imagination vs. Reality

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The path for minimum feature size

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Increase NA – Immersion Lithography
NA = nsinθ

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Immersion Lithography System

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The Immersion Trick

n: air n=1 i-fluid=1.44

minimal line width ~ /NA

However DOF shrinks which requires more
complicated stacks to planarize topography.

DOF ~ /NA2
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The path for minimum feature size

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Light Sources – Reduce λ

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Spectrum and Light Wavelengths

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Arc Lamp Sources

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Mercury Arc Lamp

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Laser Sources

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Laser Sources

The wavelength of an excimer laser depends on the molecules used and

is usually in the ultraviolet range
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Wavelength Transitions

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The challenge of EUV
λ = 13.5nm
Eph = 95eV

throughput
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The path for minimum feature size

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k1
➢ Process factor and describes the difficulty of the production
➢ the smaller the k1, the more complex and more expensive the production
process
➢ For k1 > 0.5, the resolution on chip is comparable to the wavelength of
the imaging light. Mask structures and processes are comparably simple.
➢ For 0.25 < k1 < 0.5, the chip structures are already significantly smaller
than the light wavelength. Diffraction effects dominate and the proximity of
the actual structures has a massive impact on the imaging result. Mask
layouts must often be optimized. This leads to very complex mask
structures and production process
➢ For k1 < 0.25, critical dense structures can not be resolved in a single
exposure step. Need expensive process steps like multiple exposure
and/or process steps (double patterning)
➢ k1 reduction always leads to increasing manufacturing cost and
complexity

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Reduction in k1
k1 = (d*NA)/λ
If d=90nm, NA=1.35 and λ=193nm then k1=0.63
If d=30nm, NA=1.35 and λ=193nm then k1=0.21

k1 reduction has accelerated since minimum feature size

has become smaller than the exposure wavelength
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Reduction in k1
❖ Tools (and acronyms) of the trade to reduce k1:
• Off-Axis Illumination (OAI)
• Sub-Resolution/Printing Assist Features (SRAF/PrAF) Computational
• Optical Proximity Correction (OPC) Scaling

• Double Patterning Lithography (DPL)

• Source Mask Optimization (SMO)
NTD SID
ADLV PAU PAF
1000 ACLV CODE
CPL MEEF ORC PrAF
SFIL DPL
SBAR EWAF
FLEX IL DE2
SCALPEL LER
SIT SMO
# Acronyms

CDSEM AFM LWR

NIL DET
100 SRAF
DDL TARC EUV NGL SPADE
PAB CEL OPC MEF DfM
CAR DUV BARC
EPL RET
PAC PEB TSI
10 DOF attPSM
NA PAG OAI
NILS DRM
PW
1980 1985 1990 1995 2000 2005 2010
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k1

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Phase Shift Masks

➢ Create differential optical path length to invert electric field

of adjacent features
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Source – Off Axis Illumination (OAI)

➢ Offers significant boost in resolution but imposes restrictions

in orientation and pitch
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Mask – Sub Resolution Assist Features

➢ SRAFs are features intentionally placed on mask that are

too small to print but provide enough diffraction to make
isolated features print well
➢ Helps to concurrently print dense and isolated lines
➢ But, imposes forbidden pitches on layout
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Double patterning

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Gate Etch (28nm CMOS Tech.)
flow

1. PC litho 2. PC HMO 3. PC strip 4. CT litho

Oxide

Poly

SiN

Resist System

HKMG

5. CT HMO 6. CT strip 7. Gate final etch

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Gate Etch (28nm CMOS Tech.)

90, 65, 45nm

32nm

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Gate Etch (28nm CMOS Tech.)

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Self Aligned Double patterning (SADP)

❖ Only one litho step

❖ Directly printed resist profiles not suitable for process
❖ Use etch to transfer litho pattern into substrate before double
patterning process
❖ Etch and deposition steps create significant costs
❖ But still expensive than current EUV costs
❖ Will be used for fin patterning in 16nm technology
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SADP – An example

➢ High aspect ratio thin etched lines are evident

➢ Two different space sizes are evident
➢ Average pitch is half of that of the original lithography
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Extension of SADP

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Pitch splitting

=
+

28nm contact layer litho is done by pitch

splitting.
More and more layers in advanced
nodes will be done by this technique.
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Pitch splitting (Vias)

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Cost of Lithography

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Lithography from manufacturing point of view
➢ Overlay/alignment – This concerns the placement of patterns
relative to the previous layers
➢ CD control – How accurately is the critical dimension (linewidths)
controlled?
➢ Defectivity – This applies to pattern fidelity itself, as well to added
particles: there should be none
➢ Metrology – Masks have to be verified for corrections and the
resist patterns inspected after lithography; both tasks are becoming
formidable because of simultaneous linewidth reduction and chip
size increase
➢ Downstream compatibility – Describes the appropriateness of
the lithographic results for subsequent processing steps
➢ Cost – Because lithography is done many times (50 photomasks
in modern microprocessors) it is essential to keep throughput and
yield high
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Overlay Error

Layer 1 Layer 1 Layer 1

Layer 2 Layer 2 Layer 2

➢ Errors in the overlay of different lithographic levels can

directly cause a number of electrical problems

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Allignment Marks

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Overlay measurement test structures

Box-in-Box Frame-in-Frame Bar-in-Bar

Typical ‘box-in-box’ style overlay measurement targets, showing top-down

optical images along the top and typical cross-section diagrams along the
bottom. The outer box is typically 20 mm wide. (Courtesy of KLA-Tencor
Corp.)
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Overlay measurement

wXL
w XL wXR
w XR

Measuring overlay as a
x-overlay = 0.5(wXL - wXR) difference in width
measurements.
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Overlay measurement
Wafer
Pattern of
Exposure Slit
Fields

Scan
Direction

Single Exposure Field

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Typical photoresist profile


w

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 Effect of CD on circuit performance
1.0 1.0
High leakage Leakage
current, device Devices are current bin sort
0.8 fails too slow, poor 0.8 limit limit
bin sort
Frequency

Frequency
0.6 0.6

0.4 0.4

Range affects
0.2 timing, which 0.2
affects max clock
speed possible
0 0
75 80 85 90 95 100 105 75 80 85 90 95 100 105
Gate CD (nm) Gate CD (nm)

A distribution of polysilicon gate linewidths across a chip (a) can lead to

different performance failures. Tightening up the distribution of polysilicon
gate linewidths across a chip (b) allows for a smaller average CD and
faster device performance.
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CD, Overlay and design rules
Design rules are totally dependent on CD as well as overlay control
c
d
b

g
e f
a
h

Minimum f = Oc-aa + ∆CDc/2 + ∆CDaa/2

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CD Control
1000
140

900
Feature Width (nm)

120
800

Resist Linewidth
700 100

600

(nm)
80
500
E(CD – 10%) – E(CD + 10%)
EL =  100%
Threshold Fit Straight Line Fit Enominal
400 60
-1.5 -1.0 -0.5 0.0 0.5 1.0 20 25 30 35 40 45
2
Focus (m) Exposure Energy (mJ/cm )
250
Exposure Dose
(mJ/cm2)
Resist Feature Width, CD

200
14
16
150 18
20
22
100 24
26
30
50 34

0
-0.3 -0.2 -0.1 0.0 0.1 0.2
Focus (m)
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Focus

-100nm Focus

Best Focus
+100nm Focus

- Focus Best Focus + Focus

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Process Window
30

28
70
Exposure (mJ/cm2)

26
80
24 90

22
100

20 CD = 110nm 30

18 120 28
140

Exposure (mJ/cm2)
16 26
14 24
-0.3 -0.2 -0.1 0.0 0.1 0.2
Focus (m) 22

20

18

16
14
-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2
Focus (m)

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Impact of focus on an isolated line

+0.4 m Defocus In Focus -0.4 m Defocus

Simulated impact of focus on the shape of the end of an isolated line (250nm line, NA =
0.6,  = 0.5,  = 248, positive focus defined as shifting the focal plane up).

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Line end shortening (LES)

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 Line end shortening (LES)
600 600

400 400
Y Position (nm)

Y Position (nm)
200 200

0 0

-200 -200

-400 -400

-600 -600
-800 -600 -400 -200 0 200 400 600 800 -400 -200 0 200 400
X Position (nm) X Position (nm)

Outline of the printed photoresist pattern (solid) superimposed on an outline

of the mask (dashed) shows two examples of line-end shortening (k1 = 0.6).
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Poly endcap design rule (b)

c
d
b

g
e f
a
h

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Computational Scaling

Desired Scaling vs Litho Tool Resolution

1

0.7 65nm
Scale Factor

90nm
0.5 45nm desired

32nm tool enabled

0.35 15nm
22nm
0.25
computational scaling
0.175
2003 2005 2007 2009 2011 2013
Year of Manufacturing Ramp

IC manufacturing increasingly depending on computational lithography

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Why we need to improve resolution?
Without correction With correction

This is possible without changing optics

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Resolution enhancement techniques
➢ Optical Proximity Correction (OPC) - diffraction pattern
manipulation
➢ Modify mask shapes to correct for optical effects
➢ More exotic illumination conditions to improve resolution for
certain patterns
➢ Quadrupole, c-quad, dipole (OAI techniques)
➢ Has implications on design rules- “forbidden pitches”
➢ SMO – Source- Mask Optimization Off-Axis Illumination (OAI)

Phase Shifting Mask (PSM)

Lens
Quartz
Quartz

Phase
Shifted Conventional Annular Quadrupole
Space

Greater and greater dependence on simulation

→ “Computational Lithography”
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OPC (General idea and flow)

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Examples of model based OPC

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