EEE 343: Lab Manual (Version 1.

0)

Lab manual 8
Introduction to XILINX ISE and project design flow for synthesizable RTL

Objectives
1. To understand the basic functionality and usage of FPGA based platforms.

2. To get familiarization with project design flow using XILINX ISE tool.

3. Implementation and verification of basic combinational logic modules on XILINX Spartan 3E FPGA platform.

Recommended Readings
Spartan-3E FPGA Starter Kit Board User Guide by Xilinx, “UG230.pdf”

Chapter 7 (Section 7.8) of the book Digital Design by M. Morris Mano, 5th Edition

Introduction

This lab is concerned with implementation of small synthesizable RTL designs on a FPGA based platform. For that purpose, we

need to first understand the basic structure of a FPGA based system and then acquire hands on experience in implementing our

designs on said platform using synthesis and implementation tools like XILINX ISE.

A field‐programmable gate array (FPGA) is a VLSI circuit which can be programmed in field like microcontrollers. The difference

between the microcontrollers and FPGA platform is that MCU (microcontroller unit) can be visualized as an in built computer with

built in RAM , Rom and IO interfaces whereas, FPGAs are highly reconfigurable integrated circuits where the design is mapped on

logic blocks and digital design is physically constructed using gate arrays . A typical FPGA consists of an array of millions of logic

blocks, surrounded by programmable input and output blocks and connected together via programmable interconnections. There

is a wide variety of internal configurations within this group of devices. The performance of each type of device depends on the

circuit contained in its logic blocks and the efficiency of its programmed interconnections.

A typical FPGA logic block consists of lookup tables, multiplexers, gates, and flip‐flops. A lookup table is a truth table stored in an

SRAM and provides the combinational circuit functions for the logic block. These functions are realized from the lookup table, in the

same way that combinational circuit functions are implemented with ROM. For example, a 16*2 SRAM can store the truth table of

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a combinational circuit that has four inputs and two outputs. The combinational logic section, along with a number of programmable

multiplexers, is used to configure the input equations for the flip‐flop and the output of the logic block. In Xilinx based FPGA design

implementation, three basic steps will be carried out that are synthesis of digital design, implementation and assignment of the

programming file to the respected FPGA chip. For our lab purposes, we will be using Xilinx Spartan 3E development board and

XILINX ISE software for synthesis, implementation and mapping of our designs. Let us understand the complete implementation

flow of our design using XILINX ISE tool first. Fig 1 shows the primary interface window of the software.

Fig 1: Software primary interface

From synthesis of our project till mapping of our design on FPGA, we have to follow these simple steps.

Step 1: Project creation and device selection

After running design Suite, the first step is to create a new project and select an appropriate target device for implementation. Fig 2

represents the series of steps taken to create a project and associate a target device to our project which are shown as the

screenshots.

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Fig 2: steps for creating and assigning target device to project

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Step 2: Assigning design files to the project

Now we are ready to assign or associate our HDL files to our target device which is shown in hierarchy window after completing

step 1. Simply right click the target device and assign the required files to the device. Fig 3. Shows the screenshots of assigning a

new file to our project. If you had already have the source files then you can simply select Add source from pop up menu.

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Fig 3: Assigning design files to a project

Step 3: Users constraints file creation and association

The next step is to create a user’s constraints file, which will associate your ports to the physical pins of the FPGA system. There

are two ways to Interface your IO pins of the modules to the physical pin of the FPGA module. The first way is to use Planahead

tool, which can be selected from the processes panel right under the hierarchy panel. You just need to click on user’s constraints

option and select map IO pins. The second way is to create a user’s constraint file using any text editor and save the file with

extention “*.ucf”. The details of the pins and their labels can be obtained from UG230.pdf. The basic format for specifying the nets

and interconnections is shown below

Net “port name to be associated” LOC = “pin location” | IOstandard

NET "A” LOC= "L13" | IOSTANDARD= LVTTL | PULLUP ;

In this example, the net labeled A (the input pin in our reference example) is connected to a switch which is connected with FPGA

pin location L13 and have an IO standard of LVTTL and is a pullup switch. You can assign the constraints file by right clicking your

project file under device hierarchy and use add source. Fig 4 will appear after successful association.

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Figure 4: Assigning constraints file

Step 4: synthesis, Implementation and program file generation

After completing the three steps, now we are ready to synthesize, implement our design and generating a program file which later

on will be assigned to our target device. In the processes panel just double click on option synthesize for synthesis of our design. If

design contain no errors then design summary will be generated which can be seen in the main window. If the process is failed then

errors will be notified in console. After successful synthesis, the next step is to implement our design and generate the programming

file. The design summary will be updated after implementation process. The generated programming file can be seen in your project

folder and have extension *.bit. Fig.4 shows the snapshot for the process.

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Fig 5: Synthesis, implementation and program file generation

Step 5: Configuring target device

The final step is to configure our target device. Make sure the device is connected to the system using power cable and JTAG cable.

The configuration is done though impact tool which can be executed by clicking on configure target device option in processes

panel. Fig 6. Shows the screenshots of the processes carried out till final configuration. In impact window, we will first perform

boundary scan and then right click on screen to initialize chain to see the available devices for programming. Later on we will assign

our bit file to the target device and apply our set configuration to download the bit file to system.

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Fig 6: configuring Target device

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Lab Tasks

After going through the detailed steps, now we are ready to implement our tasks and execute them on FPGA platform in order to

check their functionality.

Task:

Implement a full adder circuit on Xilinx Spartan 3E FPGA and verify your results.

Lab Report
It is mandatory for each student to write a lab report individually after successful completion of each lab session in order to check

out what they had learned through that specified session. Follow the specified template in order to generate a lab report. Answer

the home assignment first before going through the details of your assigned task(s) in lab report.

Home Assignment
1. Define the terms, logic cells and Slices?

2. Briefly describe the latest Xilinx FPGA devices?

3. What does the term speed grade mean?

Task Report

For assigned task, provide the HDL code in Appendix A, Design summary in Appendix B and user’s constraints file in Appendix C

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