Thanks to visit codestin.com
Credit goes to www.scribd.com

Scribd
Upload
16 views4 pages

Lab Report 2

This lab report demonstrates the structural hardware description of an 8x1 multiplexer (MUX) using 2x1 MUX instantiation and includes behavioral simulation. It features Verilog code for both the 2x1 and 8x1 MUX, along with a test bench and an RTL schematic diagram. The report is submitted by Junaid Khalid to Dr. Muhammad Awais at COMSATS University Islamabad, Wah Campus.

Uploaded by

engrr.junaidkhalid
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
16 views4 pages

Lab Report 2

This lab report demonstrates the structural hardware description of an 8x1 multiplexer (MUX) using 2x1 MUX instantiation and includes behavioral simulation. It features Verilog code for both the 2x1 and 8x1 MUX, along with a test bench and an RTL schematic diagram. The report is submitted by Junaid Khalid to Dr. Muhammad Awais at COMSATS University Islamabad, Wah Campus.

Uploaded by

engrr.junaidkhalid
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 4

Digital System Design

Lab Report -2

Junaid Khalid | FA21-BEE-019

Section: BEE-8A

To: Dr. Muhammad Awais

Date: 2/25/2025

Department of Electrical & Computer Engineering


COMSATS University Islamabad, Wah Campus
Task: Demonstrate the structural hardware description of 8x1 Mux using 2x1 instantiating
and its behavioral simulation.

Structural Verilog Code for 8:1 MUX using 2:1 MUX

Verilog Code
 2x1 Mux:

 8x1 Mux:
Test bench:

Behavioral Simulation:
RTL Schematic Diagram:

You might also like