Experiment no.

1
Aim: To design and simulate Half adder with VHDL on XILINX

Theory:

Introduction to Xilinx:
Xilinx ISE (Integrated Synthesis Environment) is a software tool from Xilinx for synthesis
and analysis of HDL designs, which primarily targets development of embedded firmware for
Xilinx FPGA and CPLD integrated circuit (IC) product families. It was succeeded by Xilinx
Vivado. Use of the last released edition from October 2013 continues for in-system
programming of legacy hardware designs containing older FPGAs and CPLDs otherwise
orphaned by the replacement design tool, Vivado Design Suite.
ISE enables the developer to synthesize ("compile") their designs, perform timing analysis,
examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the
target device with the programmer. Other components shipped with the Xilinx ISE include
the Embedded Development Kit (EDK), a Software Development Kit (SDK) and ChipScope
Pro. The Xilinx ISE is primarily used for circuit synthesis and design, while ISIM or the
ModelSim logic simulator is used for system-level testing.

Half Adder:
A half adder is a basic digital electronic circuit used in computer engineering and digital
electronics to perform simple arithmetic addition on binary numbers.
A half adder circuit takes in two single binary digits (bits) and produces two output bits: the
sum (denoted by S) and the carry (denoted by C) bit.
The half adder can be represented with the following truth table:
A B C (Carry) Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

As you can see from the table, the sum bit is calculated with an exclusive OR (XOR) gate,
while the carry bit is calculated with an AND gate.

1
Logic Diagram:

VHDL Behavioural Design:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;

entity adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
c : out STD_LOGIC);
end adder;

architecture Behavioral of adder is

begin
sum <= a xor b;
c <= a and b;

end Behavioral;

2
RTL Schematic:

Testbench code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY adderTest IS
END adderTest;

ARCHITECTURE behavior OF adderTest IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT adder
PORT(
a : IN std_logic;
b : IN std_logic;
sum : OUT std_logic;
c : OUT std_logic
);
3
 END COMPONENT;

--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';

--Outputs
signal sum : std_logic;
signal c : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: adder PORT MAP (
a => a,
b => b,
sum => sum,
c => c
);

a <= '0', '1' after 100 ns ;

b<= '0', '1' after 50 ns , '0' after 100 ns ;

END;

Behavioural Simulation:

4
Conclusion:
In this experiment we learned that we can design and simulate hardware with
VHDL and we also designed a half adder with VHDL.

Assessment of the Experiment/Assignment:

Timely Submission Presentation Understanding Total Signature of teacher

(07) (06) (12) (25) with date

5
Experiment no. 2
Aim: To design and simulate different Multiplexers with VHDL on XILINX

Theory:
Multiplexer:
A multiplexer (also known as "mux") is a digital electronic device that selects one of several
input signals and forwards the selected input into a single output line.
Multiplexers are widely used in digital circuits and systems to increase the amount of data
that can be transmitted over a single channel or line. They are also used to select between
different sources of data, such as in a computer's memory addressing scheme.
In digital communications, the multiplexers are used to direct multiple signals into one
channel such that there is no overlapping of the signal or any data loss.

4×1 MUX:
A 4x1 multiplexer (also known as a 4-to-1 multiplexer/mux) is a digital circuit that selects
one of four input signals and passes it to a single output line based on the values of two select
or control lines, namely S0 and S1. The four input lines are labelled I0, I1, I2, and I3.
The operation of a 4x1 multiplexer is controlled by the values of S0 and S1. These two select
lines can take on one of four possible combinations of values, corresponding to the four input
lines.
The truth table for a 4x1 multiplexer with two select lines and four input lines is as follows:
S1 S0 Output
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Schematic for 4×1 MUX:

6
8x1 MUX:
An 8x1 multiplexer is a digital circuit that selects one of eight input signals and passes it to a
single output line based on the values of three select or control lines, namely S0, S1, and S2.
The eight input lines are labelled I0 to I7.
The operation of an 8x1 multiplexer is controlled by the values of S0, S1, and S2. These three
select lines can take on one of eight possible combinations of values, corresponding to the
eight input lines.
The truth table for an 8x1 multiplexer with three select lines and eight input lines is as
follows:
S2 S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

Schematic for 8×1 MUX:

16×1 MUX:
16x1 Multiplexer has 16 data inputs, 4 selection lines and one output. So, we require two 8x1
Multiplexers in first stage in order to get the 16 data inputs.

7
Schematic:

16×1 MUX Using four 4×1 MUX:

To implement a 16x1 MUX using 4x1 MUX, we can use a hierarchical approach, as follows:
First, we divide the 16 inputs into four groups of four. Then, we use four 4x1 MUXs to select
one output from each group of four. Finally, we use another 4x1 MUX to select one output
from the four outputs of the previous stage.
Here's the schematic of the 16x1 MUX using 4x1 MUX:

8
4x1 MUX:
VHDL Behavioural Design:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity mux1 is
Port (I : in STD_LOGIC_VECTOR (3 downto 0);
s: in STD_LOGIC_VECTOR (1 downto 0);
y: out STD_LOGIC);
end mux1;

architecture myMux of mux1 is

begin
process(s,I)
begin
case s is
when "00" => y<= I(0);
when "01" => y<= I(1);
when "10" => y<= I(2);
when others => y<= I(3);
end case;
end process;
end myMux;

Testbench Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

9
ENTITY mux1Test IS
END mux1Test;

ARCHITECTURE behavior OF mux1Test IS

COMPONENT mux1
PORT(
I : IN std_logic_vector(3 downto 0);
s : IN std_logic_vector(1 downto 0);
y : OUT std_logic
);
END COMPONENT;
signal I : std_logic_vector(3 downto 0) := (others => '0');
signal s : std_logic_vector(1 downto 0) := (others => '0');
signal y : std_logic;

BEGIN
uut: mux1 PORT MAP (
I => I,
s => s,
y => y
);

I<= "0101";
s<= "00", "01" after 100 ns, "10" after 200 ns, "11" after 300 ns;
END;

10
RTL schematic:

Behavioral Simulation:

8x1 MUX:

VHDL Behavioural Design:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux8x1 is
Port ( I : in STD_LOGIC_VECTOR (7 downto 0);
S : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC);
end mux8x1;

architecture Behavioral of mux8x1 is

11
begin
p1:process(S,I) is
begin
case S is
when "000" => y <= I(0);
when "001" => y <= I(1);
when "010" => y <= I(2);
when "011" => y <= I(3);
when "100" => y <= I(4);
when "101" => y <= I(5);
when "110" => y <= I(6);
when others => y <= I(7);
end case;
end process;
end Behavioral;

Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY mux8Test IS
END mux8Test;

ARCHITECTURE behavior OF mux8Test IS

COMPONENT mux8x1
PORT(
I : IN std_logic_vector(7 downto 0);
S : IN std_logic_vector(2 downto 0);
y : OUT std_logic
);
END COMPONENT;

12
 signal I : std_logic_vector(7 downto 0) := (others => '0');
signal S : std_logic_vector(2 downto 0) := (others => '0');
signal y : std_logic;
BEGIN
uut: mux8x1 PORT MAP (
I => I,
S => S,
y => y
);
I <= "00110111";
S <= "000", "001" after 100 ns,"010" after 200 ns,"011" after 300 ns,"100" after 400
ns,
"101" after 500 ns,"110" after 600 ns,"111" after 700 ns;

END;

RTL Schematic

Behavioral Simulation:

13
MUX 16x1 Using 4x1:

VHDL Behavioural Design:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity mux16x1 is
Port ( D : in STD_LOGIC_VECTOR (15 downto 0);
Y : out STD_LOGIC;
S : in STD_LOGIC_VECTOR (3 downto 0));
end mux16x1;

architecture Behavioral of mux16x1 is

component mux1 is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC);
end component;
signal t1,t2,t3,t4: std_logic;
begin
m1: mux1 port map (I=>D(3 downto 0),s=>S(1 downto 0), y=>t1 );
m2: mux1 port map (I=>D(7 downto 4),s=>S(1 downto 0), y=>t2 );
m3: mux1 port map (I=>D(11 downto 8),s=>S(1 downto 0), y=>t3 );
m4: mux1 port map (I=>D(15 downto 12),s=>S(1 downto 0), y=>t4 );
m5: mux1 port map (I(0)=>t1,I(1)=>t2,I(2)=>t3,I(3)=>t4,s=>S(3 downto 2), y=>Y );

end Behavioral;

14
Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mux16x1Test IS
END mux16x1Test;
ARCHITECTURE behavior OF mux16x1Test IS
COMPONENT mux16x1
PORT(
D : IN std_logic_vector(15 downto 0);
Y : OUT std_logic;
S : IN std_logic_vector(3 downto 0)
);
END COMPONENT;
signal D : std_logic_vector(15 downto 0) := (others => '0');
signal S : std_logic_vector(3 downto 0) := (others => '0');
signal Y : std_logic;
BEGIN
uut: mux16x1 PORT MAP (
D => D,
Y => Y,
S => S
);
D<= "0011011011101110";
S<= "0011",
"1011" after 100 ns,
"0101" after 200 ns,
"1101" after 300 ns,
"1111" after 400 ns,
"1100" after 500 ns;
END;
15
RTL Schematic:

Behavioral Simulation:

16
Conclusion:
In this Experiment we learned about different types of multiplexers. We can
design and simulate them on Xilinx with VHDL. We also saw how to design
16x1 mux using the 4x1 as a component.

Assessment of the Experiment/Assignment:

Timely Submission Presentation Understanding Total Signature of teacher

(07) (06) (12) (25) with date

17
Experiment 3
Aim: To design and simulate Demultiplexer

Theory:
Demultiplexer:
A demultiplexer, also known as a demux or data distributor, is an electronic circuit that takes
a single input signal and distributes it to multiple output signals.

4X1 Demux:
A 1x4 demultiplexer (or demux) is a digital circuit that takes a single input signal and selects
one of four possible output lines based on a set of control signals. The demux has one input
line, and four output lines.

The truth table for a 1x4 demux is as follows:

S1 S0 Y0 Y1 Y2 Y3
0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I
The input signal is routed to one of the four output lines based on the value of the control
signal. For example, if the select signal is 0, then the input signal is passed through to output
0 and all other outputs are set to 0. If the select signal is 2, then the input signal is passed
through to output 2 and all other outputs are set to 0.

8X1 Demux:
Demultiplexer with 8 output lines is called an 8-to-1 demultiplexer (or 8x1 demux for short).

18
The truth table for an 8x1 demux is as follows:
S2 S1 S0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 I 0 0 0 0 0 0 0
0 0 1 0 I 0 0 0 0 0 0
0 1 0 0 0 I 0 0 0 0 0
0 1 1 0 0 0 I 0 0 0 0
1 0 0 0 0 0 0 I 0 0 0
1 0 1 0 0 0 0 0 I 0 0
1 1 0 0 0 0 0 0 0 I 0
1 1 1 0 0 0 0 0 0 0 I

Demux 1x4:

VHDL behavioural design:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity deux1x4 is
Port ( s : in STD_LOGIC_VECTOR (1 downto 0);
19
 I : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0));
end deux1x4;

architecture Behavioral of deux1x4 is

begin
process(I, s)
begin
if s= "00" then
y(0)<= I;
y(1)<= 'Z';
y(2)<= 'Z';
y(3)<= 'Z';
elsif s = "01" then
y(1)<= I;
y(0)<= 'Z';
y(2)<= 'Z';
y(3)<= 'Z';
elsif s = "10" then
y(2)<= I;
y(0)<= 'Z';
y(1)<= 'Z';
y(3)<= 'Z';
elsif s = "11" then
y(3)<= I;
y(0)<= 'Z';
y(1)<= 'Z';
y(2)<= 'Z';
else
y <= "ZZZZ";
end if;

20
end process;
end Behavioral;

Testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
ENTITY demuxTest IS
END demuxTest;

ARCHITECTURE behavior OF demuxTest IS

COMPONENT deux1x4
PORT(
s : IN std_logic_vector(1 downto 0);
I : IN std_logic;
y : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
signal s : std_logic_vector(1 downto 0) := (others => '0');
signal I : std_logic := '0';
signal y : std_logic_vector(3 downto 0);

BEGIN
uut: deux1x4 PORT MAP (
s => s,
I => I,
y => y
);

I<='1';
s<= "00", "01" after 100 ns,"10" after 200 ns,"11" after 300 ns;

21
END;

RTL Schematic:

Behavioural Simulation:

Demux 1x8:

VHDL behavioural design:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity demux is
Port ( I : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end demux;

22
architecture Behavioral of demux is
begin
process(I,s)
begin
if s = "000" then
y(0)<=I;
y(1)<='Z';
y(2)<='Z';
y(3)<='Z';
y(4)<='Z';
y(5)<='Z';
y(6)<='Z';
y(7)<='Z';

elsif s = "001" then

y(0)<='Z';
y(1)<=I;
y(2)<='Z';
y(3)<='Z';
y(4)<='Z';
y(5)<='Z';
y(6)<='Z';
y(7)<='Z';
elsif s = "010" then
y(0)<='Z';
y(1)<='Z';
y(2)<= I;
y(3)<='Z';
y(4)<='Z';
y(5)<='Z';
y(6)<='Z';
y(7)<='Z';

23
 elsif s = "011" then
y(0)<='Z';
y(1)<='Z';
y(2)<='Z';
y(3)<=I;
y(4)<='Z';
y(5)<='Z';
y(6)<='Z';
y(7)<='Z';
elsif s = "100" then
y(0)<='Z';
y(1)<='Z';
y(2)<='Z';
y(3)<='Z';
y(4)<=I;
y(5)<='Z';
y(6)<='Z';
y(7)<='Z';
elsif s = "101" then
y(0)<='Z';
y(1)<='Z';
y(2)<='Z';
y(3)<='Z';
y(4)<='Z';
y(5)<=I;
y(6)<='Z';
y(7)<='Z';
elsif s = "110" then
y(0)<='Z';
y(1)<='Z';
y(2)<='Z';
y(3)<='Z';

24
 y(4)<='Z';
y(5)<='Z';
y(6)<=I;
y(7)<='Z';
elsif s = "111" then
y(0)<='Z';
y(1)<='Z';
y(2)<='Z';
y(3)<='Z';
y(4)<='Z';
y(5)<='Z';
y(6)<='Z';
y(7)<=I;
else
y<="ZZZZZZZZ";
end if;
end process;
end Behavioral;

Testbench:
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

ENTITY demuxTest IS
END demuxTest;

ARCHITECTURE behavior OF demuxTest IS

COMPONENT demux

25
 PORT(
I : IN std_logic;
s : IN std_logic_vector(2 downto 0);
y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
signal I : std_logic := '0';
signal s : std_logic_vector(2 downto 0) := (others => '0');
signal y : std_logic_vector(7 downto 0);

BEGIN
uut: demux PORT MAP (
I => I,
s => s,
y => y
);

I<='1';
s <= "000",
"001" after 100 ns,
"010" after 200 ns,
"011" after 300 ns,
"100" after 400 ns,
"101" after 500 ns,
"110" after 600 ns,
"111" after 700 ns;

END;

26
RTL schematic:

Behavioural Simulation:

27
Conclusion:
In this experiment we learned about the demultiplexer. We designed it using ISE
Xilinx with VHDL.

Assessment of the Experiment/Assignment:

Timely Submission Presentation Understanding Total Signature of teacher

(07) (06) (12) (25) with date

28
Experiments 4
Aim: To design and simulate 4x2 and 8x3 encoders with VHDL

Theory:
Encoder:
An encoder in digital electronics is a one-hot to binary converter. That is, if there are 2n input
lines, and at most only one of them will ever be high, the binary code of this 'hot' line is
produced on the n-bit output lines. A binary encoder is the dual of a binary decoder.

4x2 Encoder:
A 4x2 encoder is a combinational circuit that takes in four input signals and generates a two-
bit binary output based on the input combinations.
The output bits of the encoder indicate which input line is active (high) by encoding the
binary value of the active input line. For example, if input line D0 is active (high), the output
bits will be 00. If input line D1 is active, the output bits will be 01. If input line D2 is active,
the output bits will be 10. If input line D3 is active, the output bits will be 11.

Here's a truth table that shows the input-output relationship of a 4x2 encoder:
D3 D2 D1 D0 Y1 Y0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

As you can see from the truth table, when more than one input line is active, the encoder will
prioritize the input line with the highest priority. In this case, input line D has the highest
priority, followed by input line C, input line B, and input line A, respectively.

29
8x3 Encoder:
An 8x3 encoder is a digital circuit that takes in 8 input signals and produces a 3-bit binary
code as output.

Encoder 4x2:

VHDL Behavioural Design:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Mux4X2 is
Port ( D : in STD_LOGIC_VECTOR (3 downto 0);
Y : out STD_LOGIC_VECTOR (1 downto 0));
end Mux4X2;

architecture Behavioral of Mux4X2 is

begin
Process(D)
begin
case D is

30
 when "0001" => Y<= "00";
when "0010" => Y<= "01";
when "0100" => Y<= "10";
when "1000" => Y<= "11";
when others => Y<= "ZZ";
end case;
end Process;

end Behavioral;

Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY MuxTest IS
END MuxTest;

ARCHITECTURE behavior OF MuxTest IS

COMPONENT Mux4X2
PORT(
D : IN std_logic_vector(3 downto 0);
Y : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
signal D : std_logic_vector(3 downto 0) := (others => '0');

signal Y : std_logic_vector(1 downto 0);

BEGIN
uut: Mux4X2 PORT MAP (

31
 D => D,
Y => Y
);

D<= "0000", "0001" after 100 ns,

"0010" after 200 ns,
"0100" after 300 ns,
"1000" after 400 ns;

END;

RTL Schematic:

Behavioural Simulation:

32
Encoder 8x3:

VHDL Behavioural Design:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity Encode8x3 is
Port ( D : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC_VECTOR (2 downto 0));
end Encode8x3;

architecture Behavioral of Encode8x3 is

begin

process(D) is
begin
case D is
when "00000001" => Y<= "000";
when "00000010" => Y<= "001";
when "00000100" => Y<= "010";
when "00001000" => Y<= "011";
when "00010000" => Y<= "100";
when "00100000" => Y<= "101";
when "01000000" => Y<= "110";
when "10000000" => Y<= "111";
when others => Y <= "ZZZ";
end case;
33
end process;
Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY EncoderTest IS
END EncoderTest;

ARCHITECTURE behavior OF EncoderTest IS

COMPONENT Encode8x3
PORT(
D : IN std_logic_vector(7 downto 0);
Y : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
signal D : std_logic_vector(7 downto 0) := (others => '0');
signal Y : std_logic_vector(2 downto 0);

BEGIN
uut: Encode8x3 PORT MAP (
D => D,
Y => Y
);

D<= "00000000","00000001" after 100 ns,

"00000010" after 200 ns,
"00000100" after 300 ns,
"00001000" after 400 ns,
"00010000" after 500 ns,
"00100000" after 600 ns,
"01000000" after 700 ns,

34
 "10000000" after 800 ns;

END;

RTL schematic:

Behavioural simulation:

35
Conclusion:
In this experiment we learned about the Encoders. We designed it using ISE
Xilinx with VHDL. We also verified their working with the testbench.

Assessment of the Experiment/Assignment:

Timely Submission Presentation Understanding Total Signature of teacher

(07) (06) (12) (25) with date

36
Experiment 5
Aim: To design and simulate 3x8 and 2x4 decoders.

Theory:
Binary decoder:
In digital electronics, a binary decoder is a combinational logic circuit that converts binary
information from the n coded inputs to a maximum of 2ⁿ unique outputs.

2x4 decoder:
A 2x4 decoder is a digital circuit that takes two inputs and generates four outputs, where only
one output is active (high) at a time based on the input combination. The two inputs are called
the selection lines, and the four outputs are called the data lines.

The truth table of a 2x4 decoder is as follows:

A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

3x8 decoder:
A 3x8 decoder is a digital circuit that converts a 3-bit input into one of eight possible outputs.
The output of the decoder depends on the combination of input bits. Each input combination
of 3 bits represents a unique output line out of the eight possible outputs.

37
Its truth table is as follows:
S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

Decoder 2x4:

VHDL Behavioural Design:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity Decoder2x4 is
Port ( I : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end Decoder2x4;
38
architecture Behavioral of Decoder2x4 is

begin
process(I)
begin
case I is
when "00"=> Y<="0001";
when "01"=> Y<="0010";
when "10"=> Y<="0100";
when "11"=> Y<="1000";
when others => Y<="0000";
end case;
end process;

end Behavioral;

Testbench:
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

ENTITY decoderTEst IS
END decoderTEst;

ARCHITECTURE behavior OF decoderTEst IS

COMPONENT Decoder2x4
PORT(

39
 I : IN std_logic_vector(1 downto 0);
Y : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
signal I : std_logic_vector(1 downto 0) := (others => '0');

--Outputs
signal Y : std_logic_vector(3 downto 0);

BEGIN
uut: Decoder2x4 PORT MAP (
I => I,
Y => Y
);
I <= "00","01" after 100 ns, "10" after 200 ns, "11" after 300 ns ;
END;

RTL schematic:

40
Behavioural simulation:

Decoder 3x8:
VHDL Behavioural Design:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY decodTest IS
END decodTest;

ARCHITECTURE behavior OF decodTest IS

COMPONENT Decod3x8
PORT(
I : IN std_logic_vector(2 downto 0);
Y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
signal I : std_logic_vector(2 downto 0) := (others => '0');
signal Y : std_logic_vector(7 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: Decod3x8 PORT MAP (
I => I,

41
 Y => Y
);
I<= "000",
"001" after 100 ns,
"011" after 200 ns,
"101" after 300 ns,
"110" after 400 ns,
"111" after 500 ns;

END;

Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY decodTest IS
END decodTest;

ARCHITECTURE behavior OF decodTest IS

COMPONENT Decod3x8
PORT(
I : IN std_logic_vector(2 downto 0);
Y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
signal I : std_logic_vector(2 downto 0) := (others => '0');
signal Y : std_logic_vector(7 downto 0);

BEGIN
42
 uut: Decod3x8 PORT MAP (
I => I,
Y => Y
);
I<= "000",
"001" after 100 ns,
"011" after 200 ns,
"101" after 300 ns,
"110" after 400 ns,
"111" after 500 ns;
END;

RTL schematic:

Behavioural simulation:

43
Conclusion:
In this Experiment we learned about different types of decoders (2x4 and 8x3)
We can design and simulate them on Xilinx with VHDL.

Assessment of the Experiment/Assignment:

Timely Submission Presentation Understanding Total Signature of teacher

(07) (06) (12) (25) with date

44
Experiment 6
Aim: To design and simulate full adder using half adders.

Theory:
A full adder is a digital circuit that adds two binary digits and a carry bit (a digit that
represents a carry from a previous addition operation) to produce a sum and a new carry bit.
A full adder can be implemented using logic gates such as AND, OR, and XOR gates.
A full adder can be designed using two half adders as follows:

Truth table:
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

VHDL Behavioural Design:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

45
entity fullAdder is
Port ( x1,x2,cin : in STD_LOGIC;
sum, cout : out STD_LOGIC);
end fullAdder;

architecture Behavioral of fullAdder is

component halfAdder is
Port ( a,b : in STD_LOGIC;
c,s : out STD_LOGIC);
end component;
signal t1,t2,t3:std_logic;
begin
m1: halfAdder port map(a=>x1,b=>x2,s=>t1,c=>t2);
m2: halfAdder port map(a=>t1,b=>cin,s=>sum,c=>t3);
cout <= t2 or t3;

end Behavioral;

Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY faTest IS
END faTest;

ARCHITECTURE behavior OF faTest IS

46
 COMPONENT fullAdder
PORT(
x1 : IN std_logic;
x2 : IN std_logic;
cin : IN std_logic;
sum : OUT std_logic;
cout : OUT std_logic
);
END COMPONENT;

signal x1 : std_logic := '0';

signal x2 : std_logic := '0';
signal cin : std_logic := '0';
signal sum : std_logic;
signal cout : std_logic;

BEGIN

uut: fullAdder PORT MAP (

x1 => x1,
x2 => x2,
cin => cin,
sum => sum,
cout => cout
);

x1<= '0', '1' after 500 ns;

x2<= '0', '1' after 200 ns,
'0' after 300 ns,
'1' after 600 ns;
47
 cin <= '0', '1' after 100 ns,
'0' after 200 ns,
'1' after 300 ns,
'0' after 500 ns,
'1' after 700 ns;

END;

RTL schematic:

Behavioural simulation:

48
Conclusion:
In this experiment we learned that we can design and simulate hardware with
VHDL and we also designed a full adder with VHDL using two half adders as
components.

Assessment of the Experiment/Assignment:

Timely Submission Presentation Understanding Total Signature of teacher

(07) (06) (12) (25) with date

49
Experiment 7
Aim: To design and simulate 4-bit parallel adder with VHDL

Theory:
A 4-bit parallel adder can be implemented using four full adders. Each full adder takes in
three inputs: A, B, and Carry-In (Cin), and produces two outputs: Sum (S) and Carry-Out
(Cout).
The basic idea is to connect the Cin of the first full adder to 0 (since there is no carry-in for
the first bit) and connect the Cout of each full adder to the Cin of the next full adder (since
the carry-out of one bit becomes the carry-in of the next bit). The Sum output of each full
adder becomes one bit of the final output.
Here is a schematic diagram of the n-bit parallel adder using N full adders:

VHDL Behavioural Design:

Parallel adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity parallelAdder is

50
 Port ( I1 : in STD_LOGIC_VECTOR (3 downto 0);
I2 : in STD_LOGIC_VECTOR (3 downto 0);
paSum : out STD_LOGIC_VECTOR (4 downto 0));
end parallelAdder;

architecture Behavioral of parallelAdder is

component fullAdder is
Port ( x1,x2,cin : in STD_LOGIC;
sum, cout : out STD_LOGIC);
end component;
signal t1,t2,t3,t4,t5,t6,t7,t8: std_logic;
begin
fa1: fullAdder port map (x1=>I1(0),x2=>I2(0),cin=>'0',sum=>t1,cout =>t2);
fa2: fullAdder port map (x1=>I1(0),x2=>I2(0),cin=>t2,sum=>t3,cout =>t4);
fa3: fullAdder port map (x1=>I1(0),x2=>I2(0),cin=>t4,sum=>t5,cout =>t6);
fa4: fullAdder port map (x1=>I1(0),x2=>I2(0),cin=>t6,sum=>t7,cout =>t8);
paSum(0)<= t1;
paSum(1)<= t3;
paSum(2)<= t5;
paSum(3)<= t7;
paSum(4)<= t8;

end Behavioral;

Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

51
ENTITY faTest IS
END faTest;

ARCHITECTURE behavior OF faTest IS

COMPONENT fullAdder
PORT(
x1 : IN std_logic;
x2 : IN std_logic;
cin : IN std_logic;
sum : OUT std_logic;
cout : OUT std_logic
);
END COMPONENT;

signal x1 : std_logic := '0';

signal x2 : std_logic := '0';
signal cin : std_logic := '0';

signal sum : std_logic;

signal cout : std_logic;

BEGIN
uut: fullAdder PORT MAP (
x1 => x1,
x2 => x2,
cin => cin,
sum => sum,
cout => cout
);

52
 x1<= '0', '1' after 500 ns;
x2<= '0', '1' after 200 ns,
'0' after 300 ns,
'1' after 600 ns;
cin <= '0', '1' after 100 ns,
'0' after 200 ns,
'1' after 300 ns,
'0' after 500 ns,
'1' after 700 ns;

END;

RTL schematic:

Behavioural simulation:

53
Conclusion:
In this Experiment we deigned and simulated a 4-bit parallel adder with VHDL.
In the program we used 4 full adders as components.

Assessment of the Experiment/Assignment:

Timely Submission Presentation Understanding Total Signature of teacher

(07) (06) (12) (25) with date

54
Experiment 8
Aim: VHDL Code for Up Counter, Down Counter, Up-down Counter, Mod-N Counter.

Theory:
Up Counter
A 4-bit up counter is a digital circuit that counts upwards from 0 to 15 (in binary) and then
resets back to 0. It is also known as a modulo-16 counter, as it counts 16 states before
resetting.

When the circuit is first powered on, all the flip-flops are reset to 0. On the first clock pulse,
the input to the first flip-flop (D0) becomes 1, causing its output (Q0) to become 1. On the
second clock pulse, the input to the second flip-flop (D1) becomes the value of Q0, which is
1, causing its output (Q1) to become 1. This process repeats for each flip-flop, so that on the
fourth clock pulse, the output of the last flip-flop (Q3) becomes 1, indicating that the
counter has reached its maximum value of 15 (in binary).

55
56
Down Counter
A 4-bit down counter is a digital circuit that counts downwards from 15 (in binary) to 0 and
then resets back to 15. It is also known as a modulo-16 counter, as it counts 16 states before
resetting.

When the circuit is first powered on, all the flip-flops are set to 1 (the complement of 0). On
the first clock pulse, the input to the first flip-flop (D0) becomes 0, causing its output (Q0)
to become 0. On the second clock pulse, the input to the second flip-flop (D1) becomes the
complement of Q0, which is 1, causing its output (Q1) to become 0. This process repeats for
each flip-flop, so that on the fourth clock pulse, the output of the last flip-flop (Q3) becomes
0, indicating that the counter has reached its minimum value of 0 (in binary).

57
Up-Down Counter
A 4-bit up-down counter is a digital circuit that can count up or down depending on the
input provided. It has four output bits, which represent the count value in binary form.

To count up, the control flip-flops are connected in a cascade fashion, such that the output of
one flip-flop feeds into the clock input of the next flip-flop. When B is high, the control flip-
flops generate a sequence of pulses that increment the counter. To count down, the control
flip-flops are connected in a similar cascade fashion, but with an additional OR gate to
generate the complement of the clock signal. When B is low, the control flip-flops generate
a sequence of pulses that decrement the counter.

58
Mod-N Counter
A mod n counter is a type of counter that counts modulo n, where n is a positive integer.
This means that the counter will reset to 0 after counting up to n-1, and will continue
counting from 0 again.

The design of a mod n counter can be implemented using combinational logic and
sequential logic. The combinational logic is used to generate the next state of the counter
based on the current state and the count direction, while the sequential logic is used to store
the current state of the count  er.

59
VHDL behavioral designs:
DOWN COUNTER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity downcounter is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out std_logic_vector(3 downto 0)
);
end downcounter;

architecture Behavioral of downcounter is

signal Qs : std_logic_vector(3 downto 0) := "0000";

begin
process(CLK , RST)
begin
if (RST = '1') then
Qs <= "1111";
else if (CLK = '0' and CLK'event) then
Qs <= Qs - '1';

end if;
end if;
end process;
60
 Q <= Qs;

end Behavioral;
DOWN COUNTER TESTBENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY downcounter_tb IS
END downcounter_tb;

ARCHITECTURE behavior OF downcounter_tb IS

COMPONENT downcounter
PORT(
CLK : IN std_logic;
RST : IN std_logic;
Q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

signal CLK : std_logic := '0';

signal RST : std_logic := '0';

signal Q : std_logic_vector(3 downto 0);

BEGIN

uut: downcounter PORT MAP (

CLK => CLK,
RST => RST,
Q => Q
61
 );

CLK <= not CLK after 100ns;

RST <= '0' , '1' after 500ns , '0' after 600ns;

END;

62
MODN COUNTER
---Mod 50 COunter
---Therefore min count will be 64 which requires 6 bits
---2^n >= N
---2^n >= 50 ==>> n = 5
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity modn is
Port(
CLK , RST : IN STD_LOGIC ;
S : OUT STD_LOGIC_VECTOR (5 downto 0));
end modn;

architecture Behavioral of modn is

signal Qs : std_logic_vector(5 downto 0) := "000000";

begin
process(CLK , RST)
begin
if (RST = '1') then
Qs <= "000000";
else if (rising_edge(CLK)) then
if(Qs = "110010") then
Qs <= "000000";
else
Qs <= Qs + '1';
end if;
end if;
63
 end if;
end process;
S <= Qs;
end Behavioral;

MODN COUNTER TESTBENCH

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY modn_tb IS
END modn_tb;

ARCHITECTURE behavior OF modn_tb IS

COMPONENT modn
PORT(
CLK : IN std_logic;
RST : IN std_logic;
S : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;

signal CLK : std_logic := '0';

signal RST : std_logic := '0';

signal S : std_logic_vector(5 downto 0);

BEGIN

uut: modn PORT MAP (

64
 CLK => CLK,
RST => RST,
S => S
);

CLK <= not CLK after 50ns;

RST <= '0' , '1' after 1000ns , '0' after 1100ns,'1' after 8000ns , '0' after 8100ns;

END;

65
UPCOUNTER
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY modn_tb IS
END modn_tb;

ARCHITECTURE behavior OF modn_tb IS

COMPONENT modn
PORT(
CLK : IN std_logic;
RST : IN std_logic;
S : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;

signal CLK : std_logic := '0';

signal RST : std_logic := '0';

signal S : std_logic_vector(5 downto 0);

BEGIN

uut: modn PORT MAP (

CLK => CLK,
RST => RST,
S => S
);

66
 CLK <= not CLK after 50ns;
RST <= '0' , '1' after 1000ns , '0' after 1100ns,'1' after 8000ns , '0' after 8100ns;

END;

UPCOUNTER TESTBENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY upcounter_tb IS
END upcounter_tb;

ARCHITECTURE behavior OF upcounter_tb IS

COMPONENT upcounter
PORT(
CLK : IN std_logic;
RST : IN std_logic;
Q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

signal CLK : std_logic := '0';

signal RST : std_logic := '0';

signal Q : std_logic_vector(3 downto 0);

BEGIN

uut: upcounter PORT MAP (

CLK => CLK,
67
 RST => RST,
Q => Q
);

CLK <= not CLK after 100ns;

RST <= '0' , '1' after 500ns , '0' after 600ns;

END;

68
UPDOWN COUNTER
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY upcounter_tb IS
END upcounter_tb;

ARCHITECTURE behavior OF upcounter_tb IS

COMPONENT upcounter
PORT(
CLK : IN std_logic;
RST : IN std_logic;
Q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

signal CLK : std_logic := '0';

signal RST : std_logic := '0';

signal Q : std_logic_vector(3 downto 0);

BEGIN

uut: upcounter PORT MAP (

CLK => CLK,
RST => RST,
Q => Q
);

CLK <= not CLK after 100ns;

69
 RST <= '0' , '1' after 500ns , '0' after 600ns;

END;

UPDOWN COUNTER TESTBENCH

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY updowncounter_tb IS
END updowncounter_tb;

ARCHITECTURE behavior OF updowncounter_tb IS

COMPONENT updowncounter
PORT(
CLK : IN std_logic;
RST : IN std_logic;
DIR : IN std_logic;
Q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

signal CLK : std_logic := '0';

signal RST : std_logic := '0';
signal DIR : std_logic := '1';
signal Q : std_logic_vector(3 downto 0);

BEGIN

uut: updowncounter PORT MAP (

CLK => CLK,
70
 RST => RST,
DIR => DIR,
Q => Q
);
CLK <= not CLK after 50ns;
RST <= '0' , '1' after 400ns , '0' after 600ns;
DIR <= not DIR after 1500ns;
END;

71
72
73
74
75
76
77
78
79
80
81
Conclusion:
In this experiment we designed different types of counters with VHDL on ISE
Xilinx, learned their differences and simulated them.

Assessment of the Experiment/Assignment:

Timely Submission Presentation Understanding Total Signature of teacher

(07) (06) (12) (25) with date

82