PSIT-Pranveer Singh Institute of Technology

Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Computer Organization Lab

(BCS-352)

Session 2024-25

Submitted By
Name:
Roll No:
Branch:

BCS -352
 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Table of Contents

 Evaluation Scheme and guidelines

 Syllabus

 Course Outcomes/CO-PO / PSO Mapping

 List of Experiments

 Index

 Experiments

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Evaluation Guideline and Scheme

Evaluation Scheme Marks Sub-Total

Performance 20
Viva 10
50
Internal Lab Record 10
Attendance 10
External University Exam 50 50
Grand Total 100

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Syllabus
The following list outlines the syllabus for Computer Organisation Lab (KCS-352) as prescribed
byDr. A.P.J. Abdul Kalam Technical University, Uttar Pradesh, Lucknow.
The syllabus can also be viewed on the university website:
https://fms.aktu.ac.in/Resources/aktu/pdf/syllabus/Syllabus2324/B.Tech_2nd_Yr_CSE_v2.pdf

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

LAB PLAN
SUBJECT NAME: COMPUTER ORGANIZATION LAB
SUBJECT CODE: BCS-352

Lab Schedule: As per the time table

i) Course Objective:
 To prepare students to perform the analysis and design of various digital electronics
circuits.

ii) Course Outcomes

*Level of Bloom’s Taxonomy Level to be met*Level of Bloom’s Taxonomy Level to be met

L1: Knowledge and L2: Comprehension 1
L3: Application and L4: Analysis 2
L5: synthesis and L6: Evaluation 3
Students will be able to identify the logic family and pin configuration of various
CO1
ICs used in the Lab.
CO2 Students will be able to understand scalability of different processors.
Students will be able to analyze the problem and design a circuit (combinational,
CO3
sequential, ALU,I/O System) to solve that problem with various ICs.

Mapping of Course Outcomes with Program Outcomes and Program Specific Outcomes:

Program Outcomes PSO

COs 1 2 3 4 5 6 7 8 9 10 11 12 1 2

CO-1 2 2 2 2

CO-2 2 2 2 2

CO-3 2 2 2 2

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

List of Experiments

Experiments Prescribed by AKTU

Lab No Lab Experiment Outcomes CO to be

met
1 Implementing HALF ADDER & FULL To implement HALF ADDER
ADDER using basic logic gates. & FULL ADDER circuits CO3
using basic logic gates.
2 Implementing Binary-to-Gray & Gray-to- To implement circuits for
Binary code conversions. Binary-to-Gray & Gray-to- CO3
Binary code conversions.
3 Implementing 3-8 line DECODER. To implement and verify the
CO3
truth table of 3-8 line decoder.
4 Implementing 4x1 and 8x1 To implement and verify the
MULTIPLEXERS. truth table of 4x1 and 8x1 CO3
MUX.
5 Verify the excitation tables of various Toverify the truth table and
FLIP-FLOPS. excitation tables of different CO1
flip flops
6 Design of an 8-bit Input/ Output system with To design an 8-bit Input/
four 8-bit Internal Registers. Output system with four 8-bit CO3
Internal Registers.
7 Design of an 8-bit ARITHMETIC LOGIC To design an 8-bit
CO2
UNIT. ARITHMETIC LOGIC UNIT.

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Experiments Beyond syllabus

Ex. Lab Experiment Outcomes CO to b
No. met
1 Verification of truth tables of various logi To identify various logic gate ICs and CO1
gates. verify their truth tables.
2 Implementation of 4-bit parallel adder usin To Implement 4-bit parallel adder using CO1
7483 IC 7483 IC
3 Implementation of One& Two Bit To implement One & Two Bit CO3
Comparator using logic gates. Comparator using logic gates.
4 Design, and verify the 4-bit asynchronous To design and verify the 4-bit CO3
counter. asynchronous counter.
5 Design, and verify the 4-bit synchronous To Design, and verify the 4-bit CO3
counter. synchronous counter.

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

INDEX

Lab No Lab Experiment Date of Date of Remarks/

Experiment Submission Teacher Signatur

1 Verification of truth tables of various

logic gates

2 Implementing Binary-to-Gray & Gray-

to-Binary code conversions

3 Implementing HALF ADDER & FULL

ADDER using basic logic gates

4 Implementation of 4-bit parallel adder

using 7483 IC

5 Implementation of One & Two Bit

Comparator using logic gates.

6 Implementing 3-8 line DECODER.

7 Implementing 4x1 and 8x1

MULTIPLEXERS.

8 Verify the excitation tables of various

FLIP-FLOPS.

9 Design, and verify the 4-bit

asynchronous counter.

10 Design, and verify the 4-bit synchronous

counter.

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Experiment No. 1
AIM: To identify various logic gate ICs, viz. AND, OR, NOT, NAND, NOR, Ex-OR and verify
their truth tables.
APPARATUS USED:
 Bread Board
 Power supply
 Multimeter
 Hookup wire
 LEDs
 ICs 7400, 7402, 7404, 7408, 7432, 7486
THEORY: Logic gate is a digital circuit with one or more input but only one output. AND, OR,
NAND, NOR, NOT, Ex-OR Gates are some examples of Logic Gates.
AND Gate: AND Gate operation is represented by (A.B). In AND Gate, when two or more than
two input becomes high then output becomes high

Logic Symbol of AND Gate Truth-table of AND Gate

The 7408 IC is used for AND GATE. The pin diagram of 7408 IC is shown below:

Pin Diagram of AND Gate

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

OR Gate: The OR gate has two or more than two input and one output. This operation is
represented by a plus sign (A+B). The output voltage of OR Gate is high if any or all of the
input voltages are high.

Logic Symbol of OR Gate Truth-table of OR Gate

The 7432 IC is used for OR GATE. The pin diagram of 7432 IC is shown below:

Pin Diagram of OR Gate

NAND Gate: The function of NAND Gate is compliment of AND Gate. The logic equation is
(A.B)’.Output becomes high if any of the input becomes low.

Logic Symbol of NAND Gate Truth-table of NAND Gate

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

The 7400 IC is used for NAND GATE. The pin diagram of 7400 IC is shown below:

Pin-Diagram of NAND Gate

NOT Gate: It has one input and one output. This operation is represented by bar. If input is high
then output becomes low. When input becomes low then output becomes high.

Logic Symbol of NOT Gate Truth-table of NOT Gate

The 7404 IC is used for NOT GATE. The pin diagram of 7404 IC is shown below:

Pin-Diagram of NOT Gate

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

NOR Gate: The function of NOR Gate is compliment of OR Gate. The logic equation is (A+B)’.
Output becomes low if any of the input becomes high.

Logic Symbol of NOR Gate Truth-table of NOR Gate

The 7402 IC is used for NOR GATE. The pin diagram of 7402 IC is shown below:

Pin-Diagram of NOR Gate

Ex-OR Gate: The output of Ex-OR Gate becomes high if both two input are different. The logic
equation is AB’+A’B.

Logic Symbol of XOR Gate Truth-table of XOR Gate

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

The 7486 IC is used for XOR GATE. The pin diagram of 7486 IC is shown below:

Pin Diagram of XOR Gate

PROCEDURE:
 Connect the IC to the Bread-Board.
 Connect pin-7 of the ICs to GND supply and Connect pin-14 of the ICs to +5v supply using
patch-cords.
 Connect patch cords and wires according to circuit diagram.
 Observe the result by using LED lights conditions.

RESULTS:

POSSIBLE SOURCES OF ERROR:

 Wires connections may be improper.
 Patch-cord connections may be faulty.
 ICs may be damaged.

PRECAUTIONS:
 ICs should be placed in the middle of bread-board.
 All the wires should be tightly connected.

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Question: Draw the basic logic gates using minimum number of universal gates.

Question: Draw the XOR and XNOR gates using minimum number of universal gates.

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Experiment No. 2
AIM: To implement circuits for Binary-to-Gray & Gray-to-Binary code conversions.
APPARATUS USED:
 Bread Board & Power supply
 Hookup wire
 LEDs
 IC 7486(XOR gate)
THEORY:
Gray code is also known as Cyclic Code, Reflected Binary Code (RBC) or Reflected Binary (RB).
It is defined as an ordering of the binary number system such that each incremental value can only
differ by one bit. In gray code, while traversing from one step to another step only one bit in the
code group changes. That is to say that two adjacent code numbers differ from each other by only
one bit.
Binary to Gray Code Converter: The logical circuit which converts the binary code to equivalent
gray code is known as binary to gray code converter. It works according to the following steps:
1. The MSB (Most Significant Bit) of the gray code will be exactly equal to the first bit of the
given binary number.
2. The second bit of the code will be exclusive-or (XOR) of the first and second bit of the
given binary number, i.e. if both the bits are same the result will be 0 and if they are
different the result will be 1.
3. The third bit of gray code will be equal to the exclusive-or (XOR) of the second and third
bit of the given binary number. Thus the binary to gray code conversion goes on. The
circuit is given below to illustrate these steps.

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Circuit Diagram of Binary to Gray Code Converter

Gray to Binary Code Converter: In a gray to binary code converter, the input is gray code and
output is its equivalent binary code. It works according to the following steps:
1. The MSB of the binary number will be equal to the MSB of the given gray code.
2. Now if the second gray bit is 0, then the second binary bit will be the same as the previous
or the first bit. If the gray bit is 1 the second binary bit will alter. If it was 1 it will be 0 and
if it was 0 it will be 1.
3. This step is continued for all the bits to do Gray code to binary conversion. The circuit is
given below to illustrate these steps.

Circuit Diagram of Binary to Gray Code Converter

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

PROCEDURE:

 Connect the 7486(XOR) IC to the Bread-Board.

 Connect pin-7 of the IC to GND supply and Connect pin-14 of the IC to +5V supply using patch-
cords.
 Connect patch cords and wires according to circuit diagrams.
 Observe the result by using LED lights conditions.

POSSIBLE SOURCES OF ERROR:

 Wires connections
 Patch-cord connections
 Air Effect
 Environmental Factors

RESULT: With the help of 7486(XOR) IC we successfully implemented the binary to gray & gray
to binary code converter.

CONCLUSION: By using 7486 IC and the connections shown in the circuit diagrams, we can
perform the operation of binary to gray & gray to binary code converter.

PRECAUTIONS:
1 ICs should be placed in the middle of bread-board.
2 All the wires should be tightly connected.
3 Be sure about the locations of extinguishers and first aid kits in lab.

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Question: Given two binary numbers X=1010100 and Y=1000011, perform the
subtraction using 1’s and 2’s complements. (i) X–Y (ii) Y–X

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Experiment No. 3
AIM: To implement HALF ADDER & FULL ADDER circuits using basic logic gates and verify
their truth tables.
APPARATUS USED:
 Bread Board
 Power supply
 Hookup wire
 LEDs
 ICs 7486, 7408 and 7432

THEORY: An adder is a digital logic circuit in electronics that implements addition of numbers.
In many computers and other types of processors, adders are used to calculate addresses, similar
operations and table indices in the ALU and also in other parts of the processors. These can be
built for many numerical representations like excess-3 or binary coded decimal. Adders are
classified into two types: half adder and full adder. The half adder circuit has two inputs: A and B,
which add two input digits and generate a Carry and Sum as output. The full adder circuit has three
inputs: A, B and C, which add the three input numbers and generates a Carry and Sum.

HALF ADDER:

Block Diagram Truth Table

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Circuit Diagram

FULL ADDER:

Block Diagram Truth Table

Circuit Diagram

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

PROCEDURE:
 Mount the ICs on the Bread-Board.
 Connect pin-7 of each IC to GND and pin-14 to +5v supply using patch-cords.
 Connect patch cords and wires according to circuit diagram.
 Observe the results by using LED light conditions and verify them with the provided truth
table.

RESULTS:

POSSIBLE SOURCES OF ERROR:

 Wires connections may be improper.
 Patch-cord connections may have shorts.
 Damaged IC.
CONCLUSION: Implemented the HALF ADDER & FULL ADDER circuits using basic gate
ICs and verified their outputs.

PRECAUTIONS:
 ICs should be placed in the middle of bread-board.
 All the wires should be tightly connected.
Question: Draw the block diagram of 1’s complement circuit for 4-bit binary number

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Experiment No. 4
AIM: To Implement 4-bit parallel adder using 7483 IC.
APPARATUS USED:
 Bread Board Trainer Kit
 Power supply
 Hookup wire
 Patch Cords
 IC 7483 (4-bit Parallel/ Binary Adder)
THEORY: A binary parallel adder is a digital circuit that produces the arithmetic sum oftwo
binary numbers in parallel. It consists of full-adders connected in a chain, with theoutput carry
from each full-adder connected to the input carry of the next full-adder in thechain. An n-bit
parallel adder requires n full-adders. It can be constructed from 4-bit, 2bit, and I-bit full-adders ICs
by cascading several packages. The output carry from onepackage must be connected to the input
carry of the one with the next higher-order bits.The 4-bit full-adder is a typical example of an MSI
function. It can be used in manyapplications involving arithmetic operations. Observe that the
design of this circuit by theclassical method would require a truth table with 29 = 512 entries, since
there are nineinputs to the circuit. By using an iterative method of cascading an already known
function, we were able toobtain a simple and well-organized implementation.
Block Diagram of 4-bit Binary Adder:

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Verified Truth Table of 4-bit Binary Adder:

Pin diagram of 7483 IC:

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

PROCEDURE:

 Connect the IC to the Bread-Board.

 Connect pin-7 of the ICs to GND supply and Connect pin-14 of the ICs to +5v supply using path-
cords.
 Connect patch cords and wires according to circuit diagram.
 Observe the result by using LED lights conditions

POSSIBLE SOURCES OF ERROR:

 Wires connections
 Patch-cord connections
 Air Effect
 Environmental Factors

RESULT:

CONCLUSION: Verify the addition of two 4-bit binary number.

PRECAUTIONS:
1 ICs should be placed in the middle of bread-board.
2 All the wires should be tightly connected.
3 Be sure about the locations of extinguishers and first aid kits in lab.

Design 4-bit Binary Adder/Subtractor.

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Experiment No. 5
AIM: To implement One & Two Bit Comparator using logic gates.
APPARATUS USED:

 Basic logic gate ICs

 IC Trainer kit
 Power Supply
 LEDs
 Patch cords

THEORY:Single Bit Magnitude Comparator:- A comparator used to compare two bits, i.e., two
numbers each of single bit is called a single bit comparator. It consists of two inputs for allowing
two single bit numbers and three outputs to generate less than, equal and greater than comparison
outputs. The figure below shows the block diagram of a single bit magnitude comparator. This
comparator compares the two bits and produces one of the 3 outputs as L (A<B), E (A=B) and G
(A>B).

The truth table for the single bit comparator is given below. When A0 B0 = 00 & 11, both inputs
are equal, therefore A=B output will be high. When A0 B0 = 01, B is more than A and hence AB is
active.

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

From the truth table logical expressions for each output can be expressed as

By using these Boolean expressions, we can implement a logic circuit for this comparator
using two AND gates, one NOT gate and one Ex-NOR gate as shown in below figure.
AND gates are used to find whether a binary digit is less than greater than another bit
whereas Ex-NOR gate is used to find whether two binary numbers are equal or not.

In the figure, one AND gate has inputs of A0 (B0) ̅ and another has inputs (A0) ̅ B0.
Therefore, one AND gate output is 1 if A0 > B0 (i.e., A0 =1 and B0 =0) and is zero if A0 <
B0 (i.e., A0 =0 and B0 =1). Similarly, other AND gate output is one if A0 < B0 (i.e., A0 =0
and B0 =1) and is zero if A0 > B0 (i.e., A0 =1and B0 =0).
The Ex-NOR gate has inputs A0 B0, hence the output of the Ex-NOR gate will be 1 if A0 =
B0 and the output will be 0 if A0 is not equal to B0.
2-Bit Comparator:
A 2-bit comparator compares two binary numbers, each of two bits and produces their
relation such as one number is equal or greater than or less than the other. The figure below
shows the block diagram of a two-bit comparator which has four inputs and three outputs.

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

The first number A is designated as A = A1A0 and the second number is designated as B = B1B0.
This comparator produces three outputs as G (G = 1 if A>B), E (E = 1, if A = B) and L (L = 1 if

A<B).
The truth table of this comparator is shown below which depicting various input and output states.

The k-map simplification for the above truth table is as follows.

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

From the above k-map simplification, each output can be expressed as

By using above obtained Boolean equation for each output, the logic diagram can be
implemented by using four NOT gates, seven AND gates, two OR gates and two Ex-NOR
gates.
The figure below shows the logic diagram of a 2-bit comparator using basic logic gates. It
is also possible to construct this comparator by cascading of two 1-bit comparators.

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

PROCEDURE:

 Connect the IC to the Bread-Board.

 Connect pin-7 of the ICs to GND supply and Connect pin-14 of the ICs to +5v supply using path-
cords.
 Connect patch cords and wires according to circuit diagram.
 Observe the result by using LED lights conditions

POSSIBLE SOURCES OF ERROR:

 Wires connections
 Patch-cord connections

RESULT:

CONCLUSION: By using ICs, we can perform the operation of 1-bit and 2-bit comparator.

PRECAUTIONS:
1 ICs should be placed in the middle of bread-board.
2 All the wires should be tightly connected.
3 Be sure about the locations of extinguishers and first aid kits in lab.

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Question: Draw the logical table and circuit diagram for 4-bit Magnitude Comparator.

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Experiment No. 6
AIM: To implement and verify the truth table of 3x8 line decoder.
APPARATUS USED:
 Bread Board Trainer Kit
 Power supply
 Hookup wire
 Patch Cords
 IC 74138

THEORY: A decoder is a circuit that changes a code into a set of signals. It is called a decoder
because it does the reverse of encoding. A common type of decoder is the line decoder which takes an
n-digit binary number and decodes it into 2n data lines. Examples are 1 x 2 decoder, 2 x 4 decoder, 3x8
decoder.

TRUTH-TABLE of 3 X 8 DECODER:

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

BLOCK DIAGRAM & IC CONNECTION FOR 3 X 8 DECODER:

PROCEDURE:
 Connect the IC to the Bread-Board.
 Connect pin-8 of the IC to GND and Connect pin-16 of the ICs to +5v supply using patch-cords.
 Connect patch cords and wires according to circuit diagram.
 Observe the result by using LED lights conditions.

POSSIBLE SOURCES OF ERROR:

 Wires connections may be improper.
 Patch-cord connections may be faulty.
 IC may be damaged.

RESULT:

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CONCLUSION: By using 74318 IC, we can perform decoding of the given 3bit data.

PRECAUTIONS:
 ICs should be placed in the middle of bread-board.
 All the wires should be tightly connected.

Question: Realize Full adder circuit using 3x8 decoder.

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Experiment No. 7
AIM: To implement and verify the truth table of 4x1 and 8x1 MUX.
APPARATUS USED:
 Bread Board &Trainer Kit
 Power supply
 Hookup wire
 Patch Cords
 IC 7404(NOT gate)
 IC 7408(AND gate)
 IC 7432(OR gate)
 IC 7411(3 I/P AND gate)
 IC 74151(8x1 MUX)

THEORY: A multiplexer is a device which has a number of input lines, a number of selection
lines & one output line. It steers one of 2n inputs to a single output line, using n selection lines. It is
also known as a data selector.

Block Diagram of 4 X 1 Multiplexer:

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Truth-table of 4 X 1 Multiplexer:

Logic-diagram of 4 X 1 Multiplexer:

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Block Diagram & Truth table of 8 X 1 Multiplexer:

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

PROCEDURE:
 Connect the IC to the Bread-Board.
 Connect the diagonal pins of the IC to GND &+5V supply respectively using patch-cords.
 Connect patch cords and wires according to circuit diagram.
 Observe the result by using LED lights conditions.

POSSIBLE SOURCES OF ERROR:

 Wires connections may be improper.
 Patch-cord connections may be faulty.
 ICs may be damaged.
RESULT:

CONCLUSION: By using ICs, we can perform the multiplexing of the data.

PRECAUTIONS:
1 ICs should be placed in the middle of bread-board.
2 All the wires should be tightly connected.
3 Be sure about the locations of extinguishers and first aid kits in lab.

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Question: Implement all 2-input logic gates using 4:1 MUXs.

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Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Experiment No. 8
AIM: To verify the truth tables and excitation tables of RS, D, JK and T D flip-flops.
APPARATUS USED:
 Bread Board &Trainer Kit
 Power supply
 Hookup wire
 Patch Cords
 IC 7400 (NAND gate IC)

THEORY:
The basic building – block of any counter and shift register is a flip flop. Both counters and shift
registers contain chains of flip-flops. Different types of counters are realized by changing the feed-
back connection in the chain flip-flops. Just as NAND gate is the universal building block for logic
systems, the flip-flop is the basic element of memory units.

S-R flip-flop:

Fig: Circuit Diagram

Characteristic-Table:

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

D flip-flop:

Fig: Circuit Diagram

Characteristic-Table:

J-K flip-flop:

Fig: Circuit Diagram

Characteristic-Table:

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

T flip-flop:

Fig: Circuit Diagram

Characteristic-Table:

Excitation-Tables for SR, JK, D & T flip-flops:

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

PROCEDURE:

• Place the ICs on the Bread-Board.

• Connect pin-7 of the ICs to GND supply and Connect pin-14 of the ICs to +5v supply using
patch-cords.
• Connect patch cords and wires according to circuit diagram.
• Observe the result by using LED lights conditions

POSSIBLE SOURCES OF ERROR:

 Wires connections may be improper.

 Patch-cord connections may be faulty.
 ICs may be damaged.

RESULT:

CONCLUSION: By using 7400(NAND) ICs, we can implement and perform the operation of all
the flip-flops. And use a flip-flop as a one bit storage element.

PRECAUTIONS:
 ICs should be placed in the middle of bread-board.
 All the wires should be tightly connected.

BCS -352
 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Question: Convert the J K Flip-Flop into D flip-flop.

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Experiment No. 9
AIM: Design and verify a 4-bit asynchronous counter.
APPARATUS USED:

 IC Trainer kit
 patch cords
 JK-Flip-Flop (IC 7473)

THEORY: Ripple counters are so named because the count is like a chain reaction that ripples
through the counter because of the time involved. This effect will become more evident
with the explanation of the following circuit. The ripple counter is also called
an asynchronous counter. Asynchronous means that the events (setting and resetting of flip-
flops) occur one after the other rather than all at once. Because the ripple count is
asynchronous, it can produce erroneous indications when the clock speed is high. A high-
speed clock can cause the lower stage flip-flops to change state before the upper stages
have reacted to the previous clock pulse. The errors are produced by the flip-flops’ inability
to keep up with the clock.

Block Diagram:

BCS -352
 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

PROCEDURE:

 Connect the IC to the Bread-Board.

 Connect the ICs to GND supply and Connect ICs to +5v supply using path-cords.
 Connect patch cords and wires according to circuit diagram.
 Observe the result by using LED lights conditions

POSSIBLE SOURCES OF ERROR:

 Wires connections
 Patch-cord connections
 Damage IC

RESULT:

CONCLUSION: By using ICs, we can perform the operation of binary to gray code converter.

PRECAUTIONS:
1 ICs should be placed in the middle of bread-board.
2 All the wires should be tightly connected.
3 Power supply voltage should be +5 volt DC.

BCS -352
 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Question: Design MOD-5 Asynchronous counter.

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Experiment No. 10
AIM: To Design, and verify the 4-bit synchronous counter.
APPARATUS USED:
 J-K Flip-Flop (IC 7473 or IC 7476)
 AND Gate (IC 7408)
 Bread Board Trainer Kit
 patch cords

THEORY: Synchronous counters are simple state machines made out of flip flops and logic gates.
They have two parts, a register made out of flip flops and a decoder made out of logic gates. A
register is a simple group of flip flops that are all clocked at the same time. In this way they can
hold the counters output value until the next clock cycle. The decoder, decodes the current count
and generates the correct value for the next count to the flop flops. For example in a simple up
counter the decoder would always output the current count plus one. The major advantage of
Synchronous Counters is that all the bits of their output change at the same time.

Block Diagram:

BCS -352
 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

PROCEDURE:

 Connect the IC to the Bread-Board.

 Connect pin-7 of the ICs to GND supply and Connect pin-14 of the ICs to +5v supply using path-
cords.
 Connect patch cords and wires according to circuit diagram.
 Observe the result by using LED lights conditions

POSSIBLE SOURCES OF ERROR:

 Wires connections
 Patch-cord connections
 Air Effect
 Environmental Factors

RESULT:

CONCLUSION: By using ICs, we can perform the operation of synchronous counter.

PRECAUTIONS:
1 ICs should be placed in the middle of bread-board.
2 All the wires should be tightly connected.
3 Be sure about the locations of extinguishers and first aid kits in lab.

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 PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

Question: Design MOD-5 synchronous counter.

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