B R Harne College of Engineering and Technology, Vangani

LABORATORYMANUAL
DLCOA R-19Scheme CSL304 Sem:III
Sr.No. NameofExperiment PageNo.

1 To apply the fundamentals of the digital logic for verifying the truth tables of 2-5
logic gates.
2 To develop binary to gray and gray to binary code converter. 6-10
3 To develop a half adder and full adder circuit using logic gates and verify it 11-14
using truth table.
4 To verify the truth tables of JK, D & T flip flop. 15-17
5 To implement Booth’s multiplication algorithm using C programming. 18-25
6 To implement restoring division algorithm using C programming 26-30
7 To implement non-restoring division algorithm using C programming 31-35
language.
8 To apply the basics of arithmetic & logical processing for ALU design. 36-38
9 To make use of the knowledge of memory organization for implementing 39-42
memory design.
10 To implement cache memory design with the help of concepts of memory 43-47
organization.

Prepared by:

Prof. Sanika Swami

Computer Engineering / BRHCET, Vangani

Experiment No.01

STUDYOF BASICGATES

AIM: To study and verify the truth table of various logic gates using ICs and realize

Booleanexpressions using gates.

APPARATUSREQUIRED:PowerSupply,Breadboard,Connectingwires

COMPONENTS:ICs7400,7402,7404, 7408,7432, 7486

ICPINOUTS TRUTH-TABLE
NAND
A B Y=A.B
0 0 1
0 1 1
1 0 1
1 1 0

NOR
A B Y=A+B
0 0 1
0 1 0
1 0 0
1 1 0

DLCOA /CSL 302/ Sem- III Page2

Computer Engineering / BRHCET, Vangani

NOT

A Y=A

0 1

1 0

AND

A B Y=A.B

0 0 0

0 1 0

1 0 0

1 1 1

OR

A B Y=A+B

0 0 0

0 1 1

1 0 1

1 1 1

DLCOA /CSL 302/ Sem- III Page3

Computer Engineering / BRHCET, Vangani

EX-OR

A B Y=AB+AB

0 0 0

0 1 1

1 0 1

1 1 0

THEORY

Logic gates are the digital circuits with one output and one or more inputs. They are the basicbuilding

blocks of any logic circuit. Different logic gates are: AND, OR, NOT, NAND, NOR, EX-OR.They

workaccording tocertain logic.

AND:Logiceqn.Y=A.B

TheoutputofAND gateis true whentheinputsAandBareTrue.

OR:Logiceqn.Y=A+B.

TheoutputofOR gateistruewhen oneofthe inputs AandBorboththeinputs aretrue.

NOT:Logiceqn.Y= .

TheoutputofNOTgateis complementoftheinput.

NAND:Logiceqn.Y=

TheoutputofNANDgateistruewhenoneoftheinputs or boththeinputsarelowlevel.

NOR:Logicaleqn.Y= .

TheoutputofNORgateis truewhenboththeinputsarelow.

DLCOA /CSL 302/ Sem- III Page4

Computer Engineering / BRHCET, Vangani

EX-OR:Logiceqn.Y= .

TheoutputofEX-ORgateistrue whenboththeinputs arelow.

Implementationfor 2input variables

ImplementtheBooleanfunctionbyusingbasiclogic gates. F=(A+B)*(A+ B’)

Inthegivenfunctioncompliment input, we are using the NOT gates at the input side. And to represent the sum

term,weuseORgates.Seethebelowgivenlogic diagramforrepresentationoftheBooleanfunction.

PROCEDURE

1) GivebiasingtotheICanddo necessaryconnections.

2) Givevariouscombinations of inputsand note down the output forall gateICsone byone.

1)3)Realizetheexpressionusingbasicgates.

CONCLUSION

Thus, all basicgatesarestudied.

,wehavea complementterm,(A+B)and(A+ B’).So,torepresentthe

DLCOA /CSL 302/ Sem- III Page5

Computer Engineering / BRHCET, Vangani

ExperimentNo.02
BINARYTOGREYCODEANDGREYTOBINARYCODECONVERSION

AIM: Torealizebinarytograycode and graycodeto binaryconverter.

APPARATUS:Powersupply, Breadboard,connectingwire.

COMPONENTS:IC7486.

THEORY:

The availability of large variety of codes for the same discrete elements of information results inthe use of

different codes by different systems. A conversion circuit must be inserted betweenthe two systems if

each uses different codes for same information. Thus, code converter is a circuit that makes the two

systems compatible even though each uses different binary code.

The bit combination is assigned to binary code to gray code. Each code uses four bits torepresent a

decimal digit. There are four inputs and four outputs. Gray code is a non-weightedcode.

The input variables are designated as B3,B2,B1,B0 and the output variables are designated as C3, C2, C1,

Co. from the truth table, combinational circuit is designed. The Boolean functions are obtained from K-

Map for each output variable.

A code converter is a circuit that makes the two systems compatible even though each uses adifferent

binary code. To convert from binary code to Excess-3 code, the input lines must

supplythebitcombinationofelementsasspecifiedbycodeandtheoutputlinesgeneratethecorresponding bit

combination of code. Each one of the four maps represent one of the fouroutputsofthecircuitasafunction

ofthefourinputvariables.

A two-level logic diagram may be obtained directly from the Boolean expressions derived by themaps.

These are various other possibilities for a logic diagram that implements this circuit. Now the OR gate

whose output is C+D has been used to implement partially each of three outputs.

DLCOA /CSL 302/ Sem- III Page6

Computer Engineering / BRHCET, Vangani

TRUTHTABLE

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-MapforG3: K-MapforG2:

G3 = B3

DLCOA /CSL 302/ Sem- III Page7

Computer Engineering / BRHCET, Vangani

K-MapforG1 K-MapforG0

K-MapforB3: K-Map forB2:

B3 =G3

K-MapforB1: K-Map forB0:

PROCEDURE:

DLCOA /CSL 302/ Sem- III Page8

Computer Engineering / BRHCET, Vangani

1) Connect VCC and ground pins of IC to the power supply.

2) Connect the circuit as shown in the figure.

3) Obtain output for different combinations of inputs.

4) Verify truth tables.

BINARY TO GRAY CODE

CONVERTOR:CIRCUITDIAGRAM:

Gray to binary conversion Truth Table

0G3 0G2 0G1 1G0 0B3 0

B2 0
B1 1
B0
00 00 10 10 00 00 01 00
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

DLCOA /CSL 302/ Sem- III Page9

Computer Engineering / BRHCET, Vangani

CIRCUITDIAGRAM:

RESULT:
Thus, conversionfromgrey tobinaryandbinarytogreycodeconversionisstudied.

DLCOA /CSL 302/ Sem- III Page10

Computer Engineering / BRHCET, Vangani

ExperimentNo.03
DESIGNA(I)HALFADDERAND(II)FULLADDER

AIM: To realize arithmetic circuits i) Half adder ii) Full

adder.APPARATUS: Power supply, Breadboard, connecting

wire.COMPONENTS:IC 7408,7486,7404,7432.

THEORY:

HALFADDER:

A half adder has two inputs for the two bits to be added and two outputs one from the sum ‘S’and other

from the carry ‘c’ into the higher adder position. The circuit is called as a carry signalfrom the addition of

the less significant bits sum from the X-OR Gate the carry out from the ANDgate.

FULLADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of threeinputs

and two outputs. A full adder is useful to add three bits at a time but a half adder cannotdo so. In full

adder sum output will be taken from X-OR Gate, carry output will be taken from ORGate.

DLCOA /CSL 302/ Sem- III Page11

Computer Engineering / BRHCET, Vangani

TRUTHTABLEOFHALFADDER:

A B CARRY SUM

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

K-MapforSUM: K-MapforCARRY

SUM=A’B+AB’ CARRY=AB

=AB

CIRCUITDIAGRAM:

DLCOA /CSL 302/ Sem- III Page12

Computer Engineering / BRHCET, Vangani

TRUTHTABLEOFFULLADDER:
A B C CARRY SUM

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

K-MAPFORSUM:

SUM=A’B’C+A’BC’+ABC’+ABC

=A B C

DLCOA /CSL 302/ Sem- III Page13

Computer Engineering / BRHCET, Vangani

K-MAPFORCARRY:

CARRY=AB+BC +AC

CIRCUITDIAGRAM:

PROCEDURE:
1) Connectionsaregivenaspercircuitdiagram.

2) Logicalinputsaregivenaspercircuitdiagram.

3) Observethe outputandverifythetruthtable.

RESULT:

Thus,thehalfadder andfulladder wasdesignedandtheirtruthtableis verified

DLCOA /CSL 302/ Sem- III Page14

Computer Engineering / SSJCET, Asangaon

Experiment
No. 04

FLIP-FLOPS

AIM: Design the JK and SR Flip Flop using NAND as Universal gate.

Verify the truth table of JK FlipFlop using IC7476. Implement T FlipFlop and DFlip Flop using

JK Flip Flop

APPARATUS REQUIRED : Power supply, Breadboard

COMPONENTS:IC7400,IC7410,IC7473, IC7474,IC7476

PindiagramofIC-
7476

CIRCUITDIAGRAMANDTRUTHTABLE:
I) SRFFusingNAND

DLCOA /CSL 302/ Sem- III Page15

Computer Engineering / SSJCET, Asangaon

II) JKFF usingNAND

III) JKFF(IC7476)

Clk J K Q Q Comment

0 0 NC NC NoChange

0 1 0 1 Reset

1 0 1 0 Set

1 1 Toggle Toggle

DLCOA /CSL 302/ Sem- III Page16

Computer Engineering / SSJCET, Asangaon

IV) TFFusingJK
Clk T Q Q

0 NC NC

1 Toggle

V) DFFusingJK

Clk D Q Q Comment

0 0 0 Reset

1 1 1 Set

THEORY:
Flip-flops are the basic building blocks of sequential ckt. The clocked FFs change their o/p state

depending upon i/p's at certain interval of time synchronized with the clock pulse applied to it.

Different types of FFs are S-R, J-K, D&T. Their operations are described by the respective

truthtables. MSI chip 7476 incorporates two negative edge triggered Master–Slave JK flip flops.

TheJ-Kflip flop canbeconvertedtoD&T flipflop.

PROCEDURE:

1) Give biasing to the IC and do necessary connections.

2) Forvariouscombinationsof i/pverifythetruthtable.

CONCLUSION:

ThusR-S,J-K,D&TFlip-Flops arestudied.

DLCOA /CSL 302/ Sem- III Page17

Computer Engineering / SSJCET, Asangaon

EXPERIMENT 5
BOOTHS MULTIPLICATION ALGORITHM

Aim: To implement Booths multiplication algorithm using C

programminglanguage.
Software: C language

Theory:
The multiplicand and multiplier are placed in the BR and QR registers respectively. A 1 bit
registeris placed logically to the right of the LSB (least significant bit) Qn of Q register. This is
denoted
byQn+1.AandQn+1isinitiallysetto0.ControllogicchecksthetwobitsQnandQn+1.Ifthetwobitsaresame(00
or11)thenallofthebitsofA,Q,Qn+1areshifted1bittotheright.Iftheyarenotthesameand if the combination
is 10 then the multiplicand is subtracted from A and if the combination is
01thenthemultiplicandisaddedwithA.InboththecasesresultsarestoredinA, andaftertheadditionor
subtraction operation, A, Q, Qn+1 are right shifted. The shifting is the arithmetic right
shiftoperationwheretheleftmostbitnamely,An-1isnotonlyshiftedintoAn-2butalsoremainsinAn-
1.ThisistopreservethesignofthenumberinAandQ.Theresultofthemultiplicationwillappearinthe A
andQ.

Program:
#include
<stdio.h>#includ
e<math.h>
inta =0,b= 0,c = 0,a1 = 0,b1 =0,com[5] ={ 1,0,0,0, 0};
intanum[5] = {0},anumcp[5] ={0}, bnum[5]= {0};
intacomp[5]={0},bcomp[5] ={0}, pro[5]= {0},res[5] ={0};

void

DLCOA /CSL 302/ Sem- III Page18

Computer Engineering / SSJCET, Asangaon

binary(){a1 =
fabs(a);b1=
fabs(b);
intr, r2,i,temp;
for(i=0;i<5;i++){
r= a1% 2;
a1 = a1 /
2;r2=b1%2;
b1 = b1 / 2;anum[i] =
r;anumcp[i]=r;bnum[i
] = r2;if(r2==0){
bcomp[i] =1;
}
if(r==0){
acomp[i]=1;
}
}
//part for two's
complementingc = 0;
for( i= 0;i<5;i++){
res[i] = com[i]+ bcomp[i] +
c;if(res[i]>= 2){
c = 1;
}
else
c = 0;
res[i]=res[i] %2;
}
for(i= 4;i>= 0;i--){

DLCOA /CSL 302/ Sem- III Page19

 Computer Engineering / SSJCET, Asangaon

bcomp[i]=res[i];
}
//incaseofnegativeinputs

if (a
<0){c =
0;
for (i = 4; i>= 0; i--){res[i]= 0;
}
for( i= 0;i<5;i++){
res[i] = com[i] + acomp[i] +
c;if(res[i]>= 2){
c = 1;
}
else
c = 0;
res[i]=res[i]%2;
}
for(i= 4;i>= 0;i--){
anum[i] =
res[i];anumcp[i]=res[i];
}

}
if(b<0){
for (i = 0; i< 5; i++){temp =
bnum[i];bnum[i] =
bcomp[i];bcomp[i]=temp;
}
}

DLCOA /CSL 302/ Sem- III Page20

Computer Engineering / SSJCET, Asangaon

}
voidadd(intnum[]){

int
i;c=0
;
for( i= 0;i<5;i++){
res[i]=pro[i]+ num[i]+c;
if (res[i] >=
2){c = 1;
}
else{
c = 0;
}
res[i]=res[i]%2;
}
for(i= 4;i>= 0;i--){
pro[i] =
res[i];printf("%d",pro[i]);
}
printf(":");
for(i= 4;i>= 0;i--){
printf("%d",anumcp[i]);
}
}
voidarshift(){//forarithmeticshiftrighti
nttemp =pro[4],temp2=pro[0],i;

for (i = 1; i<5 ;i++){//shift the MSB of

productpro[i-1]=pro[i];

DLCOA /CSL 302/ Sem- III Page21

Computer Engineering / SSJCET, Asangaon

}
pro[4]=temp;
for (i = 1; i<5 ;i++){//shift the LSB of
productanumcp[i-1]=anumcp[i];

}
anumcp[4]=temp2;
printf("\nAR-SHIFT: ");//display
togetherfor(i= 4;i>= 0;i--){
printf("%d",pro[i]);
}
printf(":");
for(i =4;i>= 0;i--){
printf("%d",anumcp[i]);
}
}

void
main(){inti
,q=0;
printf("\t\tBOOTH'SMULTIPLICATIONALGORITHM");
printf("\nEntertwonumberstomultiply:");printf(
"\nBothmustbelessthan 16");
//simulating for two numbers each
below 16do{
printf("\nEnter A:
");scanf("%d",&a);
printf("EnterB:");
scanf("%d",&b);

DLCOA /CSL 302/ Sem- III Page22

Computer Engineering / SSJCET, Asangaon

}while(a>=16 ||b >=16);

printf("\nExpected product = %d", a *

b);binary();
printf("\n\nBinary Equivalents are:
");printf("\nA=");

for(i= 4;i>= 0;i--){

printf("%d",anum[i]);
}
printf("\nB=");
for(i= 4;i>= 0;i--){
printf("%d",bnum[i]);
}
printf("\nB'+1=");
for(i= 4;i>= 0;i--){
printf("%d",bcomp[i]);
}
printf("\n\n");
for(i= 0;i<5;i++){
if (anum[i] == q){//just shift for 00 or
11printf("\n-->");
arshift();
q=anum[i];
}
else if(anum[i] == 1 && q == 0){//subtract and shift for
10printf("\n-->");
printf("\nSUBB:");
add(bcomp);//add two's complement to implement

DLCOA /CSL 302/ Sem- III Page23

Computer Engineering / SSJCET, Asangaon

subtractionarshift();
q=anum[i];
}
else{//add ans shift for
01printf("\n-->");
printf("\nADD B:
");add(bnum);
arshift();
q=anum[i];
}
}

printf("\nProduct is =
");for(i= 4;i>= 0;i--){
printf("%d",pro[i]);
}
for(i= 4;i>= 0;i--){
printf("%d",anumcp[i]);
}
}
Conclusion: Booths multiplication algorithm has studied and implemented successfully.
Output:

DLCOA /CSL 302/ Sem- III Page24

Computer Engineering / SSJCET, Asangaon

DLCOA /CSL 302/ Sem- III Page25

Computer Engineering / SSJCET, Asangaon

EXPERIMENT6
RESTORINGDIVISIONALGORITHM
Aim: ToimplementRestoringDivisionalgorithmusingCprogramminglanguage.
Software: Clanguage
Theory: Restoring division Restoring division operates on fixed-point fractional numbers
anddepends on the following assumptions: The following division methods are allbased on the
formQ= A/M
where

 Q=Quotient
 A=Numerator(dividend)
 M=Denominator(divisor).

Step-1:Firsttheregistersareinitializedwithcorrespondingvalues(Q=Dividend,M=Divisor,A= 0,n =
number ofbitsin dividend)
Step-2:ThenthecontentofregisterAandQisshiftedleftasiftheyareasingleunit
Step-3:ThencontentofregisterMissubtractedfromAandresultisstoredinA
Step-
4:ThenthemostsignificantbitoftheAischeckedifitis0theleastsignificantbitofQissetto1otherwiseifitis1
theleastsignificantbitofQissetto0andvalueofregisterAisrestoredi.ethevalueofAbeforethesubtraction
withM
Step-5:Thevalueofcounternisdecremented
Step-6:Ifthevalueofnbecomeszerowegetoftheloopotherwisewerepeatfromstep2
Step-7:Finally,theregisterQcontainthequotientandAcontainremainder

DLCOA /CSL 302/ Sem- III Page26

Computer Engineering / SSJCET, Asangaon

Program:

/*ProgramforimplementingRestoringDivisionalgorithm.*/#include<stdio.h>#includ
e<math.h>

inta=0,b=0,c=0,com[5]={1,0,0,0,0},s=0;
intanum[5]={0},anumcp[5]={0},bnum[5]={0};
intacomp[5]={0},bcomp[5]={0},rem[5]={0},quo[5]={0},res[5]={0};

voidbinary(){
a=fabs(a);b=fabs(b);
intr,r2,i,temp; for(i=0;i<5;i++){

DLCOA /CSL 302/ Sem- III Page27

 Computer Engineering / SSJCET, Asangaon

r=a%2;a=a
/2;r2=b%2;
b=b/2;anum[i]=r;anu
mcp[i]=r;bnum[i]=r2;
if(r2==0){
bcomp[i]=1;
}
if(r==0){
acomp[i]=1;
}
}
//partfortwo'scomplementingc=0;f
or(i=0;i<5;i++){
res[i]=com[i]+bcomp[i]+c;if(res[i]>=2){c=1
;
}
else
c=0;
res[i]=res[i]%2;
}
for(i=4;i>=0;i--){
bcomp[i]=res[i];
}
}
voidadd(intnum[]){inti;c=0;

for(i=0;i<5;i++){
res[i]=rem[i]+num[i]+c;
if(res[i]>=2){
c=1;
}
else
c=0;
res[i]=res[i]%2;
}
for(i=4;i>=0;i--){
rem[i]=res[i];printf("
%d",rem[i]);
}
printf(":");
for(i=4;i>=0;i--){
printf("%d",anumcp[i]);
}
}
voidshl(){//forshiftleftinti;
for(i=4;i>0;i--){//shifttheremainderrem[i]=rem[i-1];
}

DLCOA /CSL 302/ Sem- III Page28

Computer Engineering / SSJCET, Asangaon

rem[0]=anumcp[4];
for(i=4;i>0;i--){//shifttheremtientanumcp[i]=anumcp[i-1];
}
anumcp[0]=0;
printf("\nSHIFTLEFT:");//displaytogetherfor(i=4;i>=0;i--
){printf("%d",rem[i]);
}
printf(":");
for(i=4;i>=0;i--){
printf("%d",anumcp[i]);
}
}

voidmain(){
clrscr();inti;
printf("\t\tRESTORINGDIVISIONALGORITHM");
printf("\nEnter twonumbers tomultiply: ");printf("\nBoth
mustbelessthan16");
//simulatingfortwonumberseachbelow16do{

printf("\nEnterA:");s
canf("%d",&a);
printf("EnterB:");
scanf("%d",&b);
}while(a>=16||b>=16);

printf("\nExpectedQuotient
=%d",a/b);printf("\nExpectedRemainder=%d",a%b);if(a*b<0){
s=1;
}

binary();
printf("\n\nUnsignedBinaryEquivalentsare:");printf("\nA=");for(i=4;i>=0;i
--){
printf("%d",anum[i]);
}
printf("\nB=");
for(i=4;i>=0;i--){
printf("%d",bnum[i]);
}
printf("\nB'+1=");
for(i=4;i>=0;i--){
printf("%d",bcomp[i]);
}
printf("\n\n-->");
//divisionpartshl();for(i=0;i
<5;i++){

DLCOA /CSL 302/ Sem- III Page29

Computer Engineering / SSJCET, Asangaon

printf("\n-->"); //start with subtractionprintf("\nSUB B:

");add(bcomp);
if(rem[4]==1){//simplyaddforrestoringprintf("\n--
>RESTORE");
printf("\nADDB:");anumcp[0]
=0;add(bnum);
}
else{

}
if(i<4)

}
anumcp[0]=1;

shl();printf("\n ");

printf("\nSignoftheresult=%d",s);printf("\nR
emainderis=");
for(i=4;i>=0;i--){
printf("%d",rem[i]);
}
printf("\nQuotientis=");for(i=4;i>=0;i--){
printf("%d",anumcp[i]);
}
getch();

}
Conclusion:Thus Restoring Division algorithm has been studied and implemented successfully.
Output:

DLCOA /CSL 302/ Sem- III Page30

Computer Engineering / SSJCET, Asangaon

EXPERIMENT 7
NON-RESTORINGDIVISIONALGORITHM
Aim: ToimplementNon-
RestoringDivisionalgorithmusingCprogramminglanguage.
Software: Clanguage
Theory:Non-restoringdivisionalgorithmisusedtodividetwounsignedintegers.Thisalgorithmis
different fromthe other algorithm becausehere, there is no conceptof restoration and
thisalgorithm is less complex than the restoring division algorithm. Algorithm for Non-
restoringdivisionisas givenbelow

DLCOA /CSL 302/ Sem- III Page31

Computer Engineering / SSJCET, Asangaon

Program:
/*CProgramForImplementationOfNon-RestoringDivision*/

#include<stdio.h>
#include<conio.h
>

inta[5]={0,0,0,0,0},q[4],b[5],b2c[5];

comp()
{
inti=4;
do
{
b2c[i
]=b[i
];i--;
}while(b[i+1]
!=1);
while(i>=0)
{
b2c[i]=(b[i]
+1)%2;i--;
}
printf("\n\tB'scomplement:");fo
r(i=0;i<
5;i++)printf("%d",b2c[i]);printf("
\n");
}

nonresdiv()
{
shiftleft();if(a
[0
]==0
)
a_minus_b();elsea
_plus_b(
);

DLCOA /CSL 302/ Sem- III Page32

Computer Engineering / SSJCET, Asangaon

q[3]=(a[0]+1)%2;
}

shiftleft()
{
int i;for(i=0;i<4;i++)
a[i]=a[i+1];a[4]=q[0];
for(i=0;i<3;i++)
q[i]=q[i+1];
}

a_minus_b()
{
inti,carry=0,sum
=0;
for(i=4;i>=0;i
--)

{
sum=(a[i]+b2c[i]+carry);a[i]
=sum%2;carry=sum/2;
}
}

a_plus_b()
{
inti,carry=0,sum
=0;
for(i=4;i>=0;i
--)
{
sum=(a[i]+b[i]+carry);a[i]=su
m%2;carry=sum/2;
}
}

voidmain()
{
inti,j,k;
clrscr();
printf("Enterdividend

DLCOA /CSL 302/ Sem- III Page37

Computer Engineering / SSJCET, Asangaon

inbinaryform\t:");for(i=0;i<4;i++)
scanf("%d",&q[i]);printf("Enter divisor
in binaryform\t:");for(i=0;i<5;i++)
scanf("%d",&b[i])
;comp();printf("\n\t[A]\t[M]
\n");for(i=0;i<4;i++)
{
nonresdiv()
;
printf("\t");for(j=0;j<5;
j++)
printf("%d"
,a[j]);
printf("\t");for(k=0;k<
4;k++)

printf("%d"
,q[k]);
printf("\n")
;
}
if(a[0
]==1
)
a_plus_b();printf("\t");for(
j=0;j<5;j++)
printf("%d",a[j]);
printf("\t");for(k=0;k<
4;k++)
printf("%d",q[k]);
printf("\n");printf("\n\tTheQu
otient Is\t:
");for(k=0;k<4;k++)

printf("%d",q[k]);printf("\n\tTheR
emainderIs\t: ");for(j=0;j<
5;j++)printf("%d",a
[j]);getch();
}
Conclusion:ThusNon-RestoringDivisionalgorithmhasbeenstudiedandimplementedsuccessfully.

DLCOA /CSL 302/ Sem- III Page37

Computer Engineering / SSJCET, Asangaon

Output:

DLCOA /CSL 302/ Sem- III Page37

Computer Engineering / SSJCET, Asangaon

ExperimentNo.08
Design of Arithmetic Logic Unit
OBJECTIVE:
1. Understandingbehaviorofarithmeticlogicunitfromworkingmoduleandthemoduledesignedby
thestudent aspartoftheexperiment.
2. Designinganarithmeticlogicunitforgivenparameter.

THEORY:
ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like addition,subtraction,
division, multiplication and logical operations like and, or, xor, nand, nor
etc.Asimpleblockdiagramofa4bitALUforoperationsand,or,xorandAddisshownhere
:

The 4-bitALUblockiscombinedusing41-bitALU block

DLCOA /CSL 302/ Sem- III Page37

Computer Engineering / SSJCET, Asangaon

Design Issues:

Thecircuitfunctionalityofa1-
bitALUisshownhere,dependinguponthecontrolsignalS 1andS0thecircuitoperatesasfollows:

forControlsignalS1=0,S0=0,theoutputisAAndB,for

Control signal S1 = 0, S0 = 1, the output is A Or B,for

Control signal S1 = 1, S0 = 0, the output is A Xor B,for

ControlsignalS1=1,S0=1,theoutput isAAdd B.

PROCEDURE:
Startthesimulatorasdirected.Thissimulatorsupports5-valuedlogic.
To design the circuit we need 4 1-bit ALU, 11 Bit switch (to give input, which
willtoggleitsvaluewithadoubleclick), 5Bitdisplays (forseeingoutput),wires.
Thepinconfigurationofacomponentisshownwheneverthemouseishoveredonany canned
component of the palette. Pin numbering starts from 1 and from thebottomleftcorner
(indicatingwiththecircle)andincreasesanticlockwise.
For1-bitALUinputA0isinpin-9,B0isinpin-10,C0isinpin-11(thisisinputcarry),for selection of
operation, S0 is in pin-12, S1 is in pin-13, output F is in pin-8 andoutputcarry is pin-7
Click on the 1-bit ALU component (in the Other Component drawer in the pallet)and then
click on the position of the editor window where you want to add thecomponent (no drag
and drop, simple click will serve the purpose), likewise add 3more 1-bit ALU (from the
Other Component drawer in the pallet), 11 Bit
switchesand5BitDisplays(fromDisplayandInputdrawerofthepallet,ifitisnotseenscrolldown
in the drawer), 3 digital display and 1 bit Displays (from Display and Inputdrawerof
thepallet, ifitisnot seenscrolldownin the drawer)
To connect any two components, select the Connection menu of Palette, and
thenclickontheSourceterminalandclickonthetargetterminal.Accordingtothe

DLCOA /CSL 302/ Sem- III Page37

Computer Engineering / SSJCET, Asangaon

circuit diagram connects all the components. Connect the Bit switches with theinputs and
Bit displays component with the outputs. After the connection is overclickthe selection
tool in thepallet.
See the output, in the screenshot diagram we have given the value of S1
S0=11whichwillperformaddoperationandtwonumber input asA0A1A2A3=0010andB0 B1
B2 B3=0100 so get output F0 F1 F2 F3=0110 as sum and 0 as carry
whichisindeedanaddoperation,youcanalsousemanyothercombinationsofdifferentvalues
and check the result. The operations are implemented using the truth tablefor4-
bitALUgiven in the theory.

Components:

Tobuildany4-bitALU,weneed:

ANDgate,ORgate,XORgate
FullAdder,
4-to-1 MUX<
Wirestoconnect.
OUTPUT:

CONCLUSION:ArithmeticLogicUnithasbeendesignedandsimulated.

DLCOA /CSL 302/ Sem- III Page37

Computer Engineering / SSJCET, Asangaon

ExperimentNo.09
Design Of4x3RAM

OBJECTIVE:Todesignmemoryunitsandunderstandhowitoperatesduringreadandwrite operation.
understandingbehaviorofmemoryfromworkingmoduleandthemoduledesignedby the
studentaspartoftheexperiment
designinganmemory forgivenparameter

THEORY:
A memory unit is a collection of storage cells together with associated circuits needed
totransform information in and out of the device. Memory cells which can be accessed
forinformation transfer to or from any desired random location is called random
accessmemory(RAM).Theblock diagramofamemoryunit-

InternalConstruction:Theinternalconstructionofarandom-accessmemoryofmwordswithn
bitsperwordconsists ofm*n binarystoragecellsand associateddecoding

DLCOA /CSL 302/ Sem- III Page37

Computer Engineering / SSJCET, Asangaon

circuitsforselectingindividualwords.Thebinarycellisthebasicbuildingblockofamemoryunit.

PROCEDURE:
1. Startthesimulatorasdirected.Thissimulatorsupports5-valuedlogic.
2. Todesignthecircuit,weneed12binaryRAMcell,9ORgate, 7-bitswitch (togiveinput,
which will toggle its value with a double click), 3-bit display (to see theoutput),
wires.
3. Thepinconfigurationofacomponentisshownwheneverthemouseishoveredonany
canned component of the palette or press the 'show pinconfig' button.
Pinnumbering starts from 1 and from the bottom left corner (indicated with the
circle)andincreasesanticlockwise.
4. For a binary RAM cell input is in pin-5, output is in pin-4 and select is pin-

8,Read/Write is in pin-6, for read operation give 1 input to Read/Write pin. For
writeoperationgive0input to Read/Writepin.
5. For a 'decoder with enable', input A is in pin-6, B is in pin-5, output D0 is in pin-

4,D1 is inpin-3,D2 is inpin-2,D3 isinpin-1andenableis inpin-8

6. Clickonthe'decoderwithenable'component(intheOtherComponentsdrawerinthe
pallet) and then click on the position of the editor window where you
wanttoaddthecomponent(nodraganddrop,simpleclickwillservethepurpose),likewis
eadd 12 binary RAM cell (from the Other Components drawer in the pallet), 9
ORgates (from Logic Gates drawer in the pallete), 7 bit switches (whichwill
toggle
itsvaluewithadoubleclick),3bitdisplays(fromDisplayandInputdrawerofthepallet,ifitis
notseen scrolldowninthedrawer)

DLCOA /CSL 302/ Sem- III Page37

Computer Engineering / SSJCET, Asangaon

7. Toconnectanytwocomponents,selecttheConnectionmenuofPalette,andthenclickon

theSourceterminalandclickonthetargetterminal.Accordingtothecircuitdiagram
connect all the components, connect 2-bit switches to the inputs
ofthe'decoderwithenable'(whichwillactasaddressinput),1bitswitchtothe

enable pin of the 'decoder with enable' (which will act as memory enable input),connect a
bit switch to the Read/Write(R/W') line, 3-bit switches to the data inputsline, 3 bit displays
to the data output line and OR gates according to the diagramshown in the circuit
diagram. After the connection is over click the selection tool inthepallete.

DLCOA /CSL 302/ Sem- III Page37

Computer Engineering / SSJCET, Asangaon

8. Toseethecircuitworking,DosomereadorwriteoperationbyproperlysettingtheR/W',

memory enable then give input and check the output. suppose
yougive,R/W'=1,memoryenable=1,addressinput=01,datainput=101,thenitwillbear
eadoperationandyouwillnotsee101asoutput,itwillstore101intheword-
1. now again set, R/W'=0, memory enable=1, address input=01, then it will be
awriteoperationandyouwillsee101asthecontentofword-1ontheoutputdisplay.

OUTPUT:

CONCLUSION:A4*3RandomAccessMemoryhasbeendesignedandsimulated.

DLCOA /CSL 302/ Sem- III Page37

Computer Engineering / SSJCET, Asangaon

Experiment No.10

Design of Direct Mapped Cache

OBJECTIVE:

1. Understandingbehaviorofdirectmappedcachefromworkingmodule

2. Designingadirectmappedcacheforgivenparameters

THEORY:
Cache memory is a small (in size) and very fast (zero wait state) memory which sitsbetween the
CPU and main memory. The notion of cache memory actually rely on thecorrelation properties
observed in sequences of address references generated by CPUwhile executing a program
(principle of locality). When a memory request is generated,the request is first presented to the
cache memory, and if the cache cannot respond, therequestis thenpresented to mainmemory.
 Hit:a cacheaccessfindsdataresidentin thecachememory
 Miss: a cache access does not find data resident, so it forces to access the
mainmemory.

Cache treats main memory as a set of blocks. As the cache size is much smaller
thanmainmemorysothenumberofcachelinesareverylessthanthenumberofmainmemoryblocks. So
a procedure is needed for mapping main memory blocks into cache
lines.Cachemappingschemeaffectscostandperformance.Therearethreemethodsinblockplacemen
t-

 DirectMappedCache
 FullyAssociativeMappedCache
 SetAssociativeMappedCache

DLCOA /CSL 302/ Sem- III Page37

Computer Engineering / SSJCET, Asangaon

DirectMappedCache
Agivenmemoryblockcanbemappedintooneandonlycacheline.

Block identification: let the main memory contains n blocks (which require log 2(n)) andcache
contains m blocks, so n/m different blocks of memory can be mapped (at differenttimes) to a
cache block. Each cache block has a tag saying which block of memory iscurrently present in it,
each cache block also contains a valid bit to ensure whether amemoryblock is
inthecacheblockcurrently.

 Numberofbits inthetag:log2(n/m)
 NumberofsetsintheCache:m
 Numberofbitsto identifythecorrect set:log 2(m)

The memory address is divided into 3 parts- tag (most MSB), index, block
offset(mostLSB)inorder to do thecachemapping.

 Selectsetusingindex,block fromsetusingtag.
 Selectlocationfromblockusingblockoffset.

DLCOA /CSL 302/ Sem- III Page37

  tag+index=blockaddress.

 IfamissoccurCPUbringtheblockfromthemainmemorytothecache,ifthereis no free
block in the corresponding set it replaces a block and put the new one.CPU uses
different replacement policies to decide which block is to replace.
Thedisadvantage of the direct mapped cache is that it is easy to build, but suffer
themostfromthrashingdue tothe'conflictmisses'givingmoremiss penalty.

PROCEDURE:
To perform the experiment for Direct mapped cache, use the existing component 'DirectMapped
Cache' component in the 'other components' drawer in the simulator. Thissimulator supports 5-
valued logic. Below is a schematic diagram of the 'Direct
MappedCache'componentinthe'othercomponents'drawer inthesimulator:

DLCOA /CSL 302/ Sem- III Page37

 1. Click on the 'Direct Mapped Cache' component (in the 'other components' drawerin
the pallet) and then click on the position of the editor window where you want
toaddthecomponent(nodraganddrop,simpleclickwillservethepurpose),likewiseadd15B
itswitchesand3BitDisplays(fromDisplayandInputdrawerofthepallet,ifit is not seen
scrolldowninthedrawer)
2. 'DirectMappedCache'componentinthe'othercomponents'drawerinthesimulatorsupport
sbothwritinginthecacheandthecachemapping.Noreplacementpolicyhasbeenimplemen
ted.Initiallythecacheisempty,userhas
togiveinputs.thecomponentcontains4sets,eachsethas5bits,theleftmostbitis the valid
bit, next 2 bits are tags, next bits are data bits, also it contains a one-dimensional
array of memory with 4 bit to store the memory address, user has togive this address
input also. The cache reads all the data bits at a time so blockoffsetisnot required.
3. The pin configuration of the component can be seen whenever the mouse ishovered
on any canned component of the palette or press the 'show pinconfig'button. Pin
numbering starts from 1 and from the bottom left corner (indicatingwith thecircle) and
increasesanticlockwise.
4. Fora'DirectMappedCache'componentpinconfigurationis:
 pin-32= S (selects whether user wants to perform cache write or
cachemapping)
 pin-31= R/W'A (selects whether user wants to input the address or
cachemapping)
 pin-30=A3, pin-29=A2, pin-28=A1, pin-27=A0 (these 4 pins are used
togiveaddress input). A3 is the most significant bit and A0 is the least
significantbit. A3 and A2 will be compared with the tag. A1 and A0 will select
thecorresponding set.
 pin-26= R/W’D (selects whether user wants to input in the set of cache
orcachemapping)
 pin-25= M1, pin-24=M0 (M1 is the most significant bit and M0 is the
leastsignificantbit).thesetwobitsareusedforcachewritepurpose,itselectstheparti
cular set of which user wants to give inputs to the valid bit, tag bits
anddatabits.

DLCOA /CSL 302/ Sem- III Page37

  pin-23= Den (this is an enable input which has to set for any write
purposeinthecache).
 pin-21=validbit
 pin-20=T1,pin-
19=T0(T1isthemostsignificantbitandT0istheleastsignificantbit).Theseare tag bits.
 pin-18=D1,pin-
17=D0(D1isthemostsignificantbitandD0istheleastsignificantbit).Theseare data bits.
 pin-14=Hit/Missbit(if itgives1thenhitotherwise miss)
 pin-15= F1, pin-16=F0 (F1 is the most significant bit and F0 is the
leastsignificantbit).Theseareoutputdatabitsandwillbegivenonlywhenthereisa hit.
5. Essentialpinconfigurationsforwritinginthecache:S=1,R/W'A=0,R/W'D=0,Den=1
6. Essential pin configurations for cache mapping: S=0, R/W'A=1, R/W'D=1,Den=0
7. Toconnectanytwocomponents,selecttheConnectionmenuofPalette,andthenclickontheSourcete
rminalandclickonthetargetterminal.Accordingtothecircuitdiagramconnectallthecomponents.Af
tertheconnectionisoverclicktheselectiontool inthepallet.
8. Seetheoutput,Bitswitchesareusedtogiveinputsothatyoucantoggleitsvalue with adouble click

and see the outputs with different inputs.

OUTPUT:

CONCLUSION:A Direct Mapped Cache has been designed and simulated.

DLCOA /CSL 302/ Sem- III Page37