Lattice Radiant Software 2023.

2
User Guide

November 24, 2023

 Copyright
Copyright © 2023 Lattice Semiconductor Corporation. All rights reserved. This
document may not, in whole or part, be reproduced, modified, distributed, or publicly
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Lattice Radiant Software 2023.2 User Guide 2

 Type Conventions Used in This Document
Convention Meaning or Use

Bold Items in the user interface that you select or click. Text that you type
into the user interface.

<Italic> Variables in commands, code syntax, and path names.

Ctrl+L Press the two keys at the same time.

Courier Code examples. Messages, reports, and prompts from the software.

... Omitted material in a line of code.

. Omitted lines in code and report examples.

.
.

[ ] Optional items in syntax descriptions. In bus specifications, the

brackets are required.

( ) Grouped items in syntax descriptions.

{ } Repeatable items in syntax descriptions.

| A choice between items in syntax descriptions.

Lattice Radiant Software 2023.2 User Guide 3

 Contents

Chapter 1 Introduction 9
Radiant Software Overview 9
User Guide Organization 10

Chapter 2 Getting Started 11

Prerequisites 11
Creating a New Project 11
Opening an Existing Project 15
Importing a Lattice Diamond Project 16
Next Steps 16

Chapter 3 Design Environment Fundamentals 17

Overview 17
Project-Based Environment 18
Process Flow 19
Shared Memory 20
Context-Sensitive Data Views 21

Chapter 4 User Interface Operation 23

Start Page 23
Menus and Toolbars 24
Reports and Messages Views 24
File List Views 25
Tool View Area 25
Output and Tcl Console 26
Basic UI Controls 27
File List 27
Using Revision Control for Radiant Projects 28
Source Template 33

Lattice Radiant Software 2023.2 User Guide 4

 CONTENTS

IP Catalog 34
Process 35
Task Detail View 36
Hierarchy 36
Reports 37
Tool Views 38
Tcl Console 39
Output 39
Message 40
Find Results 40
Common Tasks 41
Controlling Views 41
Cross-Probing 42

Chapter 5 Working with Projects 46

Overview 46
Implementations 48
Adding Implementations 48
Cloning Implementations 49
Input Files 50
Pre-Synthesis Constraint Files 51
Post-Synthesis Constraint Files 51
Debug Files 52
Script Files 52
Analysis Files 53
Programming Files 53
Strategies 53
Area 55
Timing 56
User-Defined 56
Constraint Propagation Options 56
Synplify Pro Options 57
LSE Options 63
Post-Synthesis Options 70
Post-Synthesis Timing Analysis Options 71
Map Design Options 72
Map Timing Analysis Options 73
Place & Route Design Options 74
Place & Route Timing Analysis Options 77
IO Timing Analysis Options 78
Timing Simulation Options 78
Bitstream Options 80
Common Tasks 82
Creating a Project 82
Changing the Target Device 82
Setting the Top Level of the Design 82
Editing Files 83
Saving Project Data 83

Lattice Radiant Software 2023.2 User Guide 5

 CONTENTS

Chapter 6 Radiant Software Design Flow 84

Overview 84
Design Flow Processes 85
Running Processes 85
IP Encryption Flow 86
HDL File Encryption Flow 88
HDL File Encryption Steps 89
Block-Based Design - Using Macro Blocks 92
Creating a Macro Block 94
Creating a Macro Region 97
Exporting Macro 100
Reusing a Macro Block 103
Macro Usage Guidelines 106
Implementation Flow and Tasks 107
Synthesis Constraint Creation 108
Constraint Creation 109
Simulation Flow 111
Simulation Wizard Flow 111

Chapter 7 Working with Tools and Views 116

Overview 116
View Menu Highlights 116
Start Page 117
Reports 117
Tools 118
Timing Constraint Editor 119
Unified Constraints Flow 120
Constraint Propagation 121
Device Constraint Editor 121
Specifying Virtual I/O Ports 135
Checking the Virtual I/O Ports 137
Verifying Virtual I/O Ports 138
Netlist Analyzer 139
Physical Designer 140
Timing Analyzer 142
Using Standalone Timing Analyzer 143
Reveal Inserter 146
Configuring User Memory Setup 147
Configuring User Control Register Setup 149
Configuring User Status Register Setup 150
Reveal Analyzer 151
Reveal Controller 156
Power Calculator 157
ECO Editor 158
Programmer 159
Run Manager 159
Synplify Pro for Lattice 160
Mentor ModelSim 160
Simulation Wizard 160
Source Template 161
IP Catalog 161

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 CONTENTS

IP Packager 162
SEI Editor 163
Common Tasks 164
Controlling Tool Views 164
Using Zoom Controls 166
Displaying Tool Tips 167
Setting Display Options 167

Chapter 8 Command Line Reference Guide 168

Command Line Program Overview 168
Command Line Basics 170
Command Line Data Flow 170
Command Line General Guidelines 171
Command Line Syntax Conventions 172
Setting Up the Environment to Run Command Line 173
Invoking Core Tool Command Line Programs 174
Invoking Core Tool Command Line Tool Help 175
Command Line Tool Usage 175
Running cmpl_libs.tcl from the Command Line 176
Running HDL Encryption from the Command Line 178
Running Synthesis from the Command Line 186
Running Postsyn from the Command Line 193
Running MAP from the Command Line 194
Running PAR from the Command Line 196
Running Timing from the Command Line 202
Running Backannotation from the Command Line 205
Running Bit Generation from the Command Line 207
Running Programmer from the Command Line 211
Running the Deployment Tool from the Command Line 215
Running Various Utilities from the Command Line 242
Using Command Files 247
Using Command Line Shell Scripts 249

Chapter 9 Tcl Command Reference Guide 252

Launching the Tcl Console 254
Running Radiant Tcl 255
Log and Tcl Files 256
Lattice Implementation Directory 257
Attributes 257
Understanding Design Flows 257
Using Implementation Strategies and Options 258
Running Project Flow 260
Running Non-Project Flow 260
Switching From Project Flow to Non-Project Flow 260
Running Milestone Results in Non-Project Flow 261
Opening GUI in Non-Project Flow 262
Design Flow Examples 262
Accessing Command Help and Command Options in the Tcl Console 267
Changes in the Interface 267
Creating and Running Custom Tcl Scripts 268
Running Tcl Scripts When Launching the Radiant Software 271

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 CONTENTS

Radiant Software Tool Tcl Command Syntax 272

Radiant Software Tcl Console Commands 273
Radiant Software Timing Constraints Tcl Commands 275
Radiant Software Physical Constraints Tcl Commands 279
Technology Mapping Tcl Commands 283
Synthesis Tcl Command 284
Design Object Tcl Commands 284
System Tcl Commands 290
Radiant Software Project Tcl Commands 291
Design Tcl Commands 304
Device Tcl Commands 307
Place & Route Tcl Commands 309
Timing Analysis Tcl Commands 310
Simulation Libraries Compilation Tcl Commands 314
Reveal Inserter Tcl Commands 317
Reveal Analyzer Tcl Commands 325
Power Calculator Tcl Commands 334
Programmer Tcl Commands 339
Engineering Change Order Tcl Commands 339
IP Version Update Tcl Commands 341
Message Control Tcl Commands 342
Placement Tcl Commands 344
Routing Tcl Commands 346
Bitstream Generation Tcl Commands 347

Chapter 10 Advanced Topics 349

Shared Memory Environment 349
Clear Tool Memory 349
Environment and Tool Options 350
Batch Tool Operation 351
Tcl Scripts 351
Creating Tcl Scripts from Command History 351
Creating Tcl Scripts from Scratch 352
Sample Tcl Script 352
Running Tcl Scripts 353
Project Archiving 353
File Descriptions 354

Revision History 357

Lattice Radiant Software 2023.2 User Guide 8

 INTRODUCTION : Radiant Software Overview

Chapter 1

Introduction

Lattice Radiant® software is the leading-edge software design environment

for cost- sensitive, low-power Lattice Field Programmable Gate Arrays
(FPGA) architectures. The Radiant software integrated tool environment
provides a modern, comprehensive user interface for controlling the Lattice
Semiconductor FPGA implementation process. Its combination of new and
enhanced features allows users to complete designs faster, more easily, and
with better results than ever before.
This user guide describes the main features, usage, and key concepts of the
Radiant software design environment. It should be used in conjunction with
the Release Notes and reference documentation included with the product
software. The Release Notes document is also available on the Lattice Web
site and provides a list of supported devices.

Radiant Software Overview

The Radiant software uses an expanded project-based design flow and
integrated tool views so that design alternatives and what-if scenarios can
easily be created and analyzed. The Implementations and Strategies
concepts provide a convenient way for users to try alternate design structures
and manage multiple tool settings.

System-level information—including process flow, hierarchy, and file lists—is

available, along with integrated HDL code checking and consolidated
reporting features.

A fast Timing Analysis loop and Programmer provide capabilities in the

integrated framework. The cross-probing feature and the shared memory
architecture ensure fast performance and better memory utilization.

The Radiant software is highly customizable and provides Tcl scripting

capabilities from either its built-in console or from an external shell.

The Radiant software has many of the same features as Lattice Diamond
software, and adds new features, such as:
 Constraints support utilizing industry standard SDC format.
 Efficient, easy-to-use integrated graphical user interface (GUI) with a new
look-and-feel that gives users more efficient access to popular tools.

Lattice Radiant Software 2023.2 User Guide 9

 INTRODUCTION : User Guide Organization

 Unified timing analysis engine with enhanced timing reports for faster
design timing closure.

User Guide Organization

This user guide contains all the basic information for using the Radiant
software. It is organized in a logical sequence from introductory material,
through operational descriptions, to advanced topics.

Key concepts and work flows are explained in “Design Environment

Fundamentals” on page 17 and “Radiant Software Design Flow” on page 84.

Basic operation of the design environment is described in “User Interface

Operation” on page 23.

The chapter “Working with Projects” on page 46 shows how to set up project
implementations and strategies.

The chapter “Working with Tools and Views” on page 116 describes the many
tool views available.

Lattice Radiant Software 2023.2 User Guide 10

 GETTING STARTED : Prerequisites

Chapter 2

Getting Started

This chapter explains how to run the Radiant software and open or create a
project. For more information about project fundamentals, see the chapters
“Design Environment Fundamentals” on page 17 and “Working with Projects”
on page 46.

Prerequisites
To run the Radiant software, select Radiant Software from the installation
location. This opens the default Start Page, shown in Figure 1.

Figure 1: Default Start Page

Creating a New Project

A project is a collection of all files necessary to create and download your
design to the selected device. The New Project wizard guides you through the
steps of specifying a project name and location, selecting a target device, and
adding existing sources to the new project.

Note
Do not place more than one project in the same directory.

Lattice Radiant Software 2023.2 User Guide 11

 GETTING STARTED : Creating a New Project

To create a new project:

1. From the Radiant main window, click the New Project button, or
choose File > New > Project.
The New Project confirmation window opens, shown in Figure 2.

Figure 2: New Project Confirmation Window

2. Click Next. The New Project wizard opens, shown in Figure 3.

Figure 3: New Project Wizard

3. In the Project Name dialog box, do the following:

 Under Project, specify the name for the new project.

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 GETTING STARTED : Creating a New Project

File names for Radiant software projects and project source files must
start with a letter (A-Z, a-z) and must contain only alphanumeric
characters (A-Z, a-z, 0-9) and underscores (_). Spaces are allowed.
 To specify a location for your project, click Browse. In the Project
Location dialog box, you can specify a desired location.
 Under Implementation, specify the name for the first version of the
project. You can have more than one version, or “implementation,” of
the project to experiment with. For more information on
implementations, refer to “Implementations” on page 48.
 To create a sub-directory with the same name as your location
directory, click Create Subdirectory. This will allow you to keep your
project implementations separate. If this box is left unchecked, no sub-
directory will be created in the project directory.
 When you finish, click Next.
4. In the Add Source dialog box, do the following if you have an existing
source file that you want to add to the project. If there are no existing
source files, click Next.
a. Click Add Source. You can import HDL files at this time. In the Import
File dialog box, browse for the source file you want to add, select it,
and click Open.
The source file is then displayed in the Source files field.
b. Repeat the above to add more files.
c. To copy the added source files to the implementation directory, select
Copy source to implementation directory. If you prefer to reference
these files, clear this option.
d. To create empty Lattice Design Constraint (.ldc) file and Physical
Constraint File (.pdc) files that can be edited at a later time, select
Create empty constraint files. Refer to the chapter
“Implementations” on page 48 for more information about constraint
files.
e. When you finish, click Next.
5. In the Select Device dialog box, shown in Figure 4, select a device family
and a specific device within that family. Then choose the options you want
for that device. When you finish, click Next.

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 GETTING STARTED : Creating a New Project

Figure 4: Select Device Dialog Box

6. In the Select Synthesis Tool dialog box, select the synthesis tool that you
want to use. This choice can be changed at any time. When you finish,
click Next.
7. In the Project Information dialog box, make sure the project settings are
correct.

Note
If you want to change some of the settings, click Back to modify them in the
previous dialog boxes of the New Project Wizard.

Click Finish. The newly created project, shown in Figure 5, is now created
and open.

Lattice Radiant Software 2023.2 User Guide 14

 GETTING STARTED : Opening an Existing Project

Figure 5: Opened Project

Select the File List tab under the left pane, to view the Test project file list.

To close a project, choose File > Close Project.

Opening an Existing Project

Use one of the following methods to open an existing Radiant software
project:
 On the Start Page, click the Open Project button.
 From the File menu, choose Open > Project.
 On the Start Page, select the desired project from the Recent Projects
List. Alternatively, choose a recent project from the File > Recent
Projects menu.

You can use the Options dialog box to increase the number of projects that
are shown in the Recent Projects list and to automatically load the previous
project at startup. Choose Tools > Options to open the dialog box. To
increase the number of recent projects listed, click the General tab and enter
a number for “Maximum items shown in Recent Project List” (up to 32). To
automatically open the previous project during startup, click the Startup tab
and then choose Open Previous Project from the “At Lattice Radiant
Software startup” menu.

Figure 6: Recent Project List

Lattice Radiant Software 2023.2 User Guide 15

 GETTING STARTED : Importing a Lattice Diamond Project

Importing a Lattice Diamond Project

To import a Lattice Diamond project into the Radiant software, choose File >
Open > Import Diamond Project.

Figure 7: Import Lattice Diamond Project

The file browser applies an *.ldf file filter to help you find Lattice Diamond
project files. The Lattice Diamond project is converted to a Radiant project.

For more information about importing Lattice Diamond projects into the
Radiant software, refer to the Lattice Radiant Software Guide for Diamond
Users.

Next Steps
After you have a project opened in the Radiant software, you can go
sequentially through the rest of this user guide to learn how to work with the
entire design environment, or you can go directly to any topic of interest.
 The chapters “Design Environment Fundamentals” on page 17 and
“Radiant Software Design Flow” on page 84 provide explanations of key
concepts.
 “User Interface Operation” on page 23 provides descriptions of the
functions and controls that are available in the Radiant software
environment.
 The chapters “Working with Projects” on page 46 and “Working with Tools
and Views” on page 116 explain how to run processes and use the design
tools.
 Reference Guides > Tcl Command Reference Guide in the Radiant
Help provides an introduction to the scripting capabilities available, plus
command-line shell examples.
 “Advanced Topics” on page 349 provides further details about
environment options, shared memory, and Tcl scripting.

Lattice Radiant Software 2023.2 User Guide 16

 DESIGN ENVIRONMENT FUNDAMENTALS : Overview

Chapter 3

Design Environment
Fundamentals

This chapter provides background and discussion on the technology and

methodology underlying the Radiant software design environment. Important
key concepts and terminology are defined.

Overview
Understanding some of the fundamental concepts behind the Radiant
software framework technology will increase your proficiency with the tool and
allow you to quickly come up to speed on its use.

The Radiant software is a next-generation software design environment that

uses a new project-based methodology. A single project can contain multiple
implementations and strategies to provide easily managed alternate design
structures and tool settings.

The process flow is managed at a system level with run management controls
and reporting. Context-sensitive views ensure that you only see the data that
is available for the current state in the process flow.

The shared memory technology enables many of the advanced functions in

the Radiant software. Easy cross-probing between tool views and faster
process loops are among the benefits.

Note
By loading the Radiant software multiple times, you can run different Radiant projects
simultaneously. However, you must not load the same project in more than one
Radiant software instance, as software conflicts can occur.
The Radiant software can also be run remotely. Refer to the Lattice Radiant Software
Installation Guide for Windows or Lattice Radiant Software Installation Guide for Linux
for more information.

Lattice Radiant Software 2023.2 User Guide 17

 DESIGN ENVIRONMENT FUNDAMENTALS : Project-Based Environment

Project-Based Environment
A project in the Radiant software consists of the following file types:
 HDL source files
 Constraint files
 Reveal debug files
 Script files for simulation
 Analysis files for power calculation and timing analysis
 Programming files

The Radiant software also includes settings for the targeted device and the
different tools. The project data is organized into implementations, which
define the project structural elements, and strategies, which are collections of
tool settings.

The following File List shows the items in a sample project.

Figure 8: File List

Each item that is displayed in bold means that it has been selected as the
active item for an implementation. An implementation displayed in bold
means that it has been selected as the currently active implementation for the
project. Your project must have one active implementation, and the
implementation must have one active strategy. Optional items, such as
Reveal hardware debugger files, can be set as active or inactive.

The project is the top-level organizational element in the Radiant software,

and it can contain multiple implementations and multiple strategies. This
enables you to try different design approaches within the same project. If you
want to have a Verilog version of your design, for example, make an
implementation that consists of only the Verilog source files. If you want
another version of the design with primarily Verilog files but a Structural
Verilog (.vm) netlist for one module, create a new implementation using the
Verilog and .vm source files. Each implementation can have Verilog, VHDL or
Structural Verilog source or mixed of them. The same project and design is
used, but with a different set of modular blocks.

Similarly, if you want to try different implementation tool options, you can
create a new strategy with the new option values.

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 DESIGN ENVIRONMENT FUNDAMENTALS : Process Flow

You manage these multiple implementations and strategies for your project by
setting them as active. There can only be a single active implementation with
its one active strategy at a time.

Process Flow
A process is a specific task in the overall processing of a source or project.
Typical processing tasks include synthesizing, mapping, placing, and routing.
You can view the available processes for a design in the Process Toolbar.

Figure 9: Process Toolbar

Click the Task Detail View to see detailed information of the processes.

Processes are grouped into categories according to their functions.

 Synthesize Design
Click on this process and Lattice Synthesis Engine (LSE) runs to
synthesize the design. By default, this process runs the LSE tool.
If you are using Synplify Pro, choose Synplify Pro as the synthesis tool
(Project > Active Implementation > Select Synthesis Tool).
 Post-Synthesis Timing Analysis
Runs timing analysis after the Synthesize Design process.
 Post-Synthesis Simulation File
Generates a netlist file <file_name>_syn.vo used for functional
verification.
 Map Design
This process maps a design to an FPGA. Map Design is the process of
converting a design represented as a network of device-independent
components (such as gates and flip-flops) into a network of device-
specific components (for example, configurable logic blocks).
 Map Timing Analysis
Runs timing analysis after the Map Design process.
 Place & Route Design
After a design has undergone the necessary translation to bring it into the
Unified Database (.udb) format, you can run the Place & Route Design
process. This process takes a mapped physical design .udb file, places
and routes the design, and then outputs a file that can then be processed
by the design implementation tools.

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 DESIGN ENVIRONMENT FUNDAMENTALS : Shared Memory

 Place & Route Timing Analysis

Runs timing analysis after Place & Route process.
 I/O Timing Analysis
Runs I/O timing analysis that allows you to view the path delay tables
and Timing Analyzer report of your timing constraints after placement
and routing.
 Export Files
You can check the desired file you want to export and run this process.
 Bitstream File
This process takes a fully routed physical design as input and
produces a configuration bitstream (bit images). The bitstream file
contains all of the configuration information from the physical design
defining the internal logic and interconnections of the FPGA, as well
as device-specific information from other files associated with the
target device.
 IBIS Model
This process generates a design-specific IBIS (I/O Buffer Information
Specification) model file (<project_name>.ibs).
IBIS models provide a standardized way of representing the electrical
characteristics of a digital IC’s pins (input, output, and I/O buffers).
 Gate-Level Simulation File
This process backannotates the routed design with timing information
so that you may run a simulation of your design. The backannotated
design is a Verilog netlist.
The Reports view allows you to examine and print process reports.
Messages are displayed in the Messages window at the bottom of the
Radiant software main window.

The process status icons are defined as follows:

Process in initial state (not processed)

Process completed successfully

Process completed with unprocessed subtasks

Process failed

Shared Memory
The Radiant software uses a shared memory architecture. All tool and data
views look at the same design data at any point in time. This means that when
you change a data element in one view of your design, all other views will see
the change, whether they are active or not.

Lattice Radiant Software 2023.2 User Guide 20

 DESIGN ENVIRONMENT FUNDAMENTALS : Context-Sensitive Data Views

When project data has been changed but not yet saved, an asterisk (*) is
displayed in the title tab of the view.

Figure 10: Title Tab with Changed Content Indication

Notice that the asterisks indicating changed data will appear in all views
referencing the changed data.

If a tool view becomes unavailable, the Radiant software environment will

need to be closed and restarted.

Context-Sensitive Data Views

The data in shared memory reflects the state or context of the overall process
flow. This means that views such as Device Constraint Editor Spreadsheet
View will display only the data that is currently available, depending on
process steps that have been completed.

For example, Figure 11 shows the Process flow before Synthesis. Therefore,
Spreadsheet View shows no IO Type or PULLMODE.

Figure 11: Process Completed Before Synthesis

After Synthesis has been completed, Spreadsheet View displays IO Type and
PULLMODE assignments, as shown in Figure 12.

Lattice Radiant Software 2023.2 User Guide 21

 DESIGN ENVIRONMENT FUNDAMENTALS : Context-Sensitive Data Views

Figure 12: Process Completed Through Synthesis

When you see the “Loading Data” message displayed in Figure 13, it means
that a process has been completed and that the shared memory is being
updated with new data.

Figure 13: Loading Data

All tool views are dynamically updated when new data becomes available.
This means that when you rerun an earlier process while a view is open and
displaying data, the view will remain open but dimmed because its data is no
longer available.

Lattice Radiant Software 2023.2 User Guide 22

 USER INTERFACE OPERATION : Start Page

Chapter 4

User Interface Operation

The Radiant user interface (UI) provides a comprehensive, integrated tool

environment. The UI is very flexible and configurable, enabling you to store
constraints for the layout you choose.

This chapter describes the user interface, controls, and basic operation of the
Radiant software. Each major element of the interface is explained. The last
section in the chapter describes common user interface tasks.

Start Page
The Start Page contains three major sections, as shown in Figure 14.

Figure 14: Default Start Page

 Project: This section allows you to create a new project; open an existing
Project, and open an example.
 Information Center: This section has links to Getting Started, Tutorials,
User Guides, and Support Center.
 Recent Project List: Provides a quick way to load a recent project you’ve
been working on.

The Start Page appears in the View area by default when the Radiant
software is first launched, and can be opened from the View tab on the menu.

Lattice Radiant Software 2023.2 User Guide 23

 USER INTERFACE OPERATION : Start Page

The Start Page can be closed, opened, detached, and attached using the
Attach button. See “Basic UI Controls” on page 27.

Menus and Toolbars

At the top of the main window is the menu and toolbar area. High-level
controls for accessing tools, managing files and projects, and controlling the
layout are contained here. All toolbar functionality is also contained in the
menus. The menus also have functions for system, project and toolbar
control.

The Process Toolbar lists all the processes available, such as Synthesize
Design, Map Design, Place & Route Design, and Export Files. A process is a
specific task in the overall processing of a source or project. You can view the
available processes for a design in the Process Toolbar. Click Task Detail
View to see detailed information of the processes available.

Reports and Messages Views

The Reports view allows you to examine and print process reports. There are
two panes in the Reports view. The left pane lists the reports. The right pane
displays the reports.

Log messages are displayed in the Output frame of the Radiant software
main window.

Figure 15: Reports and Log Message Views

Reports View

Log Messages

Lattice Radiant Software 2023.2 User Guide 24

 USER INTERFACE OPERATION : Start Page

File List Views

In the middle of the main window on the left side is the File List area. This is
where the overall project and process flow is displayed and controlled.

Figure 16: File List Area

File List

Hierarchy View

Tabs at the bottom of the File List area allow you to select between the
following views:
 File List – shows the files in the project organized by implementations and
strategies. This is not a hierarchical listing of the design.
 Source Template – provides templates for creating VHDL, Verilog, and
Constraint files.
 IP Catalog – lists available modules/intellectual properties (IP).

Underneath the File List is the Hierarchy View area. It allows you to view the
hierarchical design representation. Hierarchy view shares the left pane with
File List view.

Tool View Area

In the middle of the main window on the right side is the Tool View area. This
is where the Start Page, Reports View, and all the Tool views are displayed.

Lattice Radiant Software 2023.2 User Guide 25

 USER INTERFACE OPERATION : Start Page

Figure 17: Tool View Area

Tool View

Multiple tools can be displayed at the same time. The tool tabs include
controls for grouping the tool views as well as integrating all tool views back
into the main window.

Each tool view is specific to its tool and can contain additional toolbars and
multiple panes or windows controlled by additional tabs. The chapter
“Working with Tools and Views” on page 116 provides more details about
each tool and view.

Figure 18: Multiple Tools

Output and Tcl Console

Near the right bottom of the main window is the Tcl Console, Output, and
Message area.

Lattice Radiant Software 2023.2 User Guide 26

 USER INTERFACE OPERATION : File List

Tabs at the bottom of this area allow you to select between Tcl Console,
Output, and Message. Tool output is automatically displayed in the Output
tab, and Errors and Warnings in the Message tab.

Figure 19: Output and Tcl Console Area

Basic UI Controls
The Radiant software environment is based on modern industry standard
user interface concepts. The menus, toolbars, and mouse pointer all behave
in familiar ways. You can resize any of the window panes, drag and drop
elements, right-click a design element to see available actions, and hold the
mouse pointer over an object to view the tool tip. Window panes can also be
detached from the main window and operated as independent windows.

File List
The File List is a project view that shows the files in the project, including
implementations and strategies. It is not a hierarchical listing of the design,
but rather a list of all the design source, configuration and control files that
make up the project.

Figure 20: File List

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At the top of the File List is the project name. Directly below the project name
is the target device, followed by the strategies, and then the implementations.
There must be one active implementation, and it must have one active
strategy. Active elements are indicated in bold.

You can right-click any file or item in the File List to access a pop-up menu of
currently available actions for that item. The pop-up menu contents vary,
depending on the type of item selected.

The File List view can be hidden by clicking the small arrow in right border:
“Click to show/hide side panel.”

Using Revision Control for Radiant

Projects
Radiant supports revision control for your projects. When changes are logged
into the revision control system, you can get all the change logs and switch to
previous milestones if necessary. Compile times can be reduced when using
revision control with Radiant design. The compilation will only start when
inputs are changed.

Recommended Revision Control System

Radiant recommends the following revision control systems:
 GIT
 SVN
 Perforce

Radiant Revision Control Strategies

You can select different revision control systems to work with Radiant, the
software does not directly integrate a specific revision control into the system.
Radiant recommends two strategies:
 Minimum Files Strategy (Radiant Recommendation) – The revision
control system only manages the necessary files of the project. Other files
– including some intermediate and configuration files, are only used in
your project and will not be submitted to the version management system.
The following files are recommended to commit to revision control
systems:
 .rdf project file and .sty strategy file
 All source files under source directory
 All files under ip_directory
 Complete Strategy – You can also add some intermediate files on the
project to the revision control system.

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For this strategy, the files under implementation can be committed to the
revision control system. You can select files to submit to the system under
each implementation, which mainly includes intermediate and analysis
files.

It is recommended to use the following strategy directory structure to manage

source code and designs:
 Radiant design can use one source directory to put all source or design
files. The software can automatically identify various types of files and
display them in categories in the File List View.

 Use a source directory to place all source and design files for every
implementation. Under the source folder, each implementation has its own
file directory (e.g. impl_1, impl_2).

 Create an IP directory (e.g. ip_designs) under the source directory of the

project to store all IP designs of Radiant. Each IP design has a

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subdirectory under the source directory to store IP source code and

design files.

 Use one implementation directory (e.g. impl_1, impl_2) to compile the

relative implementation of the project. All intermediate files will be
generated under this folder (.udb, status, report, and other intermediate
type files are all here).

Radiant File Types

The Radiant project directory contains the following file types:
 .rdf file – Radiant project file
 .sty file – Radiant strategy file

Common source or design file types under the source directory:

 .v file – Verilog file
 .vhdl file – VHDL file
 .sv file – System Verilog file

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 .ldc file – LSE Design Constraints file

 .pdc file – Post-Synthesis Constraint file
 .pcf file – Power Calculator file
 .sdc file – Pre-Synthesis Constraint file
 .rvl file – Reveal Project file
 .rva file – Reveal Analyzer file
 .vm file – Structural Verilog file
 .fdc file – Synplify Pro Constraint file
 IP_ folder – One IP instance file under the folder

Other intermedia file types:

 .ini file – Initialization file
 .log file – Log file
 .build_status file – Status file
 .xml file – XML configuration file
 .html file – HTML file
 .ibs file – Input/Output Buffer Information Specification file
 .udb file – User design Database file
 .bit file – Bitstream
 synthesis.log – LSE synthesis report
 .mrp – Radiant map report
 .twr – Radiant timing report

Note:
Intermedia files might be re-generated if you rerun the flow.

Radiant Revision Control Workflow

The following diagrams show the revision control workflow of Radiant.

Revision Control Normal Workflow

You can get the latest code from the radiant version server and develop in
your own environment and working directory. Later on, you can submit the
modified code or new design to the radiant version server as needed.

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Multiple developers working on the same file

You may have your code changes and modify the same source file or design.
For example, if you submit a file and another user updates it, you will get an
error. At this time, you need to update the latest code locally from the server,
integrate it with your modifications, and submit it again. This is the
collaborative operation of multiple users for the revision control system.

Multiple developers adding files

If you add a new a.v file in the design, and submit this file and the Radiant
project file to the revision control server, another user can do the following:
 Get the latest code from the server

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 Merge the local code

 Resolve the conflict
 Continue the subsequent development

Source Template
The Source Template is a project view that provides templates for creating
VHDL, Verilog, and constraint files. Templates increase the speed and
accuracy of design entry. You can drag and drop a template directly to the
source file. You can also create your own templates.

To access templates, choose View > Show Views > Source Template, or
click icon in the toolbar, or click on the Source Template tab in the bottom-
left pane, to locate and access the following templates:
 Verilog, including common and Parameterized Module Instantiation (PMI),
Primitives, Attributes, Encryption, and User Templates
 VHDL, including common, PMI, Primitives, Attributes, Encryption, and
User Templates
 Constraints for LSE, including Timing and Physical constraints and User
Templates

Note
For more information on PMI, refer to the Radiant Software Help. See User Guides >
Entering the Design > Designing with Soft IP, Modules, and PMI > PMI or IP
Catalog?

You can simply drag any template and drop it into your source file.

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Figure 21: Source Template

IP Catalog
IP Catalog enables you to customize a collection of functional blocks from
Lattice Semiconductor. Through the IP Catalog, you can access two types of
functional blocks, Modules and IP.

To access IP catalog, choose View > Show Views > IP Catalog, or click
icon in the toolbar, or click on the IP Catalog tab in the bottom-left pane.

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Figure 22: IP Catalog

Each module is configurable with a unique set of properties. Once generated,

the module or IP appears in your design’s File List.

Process
A process is a specific task in the overall processing of a source or project.
Typical processing tasks include synthesizing, mapping, placing, and routing.
You can view the available processes for a design in the Process Toolbar.

Figure 23: Process Toolbar

The process status icons are defined as follows:

Process in initial state (not processed)

Process completed successfully

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Process completed with unprocessed subtasks

Process failed

For more detail of different designs and Export Files available, see “Process
Flow” on page 19.

Task Detail View

Click Task Detail View to see detailed information of each process.

The default design flow processes are marked by check marks. To enable the
remaining tasks, either check-mark the specific task and rerun the process
step, or double-click the task’s name. You can also right-click on the task to
show the context menu.

Once the process has finished, the process status icon next to the task
replaces the gray dot.

Figure 24: Task Detail View

Processes are grouped into categories according to their functions. To learn

more about each process, view “Design Flow Processes” on page 85.

Hierarchy
The Hierarchy view is a project view that displays the design hierarchy and is
displayed by default. The hierarchical view is available when File List tab is
selected.

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Figure 25: Hierarchy View

If you would prefer that it not open by default, simply close Hierarchy View.
The next time you launch the Radiant software, the Hierarchy View will not be
opened. You can open it manually by selecting it from the View > Show View
menu.

Right-click any of the objects in the Hierarchy View to see the available
actions.

Figure 26: Hierarchy Item Pop-up Menu

The Hierarchy view can be selected, closed, and opened.

Reports
The Reports View provides a centralized reporting mechanism in the Tools
view area. The Reports View is automatically displayed and updated when
processes are run. It provides a separate tab for the current implementation,
enabling you to compare results quickly.

The right pane displays the report for the selected step. You can also click the
icon in the toolbar.

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Figure 27: Reports View

The Reports pane on the right shows the detail of the project summary and
resource usage.

The Report View can be selected, closed, opened, detached, and attached
with the Attach button. See “Basic UI Controls” on page 27.

Tool Views
The Tool view area of the UI displays the tools that are currently active. Each
tool that you have opened from the toolbar or the Tools menu is displayed.
The Reports and Start page, which can be opened from the toolbar or the
Windows menu, are also displayed. When multiple tools are active, the
display can be controlled with the tab group functions in the Window menu.
See “Common Tasks” on page 41 for more information on tab group
functions.

Each tool view is specific to its tool and can contain additional toolbars,
multiple panes, or multiple windows controlled by additional tabs. See
“Working with Tools and Views” on page 116 for descriptions of each tool and
view, plus details on controlling their display.

The Tool views can be selected, closed, opened, detached, and attached
using the Attach button. See “Basic UI Controls” on page 27

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Figure 28: Tool View Tab Title

Tcl Console
The Tcl Console is an integrated console for Tcl scripting. You can enter Tcl
commands in the console to control all of the functionality of the Radiant
software. Use the Tcl help command (help <tool_name>*) to display a list of
valid extended Tcl commands.

Figure 29: Tcl Console

Output
The Output View is a read-only area where tool output is displayed.

Figure 30: Output View

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Message
There are three message types available:
 Error -- displayed in red.
 Critical -- displayed in orange.
 Warnings -- displayed in yellow.
 General Information -- displayed in blue.
A red dot in the Message tab provides a visual notification
that a new message/warning was received. Once you view
the notification, the dot disappears.

Right-clicking a message provides a menu of commands, including Location

in > Text Editor, which opens the source file in the Source Editor and
highlights the location of the problem.

Figure 31: Message Display

Find Results
The Edit > Find in Files command enables you to search for information in
the files within your project directory. The search results are then displayed in
the Find Results view.

Figure 32: Find Results View

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Common Tasks
The Radiant software UI controls many tools and processes. The following
sections describe some of the more commonly performed tasks.

Controlling Views
All of the views in the Radiant software are controlled in a similar manner,
even though the information they contain varies widely. Here are some of the
most common operations:
 Open – Use the View > Show Views menu selections or right-click in the
menu or toolbar areas to select a view from the pop-up menu.
 Select – If a view is already open you can select its tab to bring it to the
front.
 Detach – Click the detach button in the upper right corner of the view.
 Attach – Click the attach button in the upper right corner of the view.
 Move – Click and hold a view’s tab, and then drag and drop the view to a
different position among the open views.

Using a Tab Group You can use the Window menu to split off a view and
control it as a separate tab group. This allows you to examine two open views
side by side. The controls work as follows:
 Split Tab Group – displays two views side by side. See Figure 33.
 Move to Another Tab Group – moves the selected tab to the other tab
group. See Figure 34.
 Merge Tab Group – merges a split tab group back into the primary view
 Switch Tab Group Position – switches the positions of the two tab groups.

Figure 33: After Split Tab Group Command Used on Physical Designer

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Figure 34: After Move to Another Tab Group Used on Netlist Analyzer

Cross-Probing
It is possible to select a data object in one view and see that same data object
in a different view or views. Right-click an object to see if cross-probing is
available. If it is, you will see a Show In sub-menu with the available views
listed. If you select a view that is not yet open, the Radiant software will open
it automatically. Cross-probing is available between Floorplan View and
Physical View of Physical Designer, and from Netlist Analyzer to Physical
Designer.

Figure 35: Show In Menu from Physical View of Physical Designer

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During the Radiant flow, various timing analyses and reports are created. You
can view a specific path in Netlist Analyzer, Physical Designer’s Floorplan
View, and Physical Designer’s Physical View. This allows for flexibility and
reduced debugging effort.

NOTE
Cross-probing to Netlist Analyzer is available only if the selected synthesis tool is LSE.

In the Reports tab, view any timing analysis report and identify a path to view.
If cross-probing is available, the specific icon tools become visible, as shown
in the following figure.

Figure 36: Available tools for Path Cross-Probing

Click on an icon and the tool opens with the selected path.

In some cases, the tool is unable to find the path. The message “Can’t show
the schematic of this timing path.” appears. In an encrypted design, in some
cases, cross-probing is not available. The message “Cannot open encrypted
design.” appears.

The following figures show cross-probing a path from the Place & Route
Timing Analysis report to Netlist Analyzer, Physical Designer’s Floorplan
View, and Physical Designer’s Physical View.

Figure 37: Path Cross-Probing in Reports

By clicking on the Netlist Analyzer icon, you can preview the data path in
Netlist Analyzer.

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Figure 38: Path Cross-Probing in Netlist Analyzer

Similarly, by clicking on the Floor Planner icon, you can easily view the same
path in Physical Designer’s Placement Mode.

Figure 39: Path Cross-Probing in Physical Designer’s Placement Mode

The same path is viewable in Physical Designer’s Routing Mode by clicking

on the Physical View icon in a timing report.

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Figure 40: Path Cross-Probing in Physical Designer’s Routing Mode

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Chapter 5

Working with Projects

This chapter covers projects and their elements. Implementations and

strategies are explained and some common project tasks are shown.

Overview
A project is the top organizational element in the Radiant software design
environment. Projects consist of design, constraint, configuration and analysis
files. Only one project can be open at a time, and a single project can include
multiple design structures and tool settings.
You can create, open, or import a project from the Start Page. Refer to
“Getting Started” on page 11 for instructions on creating a new project.

Figure 41: Default Start Page

The File List view shows a project and its main elements.

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Figure 42: Project Files in File List

The Project menu commands enable you to do the following:

 Examine the project properties.
 Change the target device.
 Change the severity level of warning messages.
 Set the synthesis tool.
 Show the active strategy tool settings.
 Set the top level design unit.

Figure 43: Project Menu

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Implementations
An implementation is the structure of a design and can be thought of as what
is in the design. For example, one implementation might use inferred memory
while another implementation uses instantiated memory. Implementations
also define the constraint and analysis parameters for a project.

There can be multiple implementations in a project, but only one

implementation can be active at a time. And there must be one active
implementation. Every implementation has an associated active strategy.
Strategies are a shared pool of resources for all implementations and are
discussed in the next section. An implementation is created whenever you
create a new project.

Implementations consist of the following files:

 Input files
 Pre-Synthesis constraint files
 Post-Synthesis constraint files
 Debug files
 Script files
 Analysis files
 Programming files

Adding Implementations
To add a new implementation to an existing project:
1. Right-click the project name in the File List project view.

Select Add > New Implementation. In the New Implementation dialog box,
you can set the implementation name, directory, default strategy, and add
source files. When you select Add Source you have a choice of browsing for
the source files or using a source from an existing implementation.

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Figure 44: New Implementation

Notice that you have the option to “Copy source to implementation directory.”
If this option is selected, the source files will be copied from the existing
implementation to the new implementation, and you will be working with
different source files in the two implementations. If you want the two
implementations to share the same source files and stay in sync, make sure
that this option is not selected.

To make an implementation active, right-click its name in the File List and
choose Set as Active Implementation.

To add a file to an implementation, right-click the implementation name or any

file folder in the implementation and choose Add > New File or Add >
Existing File.

Cloning Implementations
To clone an implementation:
1. In the File List view, right-click on the name of the implementation that you
want to copy and choose Clone Implementation.
The Clone Implementation dialog box opens.
2. In the dialog box, enter a name for the new implementation. This name
also becomes the default name for the folder of the implementation.
3. Change the name of the implementation’s folder in the Directory text box,
if desired.
4. Decide how you want to handle files that are outside of the original
implementation directory. Select one of the following options:
 Continue to use the existing references
The same files will be used by both implementations.

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 Copy files to new implementation source directory

The new implementation will have its own copies that can be changed
without effecting the original implementation.
5. The Synthesis Tool text box specifies the currently selected synthesis tool.
Go to Project > Active Implementation > Select Synthesis Tool to
update your selection.
6. The Default Strategy text box specifies the currently selected default
strategy.
7. Click OK.

Input Files
Input files are the design source files for the project. Input files can be any
combination of Verilog, SystemVerilog, and VHDL.

Right-click an input file name to open a pop-up menu of possible actions for
that file.

Figure 45: Input File Actions

You can use the “Include for” commands to specify that a source file be
included for both synthesis and simulation, synthesis only, or simulation only.

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Pre-Synthesis Constraint Files

Synopsys timing constraints are specified in the new .fdc file format. Legacy
.sdc formats are still supported in the Radiant software and Synopsys has
provided a script called sdc2fdc, which does a one-time conversion of .sdc
files to the new .fdc format. More information about this script can be found in
the Synplify Pro release notes.

An .fdc file can be added to an implementation if the selected synthesis tool is

Synplify Pro. When using Synplify Pro or the Lattice Synthesis Engine (LSE),
the constraints files can be saved as an .sdc file. If the selected synthesis tool
is LSE, a Lattice design constraint (.ldc) synthesis file can be added.
Constraints in the .ldc file use the Synopsys constraint format.

An implementation can have multiple synthesis constraint files. Only one

synthesis constraint file can be active at a time. Unlike Post-Synthesis
constraints, a synthesis constraint file must be set as active by the user.

Post-Synthesis Constraint Files

Post-Synthesis constraint files (.pdc) contain both timing and non-timing
constraint .pdc source files for storing logical timing/physical constraints.
Constraints that are added using the Device Constraint Editor are saved to
the active .pdc file. The active post-synthesis design constraint file is then
used as input for post-synthesis processes.

An implementation can have multiple .pdc files, but only one can be active at
a time.

Figure 46: Sample .pdc File

Figure 47 shows a high-level flow of how constraints from multiple sources

can be used and modified in the Radiant software.

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Figure 47: Radiant software Constraints Flow Chart

Debug Files
The files in the Debug folder are project files for Reveal Inserter. They are
used to insert hardware debug into your design. There can be multiple debug
files, and one can be set as active. To insert hardware debug into your design,
right-click a debug file name and choose Set as Active Debug File from the
pop-up menu. The debug file name becomes bold, indicating that it is active. It
is not required to have an active debug file.

Script Files
The Script Files folder contains the scripts that are generated by the
Simulation Wizard. After you run the Simulation Wizard, the steps are stored
in a simulation project file (.spf), which can be used to control the launching of
the simulator.

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Figure 48: Simulation Script File

Analysis Files
The Analysis Files folder contains Power Calculator files (.pcf). The folder can
contain multiple analysis files, and one (or none) can be set as active. The
active or non-active status of an analysis file affects the behavior of the
associated tool view.

Programming Files
Programming files (.xcf) are configuration scan chain files used by the
Radiant Programmer for programming devices. The .xcf file contains
information about each device, the data files targeted, and the operations to
be performed.

An implementation can have multiple .xcf files, but only one can be active at a
time.The file must be set as active by the user.

Strategies
Strategies are collections of all the implementation-related tool settings in one
convenient location. Strategies can be thought of as recipes for how the
design will be implemented. An implementation defines what is in the design,
and a strategy defines how that design will be run. There can be many
strategies, but only one can be active at a time. There must be one active
strategy for each implementation.

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The Radiant software provides two predefined strategies: Area and Timing. It
also enables you to create customized strategies. Predefined strategies
cannot be edited, but they can be cloned, modified, and saved as customized
user strategies. Customized user strategies can be edited, cloned, and
removed. All strategies are available to all of the implementations, and any
strategy can be set as the active one for an implementation.
To create a new strategy from scratch, choose File > New > Strategy. In the
New Strategy dialog box, enter a name for the new strategy. Specify a file
name for the new strategy and choose a directory to save the strategy file
(.sty).

Figure 49: Creating a New Strategy from Scratch

The new strategy is with all the default settings of the current design. You can
modify its settings in the Strategies dialog box.

If you want to save the strategy changes to your current project, choose File >
Save Project from the Radiant software main window.

To create a new strategy from an existing one, right-click the existing strategy
and choose Clone <strategy name> Strategy. Set the new strategy’s ID and
file name.

Figure 50: Cloning to Create a New Strategy

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To make a strategy active, right-click the strategy name and choose Set as
Active Strategy.

To change the settings in a strategy:

1. Double-click the strategy name in the File List view
2. Select the option type to modify
3. Double-click the Value of the option to be changed

The default values are displayed in plain blue text. Modified values are
displayed in italic bold text.

Strategies are design data independent and can be exported and used in
multiple projects.

Area
The Area strategy is a predefined strategy for area optimization. Its purpose is
to minimize the total logic gates used while enabling the tight packing option
available in Map.
Applying this strategy to large and dense designs might cause difficulties in
the place and route process, such as longer time or incomplete routing.

Figure 51: Area Predefined Strategy

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Timing
The Timing strategy is a predefined strategy for timing optimization. Its
purpose is to achieve timing closure. The Timing strategy uses a very high
effort level in placement and routing. Use this strategy if you are trying to
reach the maximum frequency on your design. If you cannot meet your timing
requirements with this strategy, you can clone it and create a customized
strategy with refined settings for your design. This strategy might increase
your place-and-route run time compared to the Area strategy.

Figure 52: Timing Predefined Strategy

User-Defined
You can define your own customized strategy by cloning and modifying any
existing strategy. You can start from either a predefined or a customized
strategy.

Constraint Propagation Options

This page lists all the strategy options associated with the Constraint
Propagation process.

Propagation Debug Mode

Using Propagation Debug Mode can affect timing of other circuits and can
lead to false timing reports.

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Synplify Pro Options

This page lists all the strategy options associated with the Synplify Pro
Synthesis process. For information on their use in Synplify Pro, see the
Synopsys Synplify Pro for Lattice Reference Manual.

Allow Duplicate Modules (for Synplify Pro)

Allows the use of duplicate modules in your design.

When it is set to True, the last definition of the module is used by the software
and any previous definitions are ignored. The default is False.

Area (for Synplify Pro)

Specifies optimization preference for area reduction over timing delay

reduction.

The True option specifies the area reduction mode. When set to True, this
setting overrides the setting in “Frequency (MHz) (for Synplify Pro)” on
page 60.

The default is False.

This option is equivalent to the “set_option -frequency 1” command in Synplify

Pro.

Arrange VHDL Files

Allows Synplify Pro to reorder the VHDL source files for synthesis.

The default is True for VHDL or VHDL design entry type projects, and False
for other projects. When this is set to False, Synplify Pro will use the file order
in the Radiant software File List view.

Auto Compile Point

With Automatic Compile Points, synthesis decides based on existing

hierarchy and utilization estimates.

Compile Points minimize the amount of netlist changes resulting from RTL
code changes. Compile points create logical boundaries where optimization
will not occur. This may sacrifice some design performance for design result
predictability. No user intervention is needed aside from enabling the flow.

Note:
Auto Compile Point only supports the LAV-AT-E device.

Automatic Read/Write Check Insertion for RAM

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When this option is set in the strategy, the synthesis tool inserts glue logic
around inferred RAM to avoid simulation mismatches caused by
indeterminate output values when the read and write addresses are same. By
default this option is OFF.
Users should design to make sure the read and write addresses are never the
same.

Clock Conversion
Controls gated and generated clock conversion.

Values are True and False.

Command Line Options (for Synplify Pro)

Enables additional command line options for the Synplify Pro Synthesis
process.

To enter a command line option:

1. In the Strategy dialog box, select Synplify Pro in the Process list.
2. Double-click the Value column for the Command line Options option.
3. Type in the option and its value (if any) in the text box.
4. Click Apply.

For example:

set_option -library_path c:/source

Default Enum Encoding

(For VHDL designs) Defines how enumerated data types are implemented.

The type of implementation affects the performance and device utilization.

Available options are:
 Default – Automatically assigns an encoding style based on the number of
states:
 Sequential: 0-4 enumerated types
 Onehot: 5-40 enumerated types
 Gray: more than 40 enumerated types
 Gray – Only one bit of the state register changes at a time, but because
more than one bit can be hot, the value must be decoded to determine the
state. For example: 000, 001, 011, 010, 110
 Onehot – Only two bits of the state register change (one goes to 0; one
goes to 1) and only one of the state registers is hot (driven by a 1) at a
time. For example: 0000, 0001, 0010, 0100, 1000
 Sequential – More than one bit of the state register can change at a time,
but because more than one bit can be hot, the value must be decoded to
determine the state. For example: 000, 001, 010, 011, 100

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This option is equivalent to the “set_option -default_enum_encoding default |

onehot | gray | sequential” command in Synplify Pro.

Disable IO Insertion (for Synplify Pro)

Controls whether the synthesis tool will add I/O buffers into your design.

If this is set to True, Synplify Pro will not add I/O buffers into your design. If it
is set to False (default), the synthesis tool will insert I/O buffers into your
design.

This option is equivalent to the “set_option -disable_io_insertion 1 | 0”

command in Synplify Pro.

Disable Register Replication During S/R Optimization

(Not applicable for iCE40 UltraPlus): When this option is set in the strategy,
the synthesis tool will NOT duplicate the registers while inferring the address
pointers for the RAM during Shift-register inference. By default this option is
OFF and the tool will duplicate the address pointer registers to get better
performance.

Export Radiant Software Settings to Synplify Pro GUI

Controls whether the strategy settings are exported to Synplify Pro during
interactive synthesis (opening Synplify Pro through the Tools menu). After
opening Synplify Pro, you can change settings in Synplify Pro's interface. This
option has no effect with integrated or stand-alone synthesis.

Available options are:

 No – Synplify Pro opens with its own defaults, ignoring the strategy
settings.
 Yes (default) – Synplify Pro opens with the strategy settings every time.
Options set and saved in a previous Synplify Pro session are ignored.
 Only on First Launch – Synplify Pro opens with the strategy settings the
first time only. After that, Synplify Pro opens with settings saved in a
previous session or with its own defaults. After the first time, the strategy
settings are ignored.

For more information, refer to the Radiant Software Help. See User Guides >
Implementing the Design > Synthesizing the Design > Interactive
Synthesis.

FSM Compiler (for Synplify Pro)

Enables or disables the FSM Compiler and controls the use of FSM synthesis
for state machines.

When Synplify Pro is selected as the synthesis tool, it enables or disables the
FSM Compiler and controls the use of FSM synthesis for state machines.
When this is set to True (default), the FSM Compiler automatically recognizes
and optimizes state machines in the design. The FSM Compiler extracts the
state machines as symbolic graphs, and then optimizes them by re-encoding

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the state representations and generating a better logic optimization starting

point for the state machines.

This option is equivalent to the “set_option -symbolic_fsm_compiler 1 | 0”

command in Synplify Pro.

Fanout Guide
Controls fanout during synthesis. When the specified fanout limit is achieved,
logic will be duplicated.

The default is 1000.

This option is equivalent to the “set_option -maxfan <number>” command in

Synplify Pro.

Force GSR (for Synplify Pro)

Forces Global Set/Reset Pin usage.

Available options are:

 False (default) – Does not infer Global Set/Reset in your design.
 Auto – Allows the software to decide whether to infer Global Set/Reset in
your design.
 True – Always infers Global Set/Reset in your design.

This option is equivalent to the “set_option -force_gsr auto | yes | no”

command in Synplify Pro.

Frequency (MHz) (for Synplify Pro)

Specifies the global design frequency (in MHz). Nothing in the Value column
means "auto" and Synplify Pro will try to maximize the frequency of the
clocks.

The setting is ignored when “Area (for Synplify Pro)” on page 57 is set to True.

This option is equivalent to the “set_option -frequency <number> | auto”

command in Synplify Pro.

Library Directories

Specifies all the paths to the directories which contain the Verilog library files
to be included in your design for the project.

You can also add custom library files with module definitions for the design in
a single file. The names of files read from the library path must match module
names. Mismatches result in error messages.

Number of Critical Paths (for Synplify Pro)

Specifies the number of critical timing paths to be reported in the timing report.

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This option is equivalent to the “set_option -num_critical_paths <number>”

command in Synplify Pro.

Number of Start/End Points

Specifies the number of start and end points you want the software to report in
the critical path section of the timing report.

This option is equivalent to the “set_option -num_startend_points <number>”

command in Synplify Pro.

Output Netlist Format (for Synplify Pro)

Outputs a mapped VHDL netlist for post-synthesis simulation.

Available options are: None (default) and VHDL.

This option is equivalent to the “set_option -write_vhdl 1 | 0” command in

Synplify Pro.

Pipelining and Retiming

Enables the pipelining and retiming features to improve design performance.

Values are:
 None – Disables the pipelining and retiming features.
 Pipelining Only (default) – Runs the design at a faster frequency by
moving registers into the multiplier, creating pipeline stages.
 Pipelining and Retiming – When enabled, registers may be moved into
combinational logic to improve performance.

This option is equivalent to the “setup_option -pipe 1 | 0 -retiming 1 | 0”

command in Synplify Pro.

Push Tristates
When this is set to True, the Synplify Pro compiler pushes tristates through
objects such as muxes, registers, latches, buffers, nets, and tristate buffers,
and propagates the high impedance state.

The high-impedance states are not pushed through combinational gates such
as ANDs or ORs.

The default is False.

This option is equivalent to the “set_option -compiler_compatible 1 | 0”

command in Synplify Pro.

Resolve Mixed Drivers (for Synplify Pro)

If a net is driven by a VCC or GND and active drivers, setting this option to
True will connect the net to the VCC or GND driver.

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This option is equivalent to the “set_option -resolve_multiple_driver 1 | 0”

command in Synplify Pro.

Resource Sharing (for Synplify Pro)

When this is set to True (default), the synthesis tool uses resource sharing
techniques to optimize area.

With resource sharing, synthesis uses the same arithmetic operators for
mutually exclusive statements; for example, with the branches of a case
statement. Conversely, you can improve timing by disabling resource sharing,
but at the expense of increased area.

This option is equivalent to the “set_option -resource_sharing 1 | 0” command

in Synplify Pro.

Resynthesize All

When this is set to True (default), Synplify Pro will resynthesize all portions,
modules, or files of the RTL source. When this is set to False, Synplify Pro will
synthesize only the updated portions, modules or files of the RTL source
since the last run result.

If you run the “Force Run From Start' process, all portions, modules, or files of
the RTL source will be resynthesized, regardless of whether this option is set
to True or False.

Update Compile Point Timing Data

Determines whether (True) or not (False) changes inside a compile point can
cause the compile point (or top-level) containing it to change accordingly.

When this is set to False (default), Synplify Pro keeps the top level module the
same, which is desired by incremental flow.

When this is set to True, changes in low level partitions will be propagated to
top partitions up to top module. Synplify Pro will possibly optimize timing data
and certainly will write a new timestamp onto the partition for the top level
module.

This option is equivalent to the “set_option -update_models_cp 1 | 0”

command in Synplify Pro.

Use Clock Period for Unconstrained I/O

Controls whether to forward annotate constraints for I/O ports without explicit
user-defined constraints.

When this is set to True, only explicit I/O port constraints are forward
annotated. When it is set to False (the default), all I/O port constraints are
forward annotated.

This option is equivalent to the “set_option -auto_constraint_io 1 | 0”

command in Synplify Pro.

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VHDL 2008 (for Synplify Pro)

When this is set to True, VHDL 2008 is selected as the VHDL standard for the
project.

LSE Options
This page lists all the strategy options associated with the LSE synthesis
process.

Allow Duplicate Modules (for LSE)

When set to True, allows the design to keep duplicate modules. LSE issues a
warning and uses the last definition of the module. Any previous definitions
are ignored. The default is False, which causes an error if there are duplicate
modules.

Allow Mixed Assignments (for LSE) When set to True, having both
blocking and non-blocking assignments to the same variable will be allowed.
A warning will be issued instead of an error.

Carry Chain Length

Specifies the maximum number of carry chain cells (CCUs) that get mapped
to a single carry chain. Default is 0, which is interpreted as infinite length.

This option is equivalent to the “-carry_chain_length” option in the

SYNTHESIS command.

This option is equivalent to the “-allow_duplicate_modules” option in the

SYNTHESIS command.

Command Line Options (for LSE)

Enables additional command line options for the LSE Synthesis process.

To enter a command line option:

1. In the Strategy dialog box, select LSE in the Process list.
2. Double-click the Value column for the Command line Options option.
3. Type in the option and its value (if any) in the text box.
4. Click Apply.

For detailed description on LSE command line options, refer to the Radiant
Software Help. See Reference Guides > Command Line Reference Guide
> Command Line Tool Usage > Running SYNTHESIS from the Command
Line.

DSP Style

Specifies how DSP modules should be implemented: with DSP resources or

with Logic (LUTs).

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This option is equivalent to the “-use_dsp” option in the SYNTHESIS

command.

DSP Utilization

Specifies the percentage of DSP sites that LSE should try to use.

This option is equivalent to the “-dsp_utilization” option in the SYNTHESIS

command.

Decode Unreachable States

When set to True, synthesis infers safe recovery logic from unreachable
states in all the state machines of the design.

This option is equivalent to the “-decode_unreachable_states” option in the

SYNTHESIS command.

Disable Distributed RAM

When set to True, inferred memory will not use the distributed RAM of the
PFUs.

EBR Utilization
Specifies EBR utilization target setting in percent of total vacant sites. LSE will
honor the setting and do the resource computation accordingly. Default is 100
(in percentage).

This option is equivalent to the “-bram_utilization” option in the SYNTHESIS

command.

FSM Encoding Style

Specifies the encoding style to use with the design.

This option is equivalent to the “-fsm_encoding_style” option in the

SYNTHESIS command. Valid options are auto, one-hot, gray, and binary. The
default value is auto, meaning that the tool looks for the best implementation.

Note
The encoding type “gray” only works with less than or equal to four machine states.
When the number of machine states is large than four, LSE will use other encoding
styles and issue the following warning message:
WARNING - Gray encoding is not supported for state machines with more than
four states.

Fix Gated Clocks

When set to True, LSE changes standard gated clocks to forms more
effective for FPGAs. Clocks are gated with AND or OR gates to conserve
power, but in FPGAs such clocks cause skew and prevent global clock
resources from being used. The Fix Gated Clocks option is ignored if the
Optimization Goal option is set to Area.

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The gated clocks must be specified in the .ldc file with create_clock
constraints. All inputs of the gating logic must be driven by primary inputs and
the gating logic must be decomposable. Instantiated primitives and black
boxes are not affected.

Converted clocks and the associated registers are reported in the

synthesis.log file.

Force GSR (for LSE) (Not applicable for iCE40 UltraPlus)

Forces Global Set/Reset Pin usage. (Not applicable for iCE40 UltraPlus).

Available options are:

 No (default) – Does not infer Global Set/Reset in your design.
 Auto – Allows the software to decide whether to infer Global Set/Reset in
your design.
 Yes – Always infers Global Set/Reset in your design.

Ignore Constraint Errors

Enables or disables the LSE synthesis process to ignore constraint errors.

By default, the box is unchecked (False), and LSE terminates processing and
issue an error message when a constraint errors are encountered.

When the box is checked (True), LSE will ignore constraint errors and
continue processing.

The LSE synthesis report includes the setting of this option and the constraint
errors found.

Intermediate File Dump

If you set this to True, LSE will produce intermediate encrypted Verilog files. If
you supply Lattice with these files, they can be decrypted and analyzed for
problems. This option is good for analyzing simulation issues.

This option is equivalent to the “-ifd” option in the SYNTHESIS command.

Loop Limit
Specifies the maximum number of iterations of "for" and "while" loops in the
source code. The limit is applied when the loop index is a variable, not when it
is a constant. The higher the loop_limit, the longer the run time. The default
value is 1950. Setting a higher value may cause stack overflow during some
of the optimizations during synthesis. A lower value will be ignored and the
default used instead.

This option is equivalent to the “-loop_limit” option in the SYNTHESIS

command.

Macro Search Path (for LSE)

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Allows you to specify a path (or paths) to locate physical macro files used in a
given design. The software will add the specified paths to the list of directories
to search when resolving file references. The option can also be used for
indicating the directories containing include files that are specified in the RTL
design files.

You do not need to specify a search path if the necessary file is in the
directory containing the top-level .ngo file or if the FILE attribute in the design
gives a complete path name for the file (instead of a relative path name).

The software follows the following order to search:

1. Current implementation directory
2. Project directory
3. Directories where the LPC or IPX source files reside
4. User-specified macro search paths

To specify a macro search path, double-click the Value box, and directly enter
the path or click the ... button to browse for one or more paths.

This option is equivalent to the “-p” option in the SYNTHESIS command.

Max Fanout Limit

Specifies the maximum fanout setting. LSE will make sure that any net in the
design is not exceeding this limit. Default is 1000 fanouts.

This option is equivalent to the “-max_fanout” option in the SYNTHESIS

command.

Memory Initial Value File Search Path (for LSE)

Allows you to specify a path (or paths) to locate memory initialization file
(.mem) used in a given design. The software will add the specified path(s) to
the list of directories to search when resolving file references.

To specify a search path, double-click the Value box, and directly enter the
path or click the ... button to browse for one or more paths.

This option is equivalent to the “-p” option in the SYNTHESIS command.

Optimization Goal
Enables LSE to optimize the design for area or speed.

Valid options are:

 Area – Optimizes the design for area by reducing the total amount of logic
used for design implementation.

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When Optimization Goal is set to Area, LSE honors the LDC constraints if
there are any. If “Use IO Registers” on page 70 is set to Auto, LSE packs
input and output registers into I/O pad cells.

Note
With the Area setting, LSE also ignores all SDC constraints. These constraints are
not used by LSE and are not added for use by the later stages of implementation.

 Timing – Optimizes the design for speed by reducing the levels of logic.
When Optimization Goal is set to Timing and a create_clock constraint is
available in an .ldc file, LSE ignores the “Target Frequency” on page 69
setting and uses the value from the create_clock constraint instead.
If there are multiple clocks, and if not all the clocks use create_clock
constraint, then LSE will assign 200 MHz constraint on the remaining
clocks in Timing Mode.
If “Use IO Registers” on page 70 is set to Auto, LSE does not pack input
and output registers into I/O pad cells.

The default setting depends on the device type.

For more information, refer to the Radiant Software Help. See User Guides >
Implementing the Design > Synthesizing the Design > Optimizing LSE
for Area and Timing.

This option is equivalent to the “-optimization_goal” option in the SYNTHESIS

command.

Propagate Constants
When set to True (default), enables constant propagation to reduce area,
where possible. LSE will then eliminate the logic used when constant inputs to
logic cause their outputs to be constant.

You can turn off the operation by setting this option to False.

This option is equivalent to the “-propagate_constants” option in the

SYNTHESIS command.

RAM Style
Sets the type of random access memory globally to distributed, embedded
block RAM, or registers.

The default is Auto which attempts to determine the best implementation, that
is, the synthesis tool will map to technology RAM resources (EBR/Distributed)
based on the resource availability.

This option will apply a syn_ramstyle attribute globally in the source to a

module or to a RAM instance. To turn off RAM inference, set its value to
Registers.
 Registers – Causes an inferred RAM to be mapped to registers (flip-flops
and logic) rather than the technology-specific RAM resources.

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 Distributed – Causes the RAM to be implemented using the distributed

RAM or PFU resources.
 Block_RAM – Causes the RAM to be implemented using the dedicated
RAM resources. If your RAM resources are limited, for whatever reason,
you can map additional RAMs to registers instead of the dedicated or
distributed RAM resources using this attribute.

This option is equivalent to the “-ramstyle” option in the SYNTHESIS

command.

ROM Style
Allows you to globally implement ROM architectures using dedicated,
distributed ROM, or a combination of the two (Auto).

This applies the syn_romstyle attribute globally to the design by adding the
attribute to the module or entity. You can also specify this attribute on a single
module or ROM instance.

Specifying a syn_romstyle attribute globally or on a module or ROM instance

with a value of:
 Auto (default) – Allows the synthesis tool to choose the best
implementation to meet the design requirements for speed, size, and so
on.
 Logic – Causes the ROM to be implemented using the distributed ROM or
PFU resources. Specifically, the logic value will implement ROM to logic
(LUT4) or ROM technology primitives.
 EBR – Causes the ROM to be mapped to dedicated EBR block resources.
ROM address or data should be registered to map it to an EBR block. If
your ROM resources are limited, for whatever reason, you can map
additional ROM to registers instead of the dedicated or distributed RAM
resources using this attribute.

Infer ROM architectures using a CASE statement in your code. For the
synthesis tool to implement a ROM, at least half of the available addresses in
the CASE statement must be assigned a value. For example, consider a
ROM with six address bits (64 unique addresses). The CASE statement for
this ROM must specify values for at least 32 of the available addresses.

This option is equivalent to the “-romstyle” option in the SYNTHESIS

command.

Read Write Check on RAM

(iCE40UP Only) Adds (True) or does not add (False) the glue logic to resolve
read/write conflicts wherever needed. Default is False.

Remove Duplicate Registers

Specifies the removal of duplicate registers.

When set to True (default), LSE removes a register if it is identical to another

register. If two registers generate the same logic, the second one will be

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deleted and the first one will be made to fan out to the second one's
destinations. LSE will not remove duplicate registers if this option is set to
False.

This option is equivalent to the “-remove_duplicate_regs” option in the

SYNTHESIS command.

Remove LOC Properties (for LSE)

Setting this to On removes LOC properties in the synthesized design.

Report Trimmed User Nets (for LSE)

When set to True, LSE will report whenever a user-declared HDL net is
trimmed from the netlist.

Resolve Mixed Drivers (for LSE)

If a net is driven by a VCC or GND and active drivers, setting this option to
True connects the net to the VCC or GND driver.

Resource Sharing (for LSE)

When this is set to True (default), the synthesis tool uses resource sharing
techniques to optimize area.

With resource sharing, synthesis uses the same arithmetic operators for
mutually exclusive statements; for example, with the branches of a case
statement. Conversely, you can improve timing by disabling resource sharing,
but at the expense of increased area.

This option is equivalent to the “-resource_sharing” option in the SYNTHESIS

command.

Target Frequency
Specifies the target frequency setting. This frequency applies to all the clocks
in the design. If there are some clocks defined in an .ldc file, the remaining
clocks will get this frequency setting. When a create_clock constraint is
available in an .ldc file, LSE ignores the Target Frequency setting for that
clock and uses the value from the create_clock constraint instead.

This option is equivalent to the “-frequency” option in the SYNTHESIS

command.

Use Carry Chain

Turns on (True) or off (False) carry chain implementation for adders. Default is
True.

This option is equivalent to the “-use_carry_chain” option in the SYNTHESIS

command.

Use IO Insertion
When set to True, LSE uses I/O insertion and GSR.

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This option is equivalent to the “-use_io_insertion” option in the SYNTHESIS

command.

Use IO Registers
When True, this option forces the synthesis tool to pack all input and output
registers into I/O pad cells based on the timing requirements for the target
device family. Auto, the default setting, enables this register packing if
“Optimization Goal” on page 66 is set to Area. If Optimization Goal is Timing
or Balanced, Auto disables register packing.

This option is equivalent to the “-use_io_reg” option in the SYNTHESIS

command.

You can also do control packing on individual registers and ports. Refer to the
Radiant Software Help. See Reference Guides > Constraints Reference
Guide > Lattice Synthesis Engine Constraints > Lattice Synthesis
Engine-Supported HDL Attributes > syn_useioff.

VHDL 2008 (for LSE)

When this is set to True, VHDL 2008 is selected as the VHDL standard for the
project.

Post-Synthesis Options
This page lists all strategy options associated with the Post-Synthesis
process. The options available for user setting are dependent on the target
device of your project.

Command Line Options (for Post-Synthesis)

Enables additional command line options for the associated process.

External Module Files (.udb)

Allows the user to supply already synthesized modules for design assembly
into the top level design. These modules must be already synthesized in
Unified Database (.udb) format.

For example:

c:\case1\ip1.udb; d:\example\aaa\abc.udb

Multiple .udb files can be separated by ‘;’

This internal process, Post-Synthesis, performed after logic synthesis

resolves and assembles lower level modules to top level to complete the
design contents.

All modules contents must be resolved at this stage before the flow can
continue to the next stage.

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Hardware Evaluation

Enables or disables the ability to temporarily test IP in a device without an IP

license. If enabled, a timer is added to the design that allows unlicensed IP to
function for about 4 hours in a device. If disabled, you cannot generate a
bitstream if there are any unlicensed IP in the design.

You might want to disable this option to refine your design while waiting for the
license. You will not be able to generate a bitstream, but you will be able to
see how resources are used (without the timer) and close timing. When you
get the license, you can then generate the bitstream.

Note:
The Hardware Evaluation option is only for a device that does not support bitstream
encryption ability even with a built-in hardware evaluation timer (i.e., LAV-AT device).

Post-Synthesis Timing Analysis

Options
This page lists all strategy options associated with the Post-Synthesis Timing
Analysis process.

Number of End Points

Controls the number of endpoints in the critical endpoint summary.

Number of Paths Per Constraint (for Post-Synthesis Timing Analysis)

Lists detailed logic and route delays for all constrained paths and nets in the
design.

Number of Paths Per Endpoint (for Post-Synthesis Timing Analysis)

Controls maximum number of paths that could be reported for each endpoint.

Number of Unconstrained Paths (for Post-Synthesis Timing Analysis)

Reports paths not covered by a timing preference.

Report Format (for Post-Synthesis Timing Analysis) Specifies the report

format type.
 Lattice Standard – Displays timing report format that is similar to formats
used in many industry timing tools.
 Diamond Style – Displays timing report that is similar to Diamond software
TRACE report.

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Timing Analysis Options (for Post-Synthesis Timing Analysis)

Specifies the analysis type.
 Hold Analysis – Performs hold analysis.
 Standard Setup Analysis – Performs setup time checks.
 Standard Setup and Hold Analysis – Performs both the Standard Setup
Analysis and the Hold Analysis.

Map Design Options

This page lists all strategy options associated with the Map Design process.
The options available for user setting are dependent on the target device of
your project.

Command Line Options (for Map Design)

Enables additional command line options for the associated process.

To enter a command line option:

1. In the Strategy dialog box, select the associated process in the Process
list.
2. Double-click the Value column for the Command line Options option.
3. Type in the option and its value (if any) in the text box. For example: -exp
parPathBased=ON
4. Click Apply.

To reference more information about command line options for the Map
Design process, type map -h <architecture> in a command line window. For
detailed options description, refer to “Running MAP from the Command Line”
on page 194.

Ignore Constraint Errors

Enables or disables the Map Design process to ignore constraint errors.

By default, the box is unchecked (False), and Map Design terminates

processing and issues an error message when constraint errors are
encountered.

When the box is checked (True), Map Design will ignore constraint errors and
continue processing.

The Map Design process report includes the setting of this option and the
constraint errors found.

Infer GSR
(Not applicable for iCE40 UltraPlus): Enables or disables the GSR
inferencing.

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GSR inference is only applicable to PLC slice registers by default. Each

black-box can have its own rules to guide mapper to perform GSR inference.
Rules to be applied according to device architecture specification. For
example, in LIFCL device, it is applicable to SLICE / IO registers, block RAM,
large RAM, and DDR components.

When multiple GSR instances are found in the design, mapper is able to
merge them if their outputs are actually the same wire in the netlist. Otherwise
mapper will issue an error.

Mapper can also create a GSR component if user specified the GSR signal in
the constraint file.

Report Signal Cross Reference

When this is set to True, the map report (.mrp) will show where nets in the
logical design were mapped in the physical design.
The default is False.

Report Symbol Cross Reference

When this is set to True, the map report (.mrp) will show where symbols in the
logical design were mapped in the physical design.
The default is False.

Map Timing Analysis Options

This page lists all strategy options associated with the Map Timing Analysis
process.

Number of End Points

Controls the number of endpoints in the critical endpoint summary.

Number of Paths Per Constraint (for Map Timing Analysis)

Lists detailed logic and route delays for all constrained paths and nets in the
design.

Number of Paths Per Endpoint (for Map Timing Analysis)

Controls maximum number of paths that could be reported for each endpoint.

Number of Unconstrained Paths (for Map Timing Analysis)

Reports paths not covered by a timing preference.

Report Format (for Map Timing Analysis)

Specifies the report format type.
 Lattice Standard – Displays timing report format that is similar to formats
used in many industry timing tools.

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 Diamond Style – Displays timing report that is similar to Diamond software

TRACE report.

Speed for Hold Analysis

Specifies performance grade for hold analysis. This option allows you to
override the default m (minimum) performance grade for hold time analysis,
which represents faster silicon than the fastest performance grade of the
device being targeted.

Speed for Setup Analysis

Specifies performance grade for setup analysis. This option allows you to
override the default performance grade which runs setup analysis against the
performance grade of the device currently targeted by the project
implementation.

Timing Analysis Options (for Map Timing Analysis)

Specifies the analysis type.
 Hold Analysis – Performs hold analysis.
 Standard Setup Analysis – Performs setup time checks.
 Standard Setup and Hold Analysis – Performs both the Standard Setup
Analysis and the Hold Analysis.

Place & Route Design Options

This page lists all strategy options associated with the Place & Route Design
process. The options available for user setting are dependent on the target
device of your project.

Command Line Options (for Place & Route Design)

Allows you to specify options from the par command without directly using the
command line. Type in a string of options without the par command. For
example: -exp parPathBased=ON:parHold=1

For detailed descriptions of placement, routing, and PAR explorer (-exp)

command line options, refer to the Radiant Help. See Reference Guides >
Command Line Reference Guide > Command Line Tool Usage >
Running PAR from the Command Line.

Disable Auto Hold Timing Correction (for Place & Route Design)

When the switch is used, PAR will not check the hold timing of the design, so
no correction of potential hold timing violations will be performed.

Disable Timing Driven (for Place & Route Design)

Enables or disables the timing-driven option for the PAR run.

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When this is set to True, the timing-driven option for the PAR run will not be
used. If this is set to False, PAR automatically uses the timing-driven option if
the Timing Wizard is present and if any timing constraints are found in the
preference file. If selected, the timing-driven option is not invoked in any case
and cost-based placement and routing are done instead.

Two examples of situations in which you might disable this option are:
 You have timing constraints specified in your preference file, but you want
to execute a quick PAR run without using the timing-driven option to give
you a rough idea of how difficult the design is to place and route.
 You only have a single license for the timing-driven option but you want to
use this license for another application (for example, to perform timing-
driven routing within EPIC) that will run at the same time as PAR. This
option keeps the license free for the other application.

Multi-Tasking Node List

Allows you to specify the node file name for the multi-tasking PAR.

The multi-tasking PAR allows you to use multiple machines (nodes) that are
networked together for a multi-run PAR job, significantly reducing the total
amount of time for completion.

For more information on multi-tasking PAR, refer to the Radiant Software

Help. See User Guides > Implementing the Design > Place and Route >
Running Multiple PAR Jobs in Parallel.

Number of Host Machine Cores

Allows you to run multiple threads on your local machine by specifying how
many cores to be used from your local machine. The range is from 0 to 64.

Pack Logic Block Utility

Sets the relative density (of available slices) at which the slices within a
device are to be packed, in terms of a percentage of the available slices in the
device.

This option has great control of the packing density. The value range is 0-100
percent (100 = minimum packing; 0 = maximum density).

If this option is not specified (blank), it defaults to a percentage that depends

on which device is selected. For example, for LIFCL, the default is 75 percent.
The result will be a less dense packing, depending on the size of the design
relative to the number of available slices in the device. If the design is large
compared with the number of available slices in the device, the placer will
make a reasonable effort to pack the design so that it fits in the device.

If you specify a density value for this option, the placer will attempt to pack the
device to that density. The “0” setting results in the densest mapping. If the
design is large compared with the target density, the placer will make an
aggressive packing effort to meet your target. However, this may adversely
impact the design fMAX performance.

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Path-based Placement

Allows you to apply path-based placement. Path-based placement gives

better performance and more predictable results.

Options are Off and On.

Note:
The Pack Logic Block Utility and Path-based Placement strategies are not supported
in the LAV-AT-E device.

Placement Iteration Start Point

Specifies the cost table to use (from 1-100) to begin the PAR run.

The default is 1. Cost tables are not an ordered set. There is no correlation
between a cost table's number and its relative value. If cost table 100 is
reached, placement does not begin at 1 again, even if command options
specify that more placements should be performed.

Placement Iterations
Specifies the maximum number of placement/routing passes (0-100, 0 = run
until solved) to be run (regardless of whether they complete) at the Placement
Effort Level.

Each iteration uses a different cost table when the design is placed and will
produce a different Uniform Database (.udb) file. If you specify a Starting Cost
Table, the iterations begin at that table number.

Placement Save Best Run

Determines the number (1-100) of best outputs of the Place and Route run to
save (defaults to 1).

If no number is specified, all output designs produced by the PLACE &

ROUTE run are saved. The best outputs are determined by a scoring system
described in the section titled Scoring the Routed Design.

This option does not care how many iterations you performed or how many
effort levels were used. It compares every result to every other result.

Prioritize Hold Correction Over Setup Performance (for Place & Route
Design)

During hold timing correction, there may be situations when correcting a hold
timing violation would cause a setup requirement to become violated. By
default, we do not correct the hold violation on such connections so as to
preserve the setup performance, but when this switch is used, we will attempt
to correct the hold violation and let the setup requirement become violated.

Run Placement Only

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Setting this to True prevents the design from being routed. PAR will output a
placed, but not routed Unified Design Database(.udb) file.

This option defaults to False.

Set Speed Grade for Hold Optimization (for Place & Route Design)

This overrides the default speed grade used to perform hold timing analysis.

Set Speed Grade for Setup Optimization

Change performance grade for setup optimization.

Stop Once Timing is Met (for Place & Route Design)

Setting this to True forces the Place and Route Design process to stop as
soon as the timing requirement is satisfied. This option has no effect if the
"Generate Timing Analysis report for each iteration" option is set to True or if
using Run Manager to produce multiple place-and-route runs.

Place & Route Timing Analysis Options

This page lists all strategy options associated with the Place & Route Timing
Analysis process.

Number of End Points (for Place & Route Timing Analysis)

Controls the number of endpoints in the critical endpoint summary.

Number of Paths Per Constraint (for Place & Route Timing Analysis)

Lists detailed logic and route delays for all constrained paths and nets in the
design.

Number of Paths Per Endpoint (for Place & Route Timing Analysis)

Controls maximum number of paths that could be reported for each endpoint.

Number of Unconstrained Paths (for Place & Route Timing Analysis)

Reports paths not covered by a timing preference.

Report Format (for Place & Route Timing Analysis)

Specifies the report format type.
 Lattice Standard – Displays timing report format that is similar to formats
used in many industry timing tools.
 Diamond Style – Displays timing report that is similar to Diamond software
TRACE report.

Speed for Hold Analysis

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Specifies performance grade for hold analysis. This option allows you to
override the default m (minimum) performance grade for hold time analysis,
which represents faster silicon than the fastest performance grade of the
device being targeted.

Speed for Setup Analysis

Specifies performance grade for setup analysis. This option allows you to
override the default performance grade which runs setup analysis against the
performance grade of the device currently targeted by the project
implementation.

Timing Analysis Options (for Place & Route Timing Analysis)

Specifies the analysis type.
 Hold Analysis – Performs hold analysis.
 Standard Setup Analysis – Performs setup time checks.
 Standard Setup and Hold Analysis – Performs both the Standard Setup
Analysis and the Hold Analysis.

IO Timing Analysis Options

The following option is associated with the IO Timing Analysis process.

All Performance Grade

Controls whether the I/O timing report (.ior) will give an in-depth analysis on
all available performance grades or will just produce a summary report on the
worst-case performance grade.
 True - The I/O Timing Report will summarize the worst-case scenario of all
available performance grades.
 False (default) - The I/O Timing Report will only contain a summary of the
worst-case performance grade for the given device.

Timing Simulation Options

This page lists all strategy options associated with the Timing Simulation
process. The options available for user setting are dependent on the target
device of your project.

Generate PUR in the Netlist

When this is set to False, the timing simulation file generation process will not
write PUR instance in the Verilog/VHDL back-annotation netlist. Then you
have to instantiate PUR in the test bench.

Generate X for Setup/Hold Violation

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When this is set to True, the Timing Simulation process will place X notifiers in
the output file on flip-flops with setup and/or hold time violations.

Multichip Module Prefix

Adds a prefix to module names to make them unique for multi-chip simulation.

Negative Setup-Hold Times

Allows you to select negative setup time and negative hold time for better
accuracy.

The default is True. You can set it to False for those simulators that might not
be able to handle negative setup- hold times.

Retarget Speed Grade

Retargets back annotation to a different performance grade than the one used
to create the Uniform Database (.udb) file.

You are limited to those performance grades available for the device used in
the UDB file.

Timing Check With Min Speed Grade

Setting this to True replaces all timing information for back annotation with the
minimum timing for all paths.

This option is used for simulation of hold time requirements. Separate

simulations are required for hold time verification (-min switch) and delay time
verification (normal output).

Timing Simulation Max Delay between Buffers (ps)

Distributes routing delays by splitting the signal and inserting buffers. The
delay value assigned represents the maximum delay number in picoseconds
between each buffer (1000 ps by default).

Verilog Hierarchy Separator

Specifies the hierarchy separator character which will be used in name
generation when the design hierarchy is flattened.

You can specify the following two special characters as the hierarchy
separator: “/” (back-slash) or “.” (period).

Enter the character as is in the edit box. Encapsulate the character with
double quotes, for example, “/”, “.”.

The option is only available for Verilog designs.

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Bitstream Options
This page lists all strategy options associated with the bitstream generation
process. The options available for user setting are dependent on the target
device of your project.

Bitstream Mode

Generates bitstream for use in special bitstream update flow.

Command Line Options

Enables additional command line options for the associated process.

Enable Early IO Wakeup

Enable IO output as soon as possible. (Not applicable for iCE40 UltraPlus)

Enable Timing Check

When this is set to true and there is timing error in the Place and Route report
file, a dialogue box will display before executing bitstream generation.

Enable Warm Boot

Enables the Warm Boot functionality, provided the design contains an

instance of the WARMBOOT primitive. (iCE40UP)

Initialize EBR Quadrant 0

Write the EBR initialization data into the bitstream for quadrant 0. (iCE40UP)

Initialize EBR Quadrant 1

Write the EBR initialization data into the bitstream for quadrant 1. (iCE40UP)

Initialize EBR Quadrant 2

Write the EBR initialization data into the bitstream for quadrant 2. (iCE40UP)

Initialize EBR Quadrant 3

Write the EBR initialization data into the bitstream for quadrant 3. (iCE40UP)

IP Evaluation

When enabled, a bitstream will be generated for evaluation purposes when an

IP license is not found, but will be limited to a maximum of four hours before
the device resets itself. When disabled, a bitstream will not be generated if an
IP license is not found (Not applicable for iCE40 UltraPlus).

No header
Do not write the bitstream header section. (iCE40UP)

Set All Unused IO No Pullup

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Removes the pullup on the unused I/Os, except Bank 3 I/Os which do not
have pullup. (iCE40UP)

Oscillator Frequency Range

Options include Medium and Slow. Fast is not supported for iCE40UP. Only
for NVCM configuration, not for programming

Depending on the speed of external PROM, this options adjusts the frequency
of the internal oscillator used by the iCE40UP device during configuration.
This is only applicable when the iCE40UP device is used in SPI Master Mode
for configuration.

Output Format
Specifies the type of bitstream to create for an FPGA device.

The following options are available:

 Bit File (Binary) – Generates a binary configuration file (.bin) that contains
the default outputs of the Bit Generation process.
 Raw Bit File (ASCII) – Generates an ASCII raw bit text file (.rbt) of ASCII
ones and zeros that represent the bits in the bitstream file. If you are using
a microprocessor to configure a single FPGA, you can include the Raw Bit
file in the source code as a text file to represent the configuration data.
The sequence of characters in the Raw Bit file is the same as the bit
sequence that will be written into the FPGA.
 Hex File (Headecimal) – Generates a Hexadecimal (.hex) PROM data file
used for Programming into external non-volatile memory, such as parallel
or Serial Peripheral Interface (SPI) Flash devices (iCE40UP only).
 NVCM File (Non-volatile Configuration Memory) – Generates a Non-
volatile Configuration Memory (.nvcm). Each line in this file is a separate
NVCM instruction for bitmap programming. The exceptions are comment
lines (usually the first few lines in the file) which start with the # sign.
Comment lines should be ignored when programming the NVCM array.
The comment lines contain comments as well as header information
(iCE40UP only).

Register Initialization

Enable register initialization section of the bitstream (Not applicable for iCE40
UltraPlus).

Run DRC
When this is set to True, the software runs a physical design rule check and
saves the output to the Bit Generation report file (.bgn).

Running DRC before a bitstream or JEDEC file is produced will detect any
errors that could cause the FPGA to function improperly. If no fatal errors are
detected, it will produce a bitstream or JEDEC file. Run DRC is the default.

SPI Flash Low Power Mode

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Places the PROM in low-power mode after configuration. (iCE40UP)

This option is applicable only when the iCE40UP device is used as SPI
Master Mode for configuration.

Set NVCM Security

Ensures that the contents of the Non-Volatile Configuration Memory (NVCM)

are secure and the configuration data cannot be read out of the device.
(iCE40UP)

Common Tasks
Working with projects includes many tasks, including: creating the project,
editing design files, modifying tool settings, trying different implementations
and strategies, and saving your data.

Creating a Project
See “Creating a New Project” on page 11 for step-by-step instructions.

Changing the Target Device

There are two ways to access the Device Selector dialog box for changing the
target device:
 Double-click the device in the project File List view or right-click it and
choose Edit.
 Choose Project > Device.

Setting the Top Level of the Design

If multiple top levels exist in the hierarchy of your HDL source files, you will
need to set the top-level design unit. After generating the hierarchy, choose
Project > Active Implementation > Set Top-Level Unit. Alternatively, right-
click the implementation and choose this command from the pop-up menu.

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Figure 53: Top-Level Design Unit

In the Project Properties dialog box, select Value next to Top-Level Unit and
select the desired top level from the list.

You can also use the Hierarchy View to set the top-level. Right-click a level
you want to be the top-level in the Hierarchy View and choose Set Top-Level
Unit.

Editing Files
You can open any of the files for editing by double-clicking or by right-clicking
and choosing Open or Open with.

Saving Project Data

In the File menu are the following selections for saving your design and
project data:
 Save – saves the currently active item.
 Save As – saves the active item using a different file name.
 Save All – saves all changed documents.
 Save Project – saves the current project.
 Save Project As – saves the active project using a different project name.
 Archive Project – creates a zip file of the current project in a location you
specify.

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Chapter 6

Radiant Software Design Flow

This chapter describes the design flow in the Radiant software. Running
processes and controlling the flow for alternate what-if scenarios are
explained.

Overview
The FPGA implementation design flow in the Radiant software provides
extensive what-if analysis capabilities for your design. The design flow is
displayed in the Task Detail View at the right end of the Process Toolbar.

Figure 54: Design Flow Shown in Task Detail View

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Design Flow Processes

The design flow is organized into discrete processes, where each step allows
you to focus on a different aspect of the FPGA implementation.

Synthesize Design This process runs the selected synthesis tool (Lattice
Synthesis Engine is the default) in batch mode to synthesize your HDL
design.
 Synthesis Tool - identifies the selected synthesis tool, Synplify Pro
(default) or Lattice Synthesis Engine.
 Post-Synthesis Timing Analysis - generates timing analysis files.
 Post-Synthesis Simulation File - generates a post-synthesis netlist file
<file_name>_syn.vo used for Post-Synthesis Simulation.

Map Design This process maps the design to the target FPGA and
produces a mapped Unified Database (.udb) design file. Map Design converts
a design’s logical components into placeable components.
 Map Timing Analysis - generates timing analysis files.

Place & Route Design This process takes mapped physical design files
and places and routes the design. The output can be processed by the design
implementation tools. Timing analysis files can also be generated.
 Place & Route Timing Analysis - generates timing analysis files.
 I/O Timing Analysis - generates I/O timing analysis files.

Export Files This process generates the IBIS, simulation, and programming
files that you have selected for export:
 Bitstream File – generates a configuration bitstream (bit images) file,
which contains all of the design’s configuration information that defines
the internal logic and interconnections of the FPGA, as well as device-
specific information from other files.
 IBIS Model – generates a design-specific I/O Buffer Information
Specification model file (.ibs). IBIS models provide a standardized way of
representing the electrical characteristics of a digital IC’s pins (input,
output, and I/O buffers).
 Gate-Level Simulation File – generates a Verilog netlist of the routed
design that is back annotated with timing information. This generated .vo
file enables you to run a timing simulation of your design.

The files for export can also be generated separately by double-clicking each
one.

Running Processes
You can perform the following actions for each step in the process flow:
 Run – runs the process, if it has not yet been run.
 Force Run– reruns a process that has already been run.

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 Force Run From Start – reruns all processes from the start to the selected
process.
 Stop – stops a running process.
 Clean Up Process – clears the process state and puts a process into an
initial state as if it had not been run.

The state of each process step is indicated with an icon to the left of the
process. The process status icons description is described in “Process” on
page 35

The Reports View displays detailed information about the process results,
including the last process run. The Messages section shows warning and
error messages and allows you to filter the types of messages that are
displayed. See “Reports” on page 37.

Figure 55: Reports View of Last Process Run

IP Encryption Flow
IP encryption flow enables you to protect your IP design. Following the
industry standard, the Radiant software, through the IP encryption flow, allows
the partnership between the IP Vendor, supported EDA vendor, and Lattice
Semiconductor.

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Figure 56: IP Encryption Flow

The encryption flow uses symmetric and asymmetric encryption methods to

maximize the design security. The symmetric method only involves a single
symmetric key for both, encryption and decryption. The asymmetric method
involves the public-private key pair. The public key is published by a vendor
and is used by the Radiant software. The private key is never revealed to the
public.

The Radiant software supports these cryptographic algorithms:

 AES-128/AES-256: symmetric algorithm used to encrypt the content of
the HDL source file.
 RSA-2048: asymmetric algorithm used to obfuscate a key used in HDL file
encryption. The RSA is defined by the public-private key pair. You must be
familiar with both keys in order to perform RSA decryption.

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HDL File Encryption Flow

The current software version supports encryption of a single HDL source file
per a single command.

The overall HDL file encryption flow is summarized in these steps:

 The source file of the IP design is AES encrypted using a symmetric
session key. The AES encryption uses the CBC-128 or CBC-256
algorithm. In the source files, this section is referred to as a data block.
 The session key is RSA encrypted using the vendor’s Public Key. In the
source files, this section is referred to as a key block. Multiple key blocks
may be present in the source file.
 The encrypted Session key and the encrypted design are merged to a file
generally named the Encrypted RTL.

Each encrypted source file contains a single data block and one or more key
blocks. The number of key blocks depends on the number of provided
vendor’s public keys.

Note
To decrypt an encrypted source file, you must perform the IP encryption flow steps in
the reverse order.

During the next step in the design flow, typically synthesis, the Encrypted RTL
is decrypted to access the original IP design, as shown in the following figure.

Figure 57: HDL Encryption Flow

By separating the encryption of data and key, you can use public keys from
different vendors to encrypt the same HDL file.

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For more information on how to perform HDL encryption, refer to the Radiant
Software Help. See Reference Guides > Command Line Reference Guide
> Command Line Tool Usage > Running HDL Encryption from the
Command Line.

HDL File Encryption Steps

This section provides step-by-step instructions on how to encrypt an HDL file.

The Radiant software provides the key templates you can simply drag-and-
drop into an HDL file. Each key template is specific to an EDA vendor
providing the value of a public key.

To view the templates in Project Navigator, go to the Source Template tool.

Open the Verilog > Encryption Templates folder and select the EDA-
specific key template.

Currently, the Radiant software supports these encryption templates:

 Lattice Semiconductor
 Synplicity-1
 Synplicity-2
 Mentor
 Synopsys
 Aldec
 Cadence
 Combined Sample: provides an example of file holding multiple keys.

Step 1: Prepare the HDL file.

Annotate the HDL source file with protected pragmas. Protected pragmas
provide information regarding the type of the key used to encrypt the HDL file,
the name of the key, and the encryption algorithm.

In this example, the HDL source file will be encrypted by the Lattice Public
Key.
‘pragma protect version=1
‘pragma protect encoding=(enctype=”base64”)

// optional information
‘pragma protect author=”<Your_Name>”
‘pragma protect author_info=”<Your_Information>”

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Step 2: Specify the portion of the HDL source file to

encrypt.
Annotate the HDL file to specify the encryption. Only the portion defined
within these protected pragmas is encrypted.
‘pragma protect begin
// HDL portion that should be encrypted
‘pragma protect end

Step 3: Prepare key.

Define the key with which the HDL file should be encrypted. Each key
definition must contain the following information:
 key_keyowner: specify the owner of the key
 key_keyname: specify the name of the key. Same owner may provide
multiple keys.
 key_keymethod: specify the used cryptographic algorithm. Current
version supports RSA algorithm.
 key_public_key: speficy the exact value of the key.

The key definition can be done in two ways:

Defining the key in the key.txt file: The public encryption key or keys can
be defined in any .txt file. The key file may contain a single public key or a list
of all available public keys. In the Radiant software, all common EDA vendor
public keys are located in <Radiant_install_directory>/ispfpga/data/key.txt file.

The following is an example of Lattice Public Key defined in key.txt file:

‘pragma protect key_keyowner= "Lattice Semiconductor"
‘pragma protect key_keyname= "LSCC_RADIANT_2"
‘pragma protect key_method="rsa"
‘pragma protect key_public_key
MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA0EZKUUhbuB6vSsc7OhQJ
iNAWJR5unW/OWp/LFI71eAl3s9bOYE2OlKdxbai+ndIeo8xFt2btxetUzuR6Srvh
xR2Sj9BbW1QToo2u8JfzD3X7AmRvlwKRX8708DPo4LDHZMA3qh0kfDDWkp2Eausf
LzE2cVxgq7fy/bDhUeN8xKQCSKJ7aguG6kOI6ROoZz21ljzDLUQzhm2qYF8SpU1o
tD8/uw53wLfSuhR3MBOB++xcn2imvSLqdgHWuhX6CtZIx5CD4y8inCbcLy/0Qrf6
sdTN5SAg2OZhjeNdzmqSWqhL2JTDw+Ou2fWzhEd0i/HN0y4NMr6h9fNn8nqxRyE7
IwIDAQAB

Defining the key directly in the HDL file: You may define the Public Key
directly in the HDL file. You may define one or more keys.
‘pragma protect key_keyowner= "Lattice Semiconductor"
‘pragma protect key_keyname= "LSCC_RADIANT_2"
‘pragma protect key_method="rsa"
‘pragma protect key_public_key
MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA0EZKUUhbuB6vSsc7OhQJ
iNAWJR5unW/OWp/LFI71eAl3s9bOYE2OlKdxbai+ndIeo8xFt2btxetUzuR6Srvh
xR2Sj9BbW1QToo2u8JfzD3X7AmRvlwKRX8708DPo4LDHZMA3qh0kfDDWkp2Eausf
LzE2cVxgq7fy/bDhUeN8xKQCSKJ7aguG6kOI6ROoZz21ljzDLUQzhm2qYF8SpU1o
tD8/uw53wLfSuhR3MBOB++xcn2imvSLqdgHWuhX6CtZIx5CD4y8inCbcLy/0Qrf6
sdTN5SAg2OZhjeNdzmqSWqhL2JTDw+Ou2fWzhEd0i/HN0y4NMr6h9fNn8nqxRyE7
IwIDAQAB

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If the key is defined directly in the HDL file, you don’t need to provide the -k
option in the encrypt_hdl command.

Note
The key defined directly in an HDL source file has preference over the key defined in
the key.txt file.

Step 4: Select the encryption algorithm for data

encryption.
The Radiant software supports both a 128-bit and a 256-bit advanced
encryption standard (AES) with CBC mode. Select the type of algorithm by
defining one of the two options. The default is set to 256-bit AES with CBC
mode.
`pragma protect data_method="aes128-cbc"

or
`pragma protect data_method="aes256-cbc"

Step 5: Run the encrypt_hdl Tcl command.

In the Tcl console window, type in the command to encrypt an HDL file. The
option -k may or may not be used depending the location of the key file. The
language selection (-l) and creation of new output file (-o) are optional. The
default is Verilog. If you don’t specify the output file, the tool generates a new
output file named <input_file_name>_enc.v.

If the key was defined in the key.txt file: The command will encrypt the
HDL file with all keys defined in the key.txt file.
encrypt_hdl -k <keyfile> -l <verilog | vhdl> -o <output_file>
<input_file>

If the key was defined directly in the HDL file:

encrypt_hdl -l <verilog | vhdl> -o <output_file> <input_file>

The encrypted file is located at the path specified in the encrypt_hdl

command.

Step 6: Activate the encrypted HDL source file in

the project file.
In the File List view, add the generated file to the project. Right-click on the
encrypted file and choose Include in Implementation.

To see an example of a Verilog or VHDL pragma-annotated HDL source file,

see “Defining Pragmas” on page 180.

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Block-Based Design - Using Macro Blocks

A macro block is a portion of an FPGA design that can be preserved for reuse
afterwards. Some of the benefits of implementing macros in a design include
the ability to reuse blocks in other designs, and the ability to design more
effectively as a team.

Macros contain logic or physical netlist (placed or routed) and is packaged as

an IPM format for reuse. After a macro has been created, it is no longer
parameterizable.

Macro Types:

There are three types of macro preservation levels:

1. Logical (Logic Macro)
 Logic Macro is implemented using Pre-Synthesis Constraint Editor
and after running Synthesize Design.
 Placement regions for Logic Macros are not required. However, if you
want the macro to be placed at a specific area in both macro creation
and reuse, a placement region is required.
 Placement region is constrained inside Macro block but not fixed.
 Routing region is constrained inside Macro block or Buffer Zone (if
present) but not fixed.
 Macro logic preserved.
2. Logical & Physical with Place Info (Firm Macro)
 Firm Macro is implemented using Physical Designer and after running
Map Design (MAP).
 Placement regions are constraints for placement. They may not be
good for achieving better performance as the macro has connections
to I/O ports and other instances placed far away. However, you need
to specify the region for the following cases:
 Create Firm Macro as IP for other designs.
 Create Firm Macro to be reused in other designs.
 Routing regions for Firm Macros are not required.
3. Logic & Physical with Placement & Routing Info (Hard Macro)
 Hard Macro is implemented using Physical Designer and after running
Place & Route Design (PAR).
 Placement region is required for Hard Macros.
 You need to create routing regions for the following cases:
 Create Hard Macro as IP for other designs.
 Create Hard Macro to be reused in other designs.
 Create Hard Macro for functional safety applications.

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Macro Creation:

During macro creation, the macro is implemented as a design block and gets
instantiated in the RTL design. The design contains additional logic to test
macro functionality. Unified Design Database (.udb) supports the design block
to be a macro.
 Macro Module – module in the design database which implements macro
netlist.
 Macro Instance – an instance in the design database where a macro
module is instantiated.

The ldc_create_macro constraint is used to define an instance in a design as

a macro. You can also define regions to guide placement and routing for a
macro.
 Placement Region – physical boundary of placed macro.
 Routing Region – zone surrounding a macro region for additional
resource for routing.

Routing region is always equal to or larger than placement region. It can be

defined as extra buffer on left/right/top/bottom sides compared to placement
region.

Export Macro:

Modules representing macros will be extracted from the design and exported
as a .ipm file. The macro will be the top module in the .ipm file. The name
specified in ldc_create_macro constraint will be used as the name of the top
module.

Macro Reuse:

During macro reuse, the design database checks macro compatibility and
provides APIs for tools to connect the macro to your design. Before
connecting, the macro used in the design must be a black box. Macros are
reused as black boxes in top designs. The implementation of macros will be
connected to top designs during the compilation flow.

This section lists the options available in Block-Based Design.

Topics include:
 Creating a Macro Block
 Creating a Macro Region
 Exporting Macro
 Reusing a Macro Block
 Macro Usage Guidelines

To get some hands-on experience, try the Lattice Radiant Block-Based

Design Tutorial.

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Creating a Macro Block

Macros must be created prior to synthesis because they are defined at logic
instances. For macro creation, you can use a new or an existing project.

Note:
The Lattice Synthesis Engine (LSE) tool is currently not supported in macro creation.

To create a macro block:

 Click Tools > Pre-Synthesis Constraint Editor > Macro tab.

The Macro tab contains the following columns:

 Instance – the Instance column specifies the hierarchical path of the
instance which is defined as a macro. It specifies only one instance in
a constraint.
 Macro Name – the name that is automatically set for the macro
instance. The text boxes under the Macro Name column are editable.
When Instance and Macro Name have been added, the command
line will be updated as follows:

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The ldc_create_macro constraint command tells the logic synthesis

tool which instances are macros.
 Use PIO – the Use PIO column specifies the ports of the selected
instance to define which ports need to use PIO so that it will be
included inside the macro. If you do not manually specify ports, the
PIO in the macro module will be automatically inferred.
When you add ports to the Use PIO column, the command line will be
updated as follows:

 Disable – if you do not want to use the macro, you can select the
checkbox in this column. You will see the #DISABLED# appended in
front of ldc_create_macro constraint.

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After saving the changes in Pre-Synthesis Constraint Editor, the

defined macro is stored in pre-synthesis constraints (.sdc) file for logic
synthesis.
You can also implement macros to a design by adding the
ldc_create_macro constraint to the active .sdc file.

Note:
The default hierarchy separator for Synplify Pro is a “.” (period), while Radiant tools
use “/” (forward slash). If you create a sub-module under more than two hierarchy
levels, you need to manually add the set_hierarchy_separator {/} line or change the
separator from “/” to “.” in the .sdc file.

To check Macro information in Map Report:

 After running MAP, you can view information about the created macros in
the Design Summary section of the Map Report. The details in this report
during the creation stage are based on the ldc_create_macro command
in the .sdc file.
 This section displays the total number of resources used by the created
macro (e.g., LUT, SLICE Register, PIO Register, and Block RAM).

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Creating a Macro Region

Once macro is created, you can create a macro region in Physical Designer
(optional).
 If you already know the macro region, you can add the
ldc_create_region constraint to the post-synthesis constraint (.pdc) file,
or start Physical Designer to create a macro region before running MAP.
 If you want to use the placement result to guide the region creation, you
can run PAR first. After running PAR, open Physical Designer, and
highlight the macro instance from the netlist.
Based on the macro placement result, you can create a macro region for
the selected macro. The regions will be saved to the .pdc file. As a result,
you need to rerun MAP and PAR to use the specified macro regions.

To create a macro region:

 In Physical Designer, right-click on the floorplan layout and select the
Create MACRO REGION… option.

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The Create New MACRO REGION dialog box opens.

The dialog box contains the following fields:

 Macro Region Name -- the name that you set for the macro region.
When specifying the macro region name, you can use any name you like.
This option is mandatory. You may encounter the following error if you do
not set the macro region name.

 Anchor - anchor of the placement region used to place the macro.

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 BBox - width and height of the placement region.

When you enter a value in the Anchor and BBox fields, the range of the
following items might also change:
 Macro Resource (LUTs, REGs, EBRs)
 Buffer Size range
 BBox range
The range changes depending on the value that you enter in the Anchor
and BBox fields.
If you do not enter a value within range in Anchor and BBox fields, you
may encounter the following error.

 Macro dropdown menu -- you can select the predefined macro instance
from the pre-synthesis macro creation.
 Buffer size -- buffer zone of the routing region.
 Buffer left - left buffer zone of the routing region.
 Buffer right - right buffer zone of the routing region.
 Buffer top - top buffer zone of the routing region.
 Buffer bottom - bottom buffer zone of the routing region.
If you do not enter a value within range, you may encounter an error. The
following example shows a buffer size error.

 Color option -- allows you to change the color of the macro region.

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After creating a macro region, click the Save icon in Physical Designer.
The created macro regions are saved into a post-synthesis constraint (.pdc)
file.

The ldc_create_region constraint is designed to define placement region. It

supports additional information of routing region. In the example above, -
buffer_left/-buffer_right/-buffer_top/-buffer_bottom (optional) are used to
define routing region. Without these options, routing region is identical to
placement region.

Once macro regions are defined, you can assign a macro instance to the
region by using ldc_set_location constraint.

Exporting Macro
Once synthesis is passed, you can launch the Export Macro dialog box from
the Tools menu. The dialog box lists all defined macros on the left-hand pane.
You can select them and set their preservation levels. When macro is
exported, a .ipm file will be generated.

To export macro:
 Click Tools > Export Macro.
 In the Export Macro dialog box, you can choose the macro preservation
levels and specify the default path where the macro package will be
exported.

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The macro data can be exported according to a specified preservation level.

During macro reuse, you can set the preservation levels to a lower value.

Logical (Logic Macro)

 After running Synthesize Design and MAP, you can only export to
Logical preservation level.

Logical & Physical with Place Info (Firm Macro)

 For Firm Macro, you can only export to Logical and Logical & Physical
with Place Info preservation levels after running Place & Route Design.

Logic & Physical with Placement & Routing Info (Hard Macro)
 After running PAR, you can export to Logical, Logical & Physical with
Place Info, and Logic & Physical with Placement & Routing Info
preservation levels.

The Export Macro dialog box also contains the following fields:
 Macro Name – displays the name of the selected macro from the Macro
column in the left-hand pane.
 Vendor – displays the vendor name.
 Version – displays the Macro IP version, the default is always 1.0.
 Support Radiant from Version to Version – displays the supported
maximum and minimum Radiant version. The maximum version could be
empty, but the minimum is the same as the current Radiant version.
 Testbench File – testbenches that allow you to do simulation or evaluate
the macro (optional).
 Document File – contains any document such as help, user guide, or
introduction file included in the macro (optional).
 Other Files – any files such as readme files and other documentation
(optional).
 Export to – default path where the macro package will be saved.

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After exporting, a macro .ipm package will be generated. It contains the

following files:
 <macro_name>.mac – contains general information of the macro project.
The following example shows the information included in the .mac file.

 <macro_name>_bb.v – synthesis header file of the macro project. It is

exported to define module interface for synthesis.
 <macro_name>_bb_extra.v – synthesis header file exported with
additional information.
The bb.v and bb_extra.v files may contain the following information:
 TYPE -- specifies the type of the module. Currently, only the "MACRO"
type is supported.
 syn_allowed_resources – allowed resource in the macro region. It is
needed to help create a reasonable-sized macro region.
 Locked – the macro with locked attribute is fixed, not movable.
These information are to be propagated to top design by synthesis tools
when the macro is reused as a black box. Tools can get the information
before the macro is integrated to the top design.
The following example shows the information included in the bb.v file.

The following example shows the information included in the bb_extra.v

file.

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 <macro_name>_sim.vo – exported for macro simulation. The file is

generated based on logic macro.
 <macro_name>.mdb – exported Macro in unified constraints database
(.udb) format. Modules representing macros will be extracted from design
and exported to .ipm files. The macro will be the top module in .ipm file.
The name specified in ldc_create_macro constraint will be used as the
name of the top module.

Reusing a Macro Block

During macro reuse, the design database checks macro compatibility and
provides APIs for tools to integrate macro into the design.

Macros can be reused with different devices of the same family:

 In general, Logic Macros can be reused in different devices from the same
family depending on the preservation level and resources used.
 Firm and Hard Macros can only be reused with the same device.

To reuse a macro within another project:

 For macro reuse, the .ipm file for each respective macro that is exported
can be used by importing the existing .ipm files into your project. The
imported files will be stored under the Input Files folder in the Radiant
software.

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 After running Synthesize Design, the post-synthesis Logic Macro is

merged into your design.
 You can lower the preservation level of the selected .ipm file in Project
Properties (optional). Preservation levels must be equal or less than the
preservation level when macro is exported.
 If the imported macro’s preservation level is Firm Macro, you can
lower it to Logic Macro.
 If the imported macro’s preservation level is Hard Macro, you can
lower it to Logic and Firm Macro.

 When you open Physical Designer, the netlist shows the reused macro
instances. They contain information of the original region from the create
stage.

 Run MAP with reused macro.

 Firm Macro – the post-MAP macro design with placement constraint is
merged into your design.
 Hard Macro – the post-MAP macro design with placement and route
constraint is merged into your design.
 After running MAP, you can view information about the reused macros
in the Design Summary section of the Map Report.

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 This section lists Firm and Hard macro information and attributes
such as device family, preservation level, anchor, and main
resources.
 The syn_resources information generated when exporting macro
(e.g., LUT, REG, Block RAM, LRAM) determines the main
resources listed in the Map Report.

 You can also create a macro region with the Exclusive option in Physical
Designer. This option excludes other logic from the region for placement
and routing when reusing the exported Firm and Hard macro.
The Reuse Macro Region dialog box opens when you right-click on a
macro instance from the netlist and select the Reuse macro region...
option.

For these macro instances, you can only enable the Exclusive option. The
text boxes are grayed out.

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 Once done, click the Save icon in Physical Designer.

The created macro regions are saved into a post-synthesis constraint
(.pdc) file. The -exclusive option will be added to the ldc_create_region
command line if Exclusive was enabled from the Reuse Macro Region
dialog box.

 Run PAR with reused macro.

After running PAR, you can open Physical Designer and select Routing
Mode to see the macro instances in the physical netlist.

Macro Usage Guidelines

Macro creation and reuse have the following guidelines:
 Macro is created from logic instance.

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 For multiple macro instances, you need to create a wrapper on top of

them.
 Macro creation is instance based. If the whole design is a macro, you
need to instantiate it in a top design with a wrapper.
 For macro reuse, macro black box timing model is not supported.
Synthesis cannot optimize macro's interface data paths. PAR will need to
see full netlist to run timing analysis.
 Macro cannot contain JTAG and PCS hard-IP, which may require merging
with others during reuse.
 Place/Route region only supports a single rectangular region.
 A module to be created as a macro block cannot contain black boxes.

Implementation Flow and Tasks

Implementations organize the structure of your design and allow you to try
alternate structures and tool settings to determine which ones will give you
the best results.

To help determine which scenario best meets your project goals, use a
different implementation of a design using the same tool strategy, or run the
same implementation with different strategies. Each implementation has an
associated active strategy, and when you create a new implementation you
must select its active strategy.

To try a new implementation with different strategies, you must create a new
implementation/strategy combination.
1. Right-click the project name in File List.
2. Choose Add > New Implementation.
3. In the dialog box, choose a source file from an existing implementation
using the Add Source drop-down menu.
4. Choose a strategy using the Default Strategy drop-down menu.

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Figure 58: Adding a Source to a New Implementation

To use the same source for new and existing implementations, make sure that
the “Copy source to implementation directory” option is not selected. This will
ensure that your source is kept in sync between the two implementations.

Synthesis Constraint Creation

Synthesis constraints can be added to a design implementation in the format
of the Synopsys Design Constraint language, while constraints can be added
in the Synopsys standard timing constraints format in the form of FPGA
Design Constraint (LDC, PDC, or FDC format) files.

If you are using the Lattice Synthesis Engine, the synthesis constraints will be
included in an .ldc file. If you are using Synplify Pro for synthesis, the
constraints will be included in an .fdc file. The older .sdc file format is also
supported for constraints.

To create a new synthesis constraint file, right-click the Synthesis Constraint

Files folder in the File List pane and choose Add > New File. In the New File
dialog box, select one of the following and give the file a name:
 Pre-Synthesis Constraint Files (.ldc)
 Post-Synthesis Constraint Files (.pdc)
 Synplify Pro Constraint Files (.fdc)

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Figure 59: New Synthesis Constraint Files

The .ldc, .pdc, or .fdc file will open in the Source Editor to allow you to
manually add the constraints. You can use the Pre-Synthesis Constraint
Editor tool to add pre-synthesis constraints to the .ldc file and the Post-
Synthesis Timing Constraint Editor tool to add logic view level post-synthesis
timing constraints to .pdc files. You can also use the Device Constraint Editor
and Floorplan View to add physical constraints to .pdc files. For detailed
information about setting constraints, see User Guides > Applying Design
Constraints and the Reference Guides > Constraints Reference Guide in
the Radiant Software Help.

An alternative way of adding constraint files is through Source Template. To

view a constraint template, click on the Source Template tab on the left-hand
side of the Project Navigator pane. If not selected, make sure it is enabled in
View > Show Views > Source Template. The list of constraint templates
includes the timing constraints, physical constraints, and user templates.
Select a template and copy and paste it into your active design.

Constraint Creation
LDC (pre-synthesis) and PDC (post-synthesis) files are used to input timing
and physical constraints. The following steps illustrate how to assign and edit
constraints in the Radiant software and implement them at each stage of the
design flow.
1. If desired, define some constraints at the HDL level using HDL attributes.
These source file attributes are included in the Unified Database (UDB),
and will be displayed in the Radiant software after the Map Design
process is run. The following is an example of applying the LOC attribute
in Verilog source code:

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module top (
input clk1,
input datain /* synthesis loc = B12 */,
output ff_clk1out
)
For more information on HDL Attributes, refer to the Radiant Software
Help. See Reference Guides > Constraints Reference Guide > HDL
Attributes.
2. Open one or more of the following tools to create new constraints or to
modify existing constraints from the source files:
 Device Constraint Editor, which consists of:
 Spreadsheet View – the primary view for setting constraints.
 Package View – examines the pin layout of the design, modifies
signal assignments, reserves pin sites that should be excluded
from placement and routing, and runs PIO design rule check to
verify legal placement of signals to pins.
 Device View – examines FPGA device resources.
 Netlist View - shows port types (Input, Output) and groups.
 Timing Constraint Editor. Timing/Physical constraints are entered
through:
 Pre-Synthesis Constraint Editor - used to enter pre-synthesis
constraints such as clocks, clock latency/uncertainty/Group, Input/
Output delays, timing exceptions, and attributes.
 Post-Synthesis Timing Constraint Editor - This post-synthesis
version of the Timing Constraint Editor is used to enter logic view
level timing constraints and physical constraints.
 Floorplan View examines the device layout of the design, draws
bounding boxes for GROUPs, draws REGIONs for the assignment of
groups or to reserve an area, and reserves sites and REGIONs that
should be excluded from placement.
3. Save the constraints to the pre-synthesis constraint file (.ldc) or post-
synthesis constraint file (.pdc).
4. Run the Map Design process (Map).
5. Run the Map Timing Analysis process and examine the timing analysis
report. This is an optional step, but it can be a quick and useful way to
identify serious timing issues in the design and constraint errors (syntax
and semantic). Modify constraints as needed and save them.
6. Run the Place & Route Design process.
7. Open views directly or by cross-probing to examine timing and placement
and create new GROUPs. Also examine the Place & Route Timing report.
8. Modify constraints or create new ones using the appropriate constraint
tool. Save the constraint changes and rerun the Place & Route Design
process.

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Simulation Flow
The simulation flow in the Radiant software supports source files that can be
set in the File List view to be used for the following purposes:
 Simulation and Synthesis (default)
 Simulation
 Synthesis

This allows the use of test benches, including multiple file test benches.
Additionally, multiple representations of the same module can be supported,
such as one for simulation only and one for synthesis only.

You can add top level signals to the waveform display in the simulator and to
automatically start the simulator running.

The Simulation Wizard automatically includes any files that have been set for
simulation only or for both simulation and synthesis. You can select the top of
the design for simulation independent of the implementation design top. This
allows easy support for test bench files, which are normally at the top of the
design for simulation but not included for implementation. The implementation
wizard exports the design top to the simulator, along with source files, and set
the correct top for the .spf file if running timing simulation.

After you add a module, use the Include for menu to specify how the module
file is to be used in the design.

Figure 60: “Include For” Input Files

Simulation Wizard Flow

When you are ready to simulate, export the design using the Simulation
Wizard. Aside from the RTL simulation, you can perform the Post-Synthesis
simulation and Post-Place & Route back annotated netlist simulation.

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Post-Synthesis Simulation File generates a Verilog netlist (_syn.vo) file.

Similarly, the Gate-Level Simulation File generates a Verilog netlist of the
routed design (.vo file) that is back annotated with timing information (.sdf
file). The generated file enables you to run a timing simulation of your design.
For more details on how to generate these files, see “Task Detail View” on
page 36.
1. In the Radiant software, click Tools > Simulation Wizard or click the
icon in the toolbar. The Simulation Wizard opens.
2. In the Preparing the Simulator Interface page click Next.
3. In the Project box, enter the name of your project in the Project Name text
box. In the Project Location box browse to the file path location where you
want to save your simulation project.
When you designate a project name in this wizard page, a corresponding
folder will be created in the file path you choose. If you add a subdirectory
to the default file path the wizard will prompt you to create a new directory.
Click Yes in the popup dialog box that appears.
4. In the Simulator box, click either the ModelSim or Active-HDL simulator
check box.

Notes
 If Aldec-HDL is not installed, it will not be selectable.

 If you change simulation tool, project name will not change. Any previous
Simulation Wizard results will be deleted, and a new simulation will be started
using new simulation files.

5. In the Process Stage box, choose what type of Process Stage of

simulation project you wish to create. Valid types are RTL, Post-
Synthesis, Post-Route Gate-Level, and Post-Route Gate-
Level+Timing. Only those process stages that are available are
activated. Click Next.

Note
If you want to run a post-synthesis simulation, you must first generate a post-
synthesis simulation file (<file_name>_syn.vo) as follows:

 In the Radiant Software, click Task Detail View and check Post-Synthesis
Simulation File.
 In the Process Toolbar, click Synthesize Design.

If you want to run a post-route gate-level+timing simulation, you must first

generate a post-routed, back-annotated simulation file (<file_name>_vo.vo) and a
timing constraint file (<file_name>_vo.sdf) as follows:
 In the Process Toolbar, click Export Files. Ensure that Gate-Level Simulation
File is selected in the Task Detail View .

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Figure 61: New Simulation Project

6. In the Add and Reorder Source page, select from the source files listed in
the Source Files list box or use the browse button to choose a source file
not listed.
 By default, the Automatically Set Simulation Compilation File
Order option is checked.
7. Click Next. If the Automatically Set Simulation Compilation File Order
option was checked in the previous step, you’ll need to specify a top level
simulation test bench in the Simulation Top Module box in the Parse
HDL Files for Simulation box.

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Figure 62: Simulation Top Module

8. Click Next. A Summary page appears that provides information on the

project selections, including the simulation libraries. By default the Run
simulator, Add top-level signals to waveform display, and Run
simulation check boxes are enabled. Their functionality is as follows:
 The Run simulator option launches the simulation tool you chose
earlier in the wizard.
 The Add top-level signals to waveform display option can only be
selected if the Run simulator box is checked. This option adds top-
level signals to the waveform in the simulation tool.
 The Run simulation option can only be selected if the Add top-level
signals to waveform display option is checked. This option causes
your simulation tool to run the simulation automatically.
If the Run simulation option is selected, you can specify the
simulation run length. The default run length is set to 100, measured in
nanoseconds (ns). You can manually enter an integer or fractional
value in the box. A value of 0 will cause the simulator to run the
current simulation continuously, or until it hits a breakpoint or specified
break event. You can specify a different time unit in the dropdown.
Available time units are fs, ps, ns, us, ms, or sec.
 The Resolution dropdown menu supports the -t option in the
Simulation Wizard. If you select a different value from the dropdown
menu instead of "default," this option adds -t <value> to the vsim
command line of the .mdo file.
9. Click Finish. After the simulation is complete, the Simulation Wizard
Project (.spf) file and a simulation script DO file are generated and the
simulation is displayed. If you are using Active-HDL, the wizard will

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generate an .ado file and if you are using ModelSim/Questa, it creates an

.mdo file as well.

In some designs, the compile order of the HDL files passed to the simulator
might result in compilation warnings. In most cases, these compilation
warnings can be safely ignored. The warnings can be eliminated in one of two
ways:
 The correct compilation order for the HDL files can be set manually in the
File List view. After the correct order is determined, the files are sent to the
simulator, which will eliminate any compilation warnings.
 The correct compilation order for the HDL files can be set in the
Simulation Wizard during the “Add and Reorder” step. After the correct
order for the files is set manually, the files will be sent to the simulator,
which will eliminate any compilation warnings.

You can also run the simulation directly from the wizard.

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Chapter 7

Working with Tools and Views

This chapter covers the tools and views controlled from the Radiant software.
Tool descriptions are included and common tasks are described.

Overview
The Radiant design environment streamlines the implementation process for
FPGAs by combining the tool and data views into one common location. Two
main features of this design environment make it easy to keep track of
unsaved changes in your design and examine data objects in different views.

Shared Memory The Radiant software uses shared memory that is

accessed by all tools and views. As soon as design data has been changed,
an asterisk * appears in the tab of the open views, notifying you that unsaved
changes are in memory.

Cross-Probing Shared design data in the Radiant software enables you to

select a data object in one view and display it in another. This cross-probing
capability is especially useful for displaying the physical location of a
component or net after it has been implemented. You can click on a hyperlink
icon to cross-probe into the specific tool. The Radiant software supports:
 Post-Synthesis timing report links to Netlist Analyzer
 Map & PAR timing reports link to Physical Designer’s Placement and
Routing views

View Menu Highlights

The View menu and toolbar control the display of all toolbars, project views,
and display control. Also included in the View menu are the important project-
level features: Start Page and Reports.

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Start Page
The Start Page is displayed by default when you run the Radiant software.
The Start Page enables you to open projects, read product documentation,
and view the software version and updates. You can modify startup behavior
by choosing Tools > Options > General > Startup.

Figure 63: Default Start Page

The Start Page gives you quick access to recent projects and to product
documentation.

Reports
The Reports view provides one central location for the project summary and
design processing reports. It is displayed by default when a project is open.
Alternatively, click on the Reports icon in the toolbar.

Figure 64: Reports View Showing Last Process Run

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The Reports view is organized into Project Summary, Synthesis Reports, Map
Reports, Place & Route Reports, Export Reports, and Misc Reports.

The different file icons indicate:

 A report has been completed (blue check mark).
 A report has never been generated (gray circle).
 A report is out of date (orange question mark).

Select any item to view its report.

The Reports view also supports path cross-probing through the timing or
analysis reports. You can view a specific clock or data path in Netlist Analyzer
and Physical Designer by clicking the icon next to the path.

Figure 65: Cross-Probing

To learn more about cross-probing, view “Cross-Probing” on page 42.

Tools
The entire FPGA implementation process tool set is contained in the Radiant
software. You can run a tool by selecting it from the Tools menu or toolbar.

This section provides an overview of each of these tools. More detailed

information is available in their respective user guides, which you can access
from the Start Page or from the Radiant Software Help. Detailed descriptions
of external tools can be found in their product documentation as well.

If you are viewing an encrypted design, some secured objects may not be
visible in the selected tool. To learn more, see User Guides > Securing the
Design > Secure Objects in the Design in the Help.

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Timing Constraint Editor

The Timing Constraint Editor is used to edit pre-synthesis (.ldc) constraints
and post-synthesis constraints stored in a .pdc file.The Timing Constraint
Editor consists of two tools:
 Pre-Synthesis Constraint Editor
 Post-Synthesis Timing Constraint Editor
Both tools have identical interfaces and the entry mechanisms of the
constraints are also the same. The key differences are that pre-synthesis
constraints are entered pre-synthesis and are synthesized by the chosen
synthesis tool. The post-synthesis constraints are already synthesized and
populated in each of the different constraints tabs. You cannot modify the
post-synthesis constraints that were populated from pre-synthesis, but can
supply new constraints (physical and timing) to either override the existing
one already populated or supply new constraints to better constrain the
design for improved performance upon analysis.
The different constraint types are entered through these tabs:
 Clock - used to define the clocking scheme of the design.
 Generated Clock - used to define generated clocks such as from PLLs.
 Clock Latency - is the delay between the clock source and clock pin. Used
to define the latency in terms of rise and fall times.
 Clock Uncertainty - is the jitter difference of two signals, possibly caused
by clocks. Used to define the amount of uncertainty of a clock or during
clock domain transfer.
 Clock Group - used to specify which clocks are not related in terms of
being logically/physically exclusive and asynchronous.
 Load Capacitance - used to define the load capacitance of ports.
 Input/Output Delay - used for setting input and output delays.
 Timing Exception - used to set min/max, false, and multicycle path
constraints.
 Attribute - used to set synthesis attributes.

Figure 66: Pre-Synthesis Constraint Editor

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Unified Constraints Flow

The goal of the unified constraints flow is to have one constraint file that can
be used by both the synthesis tools (LSE & Synplify Pro). From Radiant 3.0
onwards, pre-synthesis TCE can be launched with Synplify Pro, and
constraints can be saved into an .sdc file, which can be used by both LSE and
Synplify Pro, along with .ldc (for LSE) and .fdc (Synplify Pro).

Table 1: Supported Constraints File Type

Constraint Type Synthesis Tool TCE Support

.ldc LSE Yes

.sdc LSE/Synplify Pro Yes

.fdc Synplify Pro No

Table 2: Difference between Radiant 3.0 (or later) and previous versions
Radiant 1.x/2.x Radiant 3.0 or later

.sdc file For Synplify Pro only For both LSE and Synplify
Pro

The following figure shows the Radiant folder structure. The .ldc constraints
are stored under the Lattice LSE folder, the .fdc constraints are stored under
Synplify Pro, and the newly created .sdc constraints are stored outside these
two folders, which can be commonly used by both synthesis tools.

Notes:
1. If the previous project includes an .sdc file, Radiant 3.0 or later will use it
in the LSE flow, but it can cause unexpected syntax errors.
2. If the previous project includes both .ldc and .sdc files, Radiant 3.0 or later
will force one of them to be inactive. Only one constraint file can be active.
The Timing Constraint Editor can only be launched with the active
constraints file.

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Known Limitations
 Constraints on internal objects from Synplify Pro may not be fully
compatible. The pre-synthesis TCE uses Verific parser for compilation
whereas Synplify Pro uses their own parser. This may cause some name
changes on the internal objects when Synplify Pro is used.
 Pre-Synthesis TCE "Attribute" tab is only supported by LSE. The
attributes are passed using a Lattice Proprietary constraint
"ldc_define_attribute,” which is not supported by Synplify Pro.

See Also
 Reference Guides > Constraints Reference Guide in the Radiant Help.
 User Guides > Applying Design Constraints > Using Radiant
Software Pre-Synthesis Constraints in the Radiant Help.
 User Guides > Applying Design Constraints > Using Radiant
Software Tools > Device Constraint Editor in the Radiant Help

Constraint Propagation
Constraint propagation is not a stand-alone tool, nor do you have to provide
any input to take advantage of this feature.

You usually define constraints for the top-level design as well as include other
constraint files for any IP that are generated with Radiant tools such as IP
Catalog. Constraints defined at the IP level may not contain the correct
hierarchical names and so will not be applied correctly when synthesized. To
help honor as much of the supplied constraints as possible, this feature runs a
design rule check (DRC) on all the input constraints and writes out a new
constraint file to support hierarchical constraints such as soft-IP constraints
and honor top-level constraints.

For more information about Constraint Propagation, refer to the Radiant

Software Help. See User Guides > Applying Design Constraints >
Constraint Propagation.

Device Constraint Editor

The Device Constraint Editor is used to edit post-synthesis constraints. These
constraint editing views are available from the Radiant toolbar and Tools
menu.

All modified constraints are saved to a .pdc file and the flow returned to Map.
The Device Constraint Editor shows the pin layout of the device and displays
the assignments of signals to device pins. This view allows you to edit these
assignments, and reserve sites on the layout to exclude from placement and
routing. The Device Constraint Editor is also the entry mechanism for physical
constraints.

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Device Constraint Editor views, shown in Figure 67, enable you to develop
constraints that will shorten turn-around time and achieve a design that
conforms to critical circuit performance requirements.

Figure 67: Device Constraint Editor

Global Settings
In the Device Constraint Editor tool at the bottom of the tool, there are a series
of tabs to allow you to set many of the device settings such as Junction
Temperature, Voltage, sysCONFIG, User Code, Derating, Bank VCCIO,
Global Set/Reset, Use Primary Net, and Vref Locate constraints.

For more information on how to do this, in addition to detailed information

about Device Constraint Editor, refer to the Radiant Software Help. See User
Guides > Applying Design Constraints > Applying Radiant Software
Physical Constraints > Setting Global Constraints.

sysCONFIG Settings
Defines system configuration option settings for the sysCONFIG feature. If
you do not specify these settings in the .pdc file, using the Global tab in
Device Constraint Editor or manually, some default sysCONFIG constraints
will automatically be generated based on the device selection.

The SYSCONFIG constraint is available for all Lattice FPGA devices that
support the sysCONFIG configuration port. The sysCONFIG port can be a

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single data line or byte-wide (multiple byte) data port that can support serial
and parallel configurations streams. The devices also support daisy chaining.

To set SysConfig parameter values:

1. After opening the design project, choose Tools > Device Constraint
Editor.
2. Select the Global tab at the bottom of the view.
3. In the SysConfig drop down setting, for each parameter in the value
column, double click to bring up the drop down to select a value or, type in
the actual value.

SYSCONFIG Keyword Settings

The following table shows the default settings in bold type and the selectable
settings for all of the keyword values for the SYSCONFIG constraint. They are
ordered as they appear in the Global tab in the Device Constraint Editor.

Device Support

LAV-AT, LFCPNX, LFD2NX, LFMXO5, LIFCL, UT24C, UT24CP

Syntax

ldc_set_sysconfig <keyword>=<value>+

You should set the constraint configuration using the Device Constraint Editor
or by editing the .pdc file directly. If you do not set sysCONFIG options,
default SYSCONFIG constraints are automatically set.

Examples

The SYCSCONFIG constraint allows you to set a series of keyword values in

succession after the ldc_set_sysconfig tcl command.

Figure 68: Example of a SYSCONFIG in the .pdc constraint file

ldc_set_sysconfig {JTAG_PORT=ENABLE PROGRAMN_PORT=ENABLE
MCCLK_FREQ=56.2}

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Table 3: sysCONFIG Values

Keyword Default and Selectable Values Supported Devices

SLAVE_SPI_PORT DISABLE [DISABLE, SERIAL, DUAL, LAV-AT, LFCPNX, LFD2NX,

QUAD] for Nexus Devices LFMXO5, LIFCL, UT24C,
UT24CP
DISABLE [DISABLE, SERIAL, DUAL,
QUAD, XSPI] for Avant Devices

MASTER_SPI_PORT DISABLE [DISABLE, SERIAL, DUAL, LAV-AT, LFCPNX, LFD2NX,

QUAD] for Nexus Devices LFMXO5, LIFCL, UT24C,
UT24CP
DISABLE [DISABLE, SERIAL, DUAL,
QUAD, XSPI, XSPI_DIFF_CLK] for Avant
Devices

SLAVE_I2C_PORT DISABLE [DISABLE, ENABLE] LFCPNX, LFD2NX, LFMXO5,

LIFCL, UT24C, UT24CP

SLAVE_I3C_PORT DISABLE [DISABLE, ENABLE] LFCPNX, LFD2NX, LFMXO5,

LIFCL, UT24C, UT24CP

JTAG_PORT ENABLE [ENABLE, DISABLE] LFCPNX, LFD2NX, LFMXO5,

LIFCL, UT24C, UT24CP

DONE_PORT ENABLE [ENABLE, DISABLE] LFCPNX, LFD2NX, LFMXO5,

LIFCL, UT24C, UT24CP

INITN_PORT ENABLE [ENABLE, DISABLE] LFCPNX, LFD2NX, LFMXO5,

LIFCL, UT24C, UT24CP

PROGRAMN_PORT ENABLE [ENABLE, DISABLE] LFCPNX, LFD2NX, LFMXO5,

LIFCL, UT24C, UT24CP

BACKGROUND_RECONFIG OFF [OFF, ON, SRAM_EBR, LAV-AT, LFCPNX, LFD2NX,

SRAM_ONLY] for Nexus Devices LFMXO5, LIFCL, UT24C,
UT24CP
OFF [OFF, SRAM_ONLY, ON] for Avant
Devices

DONE_EX OFF [OFF, ON] LFCPNX, LFD2NX, LFMXO5,

LIFCL, UT24C, UT24CP

DONE_OD ON [OFF, ON] LFCPNX, LFD2NX, LFMXO5,

LIFCL, UT24C, UT24CP

MCCLK_FREQ See MCCLK section below LAV-AT, LFCPNX, LFD2NX,

LIFCL, UT24C, UT24CP

FLASH_CLK_FREQ 3.5 [ 3.5, 7.0, 14.1, 28.1, 56.2, 75, 90, LFMXO5
112.5]

TRANSFR ON [OFF, ON] for LAV-AT, LFCPNX, LAV-AT, LFCPNX, LFD2NX,

LFMXO5, and UT24CP LFMXO5, LIFCL, UT24C,
UT24CP
OFF [OFF] for LFD2NX, LIFCL, and UT24C

CONFIG_IOSLEW SLOW [SLOW, MEDIUM, FAST] LFCPNX, LFD2NX, LFMXO5,

LIFCL, UT24C, UT24CP

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Keyword Default and Selectable Values Supported Devices

CONFIGIO_VOLTAGE_BANK0/1 NOT_SPECIFIED [NOT_SPECIFIED, 2.5, LAV-AT, LFCPNX, LFD2NX,

1.2, 1.5, 1.8, 3.3] for Nexus devices LFMXO5, LIFCL, UT24C,
UT24CP
NOT_SPECIFIED [NOT_SPECIFIED, 2.5,
1.2, 1.8, 3.3] for Avant devices

CONFIG_SECURE OFF [OFF, ON] LFCPNX, LFD2NX, LFMXO5,

LIFCL, UT24C, UT24CP

WAKE_UP ENABLE[DISABLE]_DONE_SYNC LFCPNX, LFD2NX, LFMXO5,

LIFCL, UT24C, UT24CP

COMPRESS_CONFIG OFF [OFF, ON] LFCPNX, LFD2NX, LFMXO5,

LIFCL, UT24C, UT24CP

EARLY_IO_RELEASE OFF [OFF, ON] LFCPNX, LFD2NX, LFMXO5,

LIFCL, UT24C, UT24CP

BOOTMODE DUAL [DUAL, SINGLE, NONE] LFCPNX, LFD2NX, LFMXO5,

LIFCL, UT24C, UT24CP

MASTER_PREAMBLE_TIMER_C 600000 [600000, 400, 2000, 4000, 20000, LFCPNX, LFD2NX, LFMXO5,
YCLES 40000, 200000, 400000] LIFCL, UT24C, UT24CP

Table 4: Avant sysCONFIG Values

Keyword Default and Selectable Values Supported
Devices

BOOT_SEL DUAL [DUAL, SINGLE] LAV-AT

PROGRAMN_RECOVERY DISABLE [DISABLE, ENABLE] LAV-AT

MSPI_RESET DISABLE [DISABLE, ENABLE] LAV-AT

MULTI_BOOT_MODE DISABLE [DISABLE, ENABLE] LAV-AT

DAISY_CHAIN DISABLE [DISABLE, BYPASS, LAV-AT

FLOW_THROUGH]

DAISY_CHAIN_WAIT_DONE DISABLE [DISABLE, ENABLE] LAV-AT

MSPI_SIGNATURE_TIMER 200MS [200MS, 100MS, 50MS, 40MS, 20MS, LAV-AT

1MS, 500US, 100US]

MSPI_CLK_PHASE RX_RISING_TX_FALLING LAV-AT

[RX_RISING_TX_FALLING,
RX_RISING_TX_RISING,
RX_FALLING_TX_RISING,
RX_FALLING_TX_FALLING]

MSPI_CPOL IDLE_CLOCK_LOW [IDLE_CLOCK_LOW, LAV-AT

IDLE_CLOCK_HIGH]

SSPI_CLK_PHASE RX_RISING_TX_FALLING LAV-AT

[RX_RISING_TX_FALLING,
RX_RISING_TX_RISING,
RX_FALLING_TX_RISING,
RX_FALLING_TX_FALLING]

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Table 4: Avant sysCONFIG Values

Keyword Default and Selectable Values Supported
Devices

SSPI_CPOL IDLE_CLOCK_LOW [IDLE_CLOCK_LOW, LAV-AT

IDLE_CLOCK_HIGH]

SSPI_SHIFT_ORDER MSB_FIRST [MSB_FIRST, LSB_FIRST] LAV-AT

SSPI_DAISY_CHAIN_MODE DISABLE [DISABLE, SCM, AUTO] LAV-AT

ERASE_EBR_ON_REFRRESH ENABLE [ENABLE, DISABLE] LAV-AT

SIGNATURE_CHECK ENABLE_LSCC_SIGNATURE LAV-AT

[ENABLE_LSCC_SIGNATURE, DISABLE,
ENABLE_SFDP_SIGNATURE]

MSPI_ADDRESS_32BIT DISABLE [DISABLE, ENABLE] LAV-AT

MSPI_COMMAND_32BIT DISABLE [DISABLE, ENABLE] LAV-AT

SSPI_IDLE_TIMER DISABLE [DISABLE, 200S, 100S, 50S, 25S, 10S, LAV-AT

5S, 1S, 750MS, 500MS, 250MS, 100MS, 75MS,
50MS, 25MS, 10MS]

MSPI_PREAMBLE_DETECTION_TIMER 200MS [200MS, 100MS, 50MS, 40MS, 20MS, LAV-AT

1MS, 500US, 100US]

MULTI_BOOT_SEL STATIC [STATIC, DYNAMIC] LAV-AT

CONFIGIO_VOLTAGE_BANK1/2 NOT_SPECIFIED [NOT_SPECIFIED, 2.5,1.2,1.8, LAV-AT

3.3]

SLAVE_SPI_PORT

DISABLE (default) | SERIAL | DUAL | QUAD – Nexus Devices

DISABLE (default) | SERIAL | DUAL | QUAD | XSPI – Avant Devices

Specifies if the TARGET_SPI port should be available after configuration. This

option will preserve the dual-purpose pins for PAR.

MASTER_SPI_PORT

DISABLE (default) | SERIAL | DUAL | QUAD – Nexus Devices

DISABLE (default) | SERIAL | DUAL | QUAD | XSPI | XSPI_DIFF_CLK –

Avant Devices

Specifies if the CSPI port should be available after configuration. Used for
background programming of the connected SPI flash. This option will
preserve the dual-purpose pins for PAR. When enabled, it allows the use of
the external Controller SPI port for configuring the SRAM fuses using the
bitstream.

SLAVE_I2C_PORT

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Note
As part of the Lattice inclusive language guidelines, the Avant device's
MASTER_SPI_PORT has been changed to CONTROLLER_SPI_PORT and
SLAVE_SPI_PORT to TARGET_SPI_PORT. If you want to know more about the
Lattice Inclusive Language, please visit Lattice Answer Database.

DISABLE (default) | ENABLE

Specifies if the SLAVE I2C port should be available after configuration. This
option will preserve the dual-purpose pins for PAR.

SLAVE_I3C_PORT

DISABLE (default) | ENABLE

Specifies if the SLAVE I3C port should be available after configuration. This
option will preserve the dual-purpose pins for PAR.

JTAG_PORT

ENABLE (default) | DISABLE

Specifies if the JTAG port should be available after configuration. This option
will preserve the dual-purpose pins for PAR. When ENABLED, it is used for
configuration settings only, PAR will prohibit them. When DISABLED, it can be
used as GPIOs.

DONE_PORT

ENABLE (default) | DISABLE

When set to ENABLE, the pin is not available in user mode.

INITN_PORT

ENABLE (default) | DISABLE

When set to ENABLE, the pin is not available in user mode.

PROGRAMN_PORT

ENABLE (default) | DISABLE

When set to ENABLE, the pin is not available in user mode.

BACKGROUND_RECONFIG

OFF (default) | ON | SRAM_EBR | SRAM_ONLY – Nexus Devices

OFF (default) | SRAM_ONLY | ON – Avant Devices

DONE_EX

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OFF (default) | ON

The customer can select if the device should wake up on its own after the
DONE bit is set or wait for an external DONE signal to drive the DONE pin
high. The DONE_EX attribute will determine if the wake up sequence is
driven by an external DONE signal. If set to ON, the user wishes to delay
wake up until the DONE pin is driven high by an external signal and
synchronous to the clock. The user will select OFF if they want to
synchronously wake up when the DONE bit is set and ignore any external
driving of the DONE pin.

DONE_OD

ON (default) | OFF

Done Pin Open Drain. Enables you to configure the DONE pin as an open
drain pin. By default, the pullup on the DONE pin is active.

The DONE pin used in sysCONFIG to indicate that configuration is done. The
DONE pin can be linked to other DONE pins and used to initiate the wake up
process. The DONE pin can be open collector or active drive. Default is ON
and insures the user needs to make a conscious decision to drive the pin.

MCCLK_FREQ

3.5 (default) | 7.0 | 14.1 | 28.1 | 56.2 | 90 | 112.5 | 150 – Nexus devices.

3.1 (default) | 7.1 | 14.3 | 28.6 | 57.1 | 66.7 | 80.0 | 100.0 | 106.7 | 133.3 | 160.0
– Avant devices.

Controls the Master Clock frequency. When a master configuration mode is

used, MCLK will become an output clock with the frequency set by the user.
Until the device is configured, the default Master Clock frequency is the
lowest frequency support by the device.

For LFCPNX, LFD2NX, LFMXO5, LIFCL, UT24C, and UT24CP devices, a

450 Mhz oscillator is divided and made available for configuration.

For LAV-AT devices, a 400 Mhz oscillator is divided and made available for
configuration.

FLASH_CLK_FREQ

3.5 (default) | 7.0 | 14.1 | 28.1 | 56.2 | 75| 90 | 112.5

TRANSFR

OFF (default) for LAV-AT, LFD2NX, LIFCL, and UT24C. ON [default] for
LFCPNX and UT24CP

For the current supported devices, only OFF is available. When ON is

selected for a future supported device,it sets the CR0 TransFR option. This
will also enable the Hold IO type.

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CONFIG_IOSLEW

SLOW (default) | MEDIUM | FAST

Controls config output pin slew rate. Sets CR0[7:6].

CONFIGIO_VOLTAGE_BANK0/1

NOT_SPECIFIED (default) | 2.5 | 1.2 | 1.5 | 1.8 | 3.3 – Nexus Devices

NOT_SPECIFIED (default) | 2.5 | 1.2 | 1.8 | 3.3 – Avant devices

Setting this attribute informs the software which voltage is required in Bank0/1
to satisfy the user’s sysCONFIG requirements. The sysCONFIG pins used for
configuration may or may not be used in the design and hence the user shall
be able to declare the voltage interface for this bank. DRC errors can then be
generated based on CONFIG_IOVOLTAGE and usage of the dual-purpose
sysCONFIG pins. BANK0 and 1 values can be different and a combination of
the available values including NOT_SPECIFIED.

CONFIGIO_VOLTAGE_BANK1/2

NOT_SPECIFIED (default) | 2.5 | 1.2 | 1.8 | 3.3

The CONFIGIO_VOLTAGE_BANK0/1 attribute supports all devices except

LAV-AT and iCE40UP.

The CONFIGIO_VOLTAGE_BANK1/2 attribute only supports the LAV-AT

devices.

CONFIG_SECURE

OFF (default) | ON

Configuration Security. When set to ON, no readback operation is supported

through the sysCONFIG port or ispJTAG port of the general contents. The
USERCODE area is readable and not considered securable. The OFF setting
indicates that readback is enabled through any port. Prevents readback of the
configuration memory contents.

WAKE_UP

ENABLE/DISABLE_DONE_SYNC (DONE_EX = OFF) /(DONE_EX = ON)

Wake Up. Wake Up is a controlled event after a part has been configured.
External control of the DONE pin can be selected to either delay wake up or
be ignored. See DONE_EX.

The Wake Up sequence controls three internal signals, and the DONE Pin will
be driven after configuration and prior to user mode. If DONE_EX = ON, the
WAKE_UP keyword will take your selected option (1-7), and then the software
will set wake-up signal bits accordingly. If you do not select a wake-up
sequence, the default wake-up sequence will be 4. If DONE_EX = OFF
(default), the WAKE_UP keyword will take your selected option (1-25), and

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then the software will set wake-up signal bits accordingly. If you do not select
a wake-up sequence, the default wake-up sequence will be 21.

COMPRESS_CONFIG

OFF (default)

Bitstream Compression. When set to ON, for those devices that support
bitstream compression, the software generates a compressed version of the
bitstream file.

EARLY_IO_RELEASE

OFF (default) | ON [once]

Program and wakeup the left/right I/O banks early, before the rest of the
device is programmed.

BOOTMODE

DUAL (default) | SINGLE | NONE

This setting enables you to select the booting mode at power up.
 DUAL - Performs the dual boot for the booting event. In case the
primary booting image (bitstream) fails, the secondary boot image is
invoked to boot the device.
 SINGLE - Performs a single boot only. If it fails, the device will move to
unprogrammed mode directly.
 NONE - No controller SPI booting at startup, waits for target
configuration port to configure the device.

MASTER_PREAMBLE_TIMER_CYCLES

600000 (default) | 400 | 2000 | 4000 | 20000 | 40000 | 200000 | 400000

This attribute sets the master preamble timer count value.

The preamble_count value below is the number of clock cycles to get a valid
preamble before an error is declared.

000 -> 600000

001 -> 400000

010 -> 200000

011 -> 40000

100 -> 20000

101 -> 4000

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110 -> 2000

111 -> 400

BOOT_SEL

DUAL (default) | SINGLE

The BOOT_SEL preference allows you to select the booting mode (DUAL or
SINGLE) at power up (POR), PROGRAMN pin toggle or REFRESH
command execution with the following available options:
 DUAL (default) - Performs the dual boot for the booting event. In case
the primary booting image (bitstream) failed, the secondary booting
image is automatically invoked to boot up the device.
 SINGLE - Performs the single boot only. If it fails, the device goes
directly to unprogrammed mode.

PROGRAMN_RECOVERY

DISABLE (default) | ENABLE

The PROGRAMN_RECOVERY preference allows recovery from Secure

Non-Operation (SNOP) state using PROGRAMN with the following available
options:
 DISABLE (default) - Disables recovery from Secure Non-Operation
(SNOP) state using PROGRAMN.
 ENABLE - Enables recovery from Secure Non-Operation (SNOP)
state using PROGRAMN.

MSPI_RESET

DISABLE (default) | ENABLE

Enables the hardware reset signal to the flash device.

The default MSPI_RES attribute has the following options:

 DISABLE - Enables reset port to flash device is disabled.
 ENABLE - Enables reset port to flash device.

MULTI_BOOT_MODE

DISABLE (default) | ENABLE

The MULTI_BOOT_MODE preferences allows you to enable the multi-boot

feature. It has the following options:
 DISABLE - Disables multi-boot feature.
 ENABLE - Enables the multi-boot feature.

DAISY_CHAIN

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DISABLE (default) | BYPASS | FLOW_THROUGH

You can select the daisy chain mode for upstream device using
DAISY_CHAIN preference with the following available options:
 DISABLE - Daisy Chain is disabled (default).
 BYPASS - Enables the transparent SRAM access mode.
 FLOW_THROUGH - Enables the transparent SRAM or/and INIT
Registers access mode.

DAISY_CHAIN_WAIT_DONE

DISABLE (default) | ENABLE

The DAISY_CHAIN_WAIT_DONE preference allows you to wait for the done

pin before “wakeup” for the daisy chain upstream. It has the following options:
 DISABLE (default) - Does not wait for DONE.
 ENABLE - Waits for DONE.

MSPI_SIGNATURE_TIMER

200MS (default) | 100MS | 50MS | 40MS | 20MS | 1MS | 500US | 100US

The MSPI_SIGNATURE_TIMER allows you to specify the time to get a valid

LSCC/SFDP signature.

MSPI_CLK_PHASE

RX_RISING_TX_FALLING (default) | RX_RISING_TX_RISING |

RX_FALLING_TX_RISING | RX_FALLING_TX_FALLING

The MSPI_CLK_PHASE allows you to specify the phase of MSPI RX and TX

clock with the following available options:
 RX_RISING_TX_FALLING (default) - The RX is triggered at the rising
edge and TX is triggered at the falling edge.
 RX_RISING_TX_RISING - Both RX and TX are triggered at the rising
edge.
 RX_FALLING_TX_RISING - The RX is triggered at the falling edge
and TX is triggered at the rising edge.
 RX_FALLING_TX_FALLING - Both RX and TX are triggered at the
falling edge.

MSPI_CPOL

IDLE_CLOCK_LOW (default) | IDLE_CLOCK_HIGH

The MSPI_CPOL specifies the clock to be low or high in idle state.

 IDLE_CLOCK_LOW (default) - Clock is low in idle state.
 IDLE_CLOCK_HIGH - Clock is high in idle state.

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SSPI_CLK_PHASE

RX_RISING_TX_FALLING (default) | RX_RISING_TX_RISING |

RX_FALLING_TX_RISING | RX_FALLING_TX_FALLING

The SSPI_CLK_PHASE allows you to specify the phase of SSPI RX and TX

clock with the following available options:
 RX_RISING_TX_FALLING (default) - The RX is triggered at the rising
edge and TX is triggered at the falling edge.
 RX_RISING_TX_RISING - Both RX and TX are triggered at the rising
edge.
 RX_FALLING_TX_RISING - The RX is triggered at the falling edge
and TX is triggered at the rising edge.
 RX_FALLING_TX_FALLING - Both RX and TX are triggered at the
falling edge.

SSPI_CPOL

IDLE_CLOCK_LOW (default) | IDLE_CLOCK_HIGH

The SSPI_CPOL specifies the clock to be low or high in idle state with the
following available options:
 IDLE_CLOCK_LOW (default) - Clock is low in idle state.
 IDLE_CLOCK_HIGH - Clock is high in idle state.

SSPI_SHIFT_ORDER

MSB_FIRST (default) | LSB_FIRST

The SSPI_SHIFT_ORDER bit specifies the SSPI shift order with the following
available options:
 MSB_FIRST (default) - Shifts the most significant bit first.
 LSB_FIRST - Shifts the least significant bit first.

SSPI_DAISY_CHAIN_MODE

DISABLE (default) | SCM | AUTO

The SSPI_ DAISY_CHAIN_MODE allows you to enable the SSPI auto

function for downstream daisy chain with the following available options:
 DISABLE (default) - Disables SSPI Auto/SCM mode.
 SCM - Persists CLK and MOSI.
 AUTO - SPI Auto mode based on SSPI_PORT selection for SERAIL,
DUAL, QUAD or XSPI.

ERASE_EBR_ON_REFRRESH

ENABLE (default) | DISABLE

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The ERASE_EBR_ON_REFRRESH allows you to enable or disable “erase”

on refresh.

SIGNATURE_CHECK

ENABLE_LSCC_SIGNATURE (default) | DISABLE |

ENABLE_SFDP_SIGNATURE

The SIGNATURE_CHECK preference allows you to check the signature with

the following available options:
 ENABLE_LSCC_SIGNATURE (default) - Checks the LSCC signature.
 DISABLE - Skips signature checking.
 ENABLE_SFDP_SIGNATURE - Checks SFDP signature.

MSPI_ADDRESS_32BIT

DISABLE (default) | ENABLE

The MSPI_ ADDRESS_32BIT enables you to send the 32-bit command set
on MSPI with the following available options:
 DISABLE (default) - 24-bit command set.
 ENABLE - 32-bit command set.

MSPI_COMMAND_32BIT

DISABLE (default) | ENABLE

The MSPI_ ADDRESS_32BIT enables the 32-bit MSPI addressing mode with
the following available options:
 DISABLE (default) - 24-bit MSPI addressing mode.
 ENABLE - 32-bit MSPI addressing mode.

SSPI_IDLE_TIMER

DISABLE (default) | 200S | 100S | 50S | 25S | 10S | 5S | 1S | 750MS | 500MS

| 250MS | 100MS | 75MS | 50MS | 25MS | 10MS

The SSPI_IDLE_TIMER allows you to specify the time to get a valid

preamble.

MSPI_PREAMBLE_DETECTION_TIMER

200MS (default) | 100MS | 50MS | 40MS | 20MS | 1MS | 500US | 100US

The MSPI_PREAMBLE_DETECTION_TIMER allows you to specify the time

to get a valid preamble.

MULTI_BOOT_SEL

STATIC (default) | DYNAMIC

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The MULTI_BOOT_SEL preference allows you to select the multi-boot

address. It has the following options:
 STATIC - Selects the multi-boot address from sysConfig
MULTI_BOOT_OFFSET preference.
 DYNAMIC - Selects the multi-boot address from the
MULTI_BOOT_OFFSET parameter setting of CONFIG_LMMIC
primitive.

SSO Analysis
The Radiant software enables you to run an analysis of simultaneous
switching outputs (SSO). SSO analysis describes the noise on signals caused
by a large number of output drivers that are switching at the same time.
Analysis of SSO helps ensure that your I/O standards and power integrity
meet requirements of the PCB design. This tool can be accessed in the
Device Constraint Editor in the SSO tab at the bottom. From there you can set
output loads, ground plane PCB noise, SSO Allowance %, and power plane
PCB noise values. Once the flow is re-run, an SSO report is generated.

Specifying Virtual I/O Ports

The Radiant Virtual I/O flow is useful in checking the design timing, resource
utilization, or performance of a selected device to determine if your modules
exceeded the number of physical pins present in the FPGA (e.g., during an IP
design). Without the Virtual I/O flow, the implementation will result in an error
due to the number of I/Os exceeding the device capacity. You can use the
Virtual I/O flow to specify certain ports as "virtual" ports at the top level.

Refer to the following flow chart.

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A Virtual I/O is terminated in the LUT instead of a PIO. This is reported as the
"Number of feedthrough LUT4s" in the MAP report, and is not included in the
number of LUTs in the design implementation.

If the total number of real ports in the design is less than or equal to the total
number of I/O ports in the device, you can use the regular Radiant flow for
such IP without the Virtual I/O flow.

To specify the Virtual I/O ports in the selected I/Os:

 In the .pdc file using ldc_set_attribute.

Syntax: ldc_set_attribute {VIRTUAL_IO=TRUE} [get_ports

<port_name>]
ldc_set_attribute {VIRTUAL_IO = TRUE} [get_ports ch0_sdrxp]

Notes:
Wildcard "*" is supported for the port names:
ldc_set_attribute {VIRTUAL_IO = TRUE} [get_ports datain*]

 Using the DCE Spreadsheet View Virtual column, set the required ports
value to "TRUE." By default, the value is set to "FALSE."

See Also
 “Checking the Virtual I/O Ports” on page 137
 “Verifying Virtual I/O Ports” on page 138

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Checking the Virtual I/O Ports

The Virtual I/O attribute for a port is ignored if one of the following conditions
is met:
 The I/O port is with tristate signal.
e.g. tristate output or bi-directional I/O. Tristate support is only in I/O port.
 The I/O port is with LOCATION constraint.
When user specifies the location (either to pin or bank), it is a real external
I/O.
 The I/O port is with IO_TYPE attribute in RTL or constraint.
When user specifies IO_TYPE, it is a real external I/O. Virtual I/O should
not be specified for the ports with IO_TYPE attribute.
 The I/O port is connected with DELAY module.
 The I/O port is not a simple input buffer (IB) or output buffer (OB) but a
special I/O buffer, either from an IP or RTL instantiation.
e.g. MIPI, SEIO18_CORE, DIFFIO18_CORE, etc.
Its special usage means it is a real external I/O.
 The I/O port drives a clock signal or is driven by a clock signal.
 The I/O port is connected to an external I/O directly in a hardware device,
such as:
 APIO pin of a component (e.g. High speed I/O in PCIE)
 JTAG ports
 Some ports of ADC/PMU/I2C etc. components
 IDDR's D input
 ODDR's Q output
 DQS's DQSI input

Notes:
I/O registers are treated differently in the LFCPNX (CertusPro-NX) and UT24CP
(CertusPro-NX-RT) device versus the iCE40UP (iCE40 UltraPlus) device. For the
LFCPNX and UT24CP device, IOLOGIC is a whitebox cell model. I/O registers are
mapped into IOLOGIC. So, when IREG's D input or OREG's Q output is a Virtual I/O
port, the I/O REG will be pushed into PLC (SLICE).
However, for the iCE40UP device, I/O register is in IOLOGIC black box. It is packed by
the synthesis tool. As a result, the Virtual I/O constraints will be ignored for ports
associated with I/O registers.

See Also
 “Specifying Virtual I/O Ports” on page 135
 “Verifying Virtual I/O Ports” on page 138

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Verifying Virtual I/O Ports

There are several ways to verify Virtual I/Os.

Viewing Virtual I/Os in DCE If you have specified the Virtual I/O attributes
for some I/O ports in the Post-Synthesis constraint file (.pdc), you can see
them in the "Virtual" column. As shown in the following figure, the ports
"datain[0]" to "datain[7]" are virtual I/Os.

Changing Virtual I/O attributes in DCE

If you save the result, the Radiant software will ask you to rerun the Map
Design and Place & Route Design processes, since the .pdc file has been
changed.

Viewing Virtual I/Os in the Map Report file

The number of Virtual I/Os are reported in the Map Report (.mrp) file. Here is
an example:

Number of LUT4s: 8 out of 32256 (<1%)

Number used as logic LUT4s: 0

Number used as distributed RAM: 0 (6 per 16X4 RAM)

Number used as ripple logic: 0 (2 per CCU2)

Number of inserted feedthrough LUT4s:8

Number for virtual IO: 8

Number of Virtual IOs: 8

The report shows that the "Number of Virtual I/Os" is 8, and it used 8 LUTs to
replace the specified Virtual I/O ports. These eight LUTs are part of "Number
of inserted feedthrough LUT4s."

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You can find the individual Virtual I/Os in the "I/O (PIO) Attributes" section in
the same .mrp file. If a port is a Virtual I/O, the value is marked as "VIRTUAL"
in column "Levelmode IO_TYPE."

I/O Name Direction Levelmode I/O REG I/O DDR Special I/O Buffer
IO_TYPE

clk INPUT LVCMOS33

datain[7] INPUT VIRTUAL

datain[6] INPUT VIRTUAL

datain[5] INPUT VIRTUAL

See Also
 “Specifying Virtual I/O Ports” on page 135
 “Checking the Virtual I/O Ports” on page 137

Netlist Analyzer
Netlist Analyzer works with Lattice Synthesis Engine (LSE) and Synplify Pro
to produce schematic views of your design while it is being implemented. Use
the schematic views to better understand the hierarchy of the design and how
the design is being implemented.The Netlist Analyzer window has four parts,
as shown in Figure 69.

Figure 69: Netlist Analyzer

 Tool bar provides buttons for various functions.

 Browser provides nested lists of module instances, ports, and nets.
 Schematic view shows a schematic of the design. Depending on the size
of the design, the schematic may be made of multiple sheets.

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 World View, which is a miniature view of the sheet, helps you pan and
zoom in the schematic view.
Netlist Analyzer can have multiple schematics open. The open schematics
are shown on tabs along the bottom of the window.
There are several ways to adjust the view of a schematic and to navigate
through the hierarchy. For more information on how to do this, in addition to
detailed information about Netlist Analyzer, refer to the Radiant Software
Help. See User Guides > Managing Projects > Analyzing a Design.

Physical Designer
Physical Designer provides one central location where you can do all the
floorplanning and be able to view the physical layout of the design. Physical
Designer does this with Placement, IO, and Routing modes.

Placement Mode
Placement Mode provides a large-component layout of your design, and is
available as soon as the target device has been specified. Placement Mode
displays user constraints, and placement and routing information. All
connections are displayed as fly-lines. Placement Mode allows you to create
REGION and GROUP constraints to keep components together. You can
specify the types of components and connections to be displayed. As you
move your mouse pointer over the floorplan layout, details are displayed in
tool-tips and in the status bar, including:
 Number of resources for each GROUP and REGION
 Number of utilized slices for each PLC component
 Name and location of each component, port, net, and site

Figure 70: Placement Mode

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Placement Mode has a Congestion Timing Map view allowing you to debug
timing congested areas of your design. This view gives the timing of the most
critical paths within the slack threshold input. There is also the Congestion
View, which is a read-only view showing the most congested regions based
on wire length and pins selected.

IO Mode
IO Mode is used for I/O assignments such as DDR Interface, DQS, and clock
assignments. I/O resource utilization can be displayed by hovering and
displayed in tool tips.

Figure 71: IO Mode

Routing Mode
Routing Mode provides a read-only detailed layout of your design that
includes physical wire connections. Routed connections are displayed as
Manhattan-style lines, and unrouted connections are displayed as fly-lines.

Figure 72: Routing Mode

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As you move your mouse pointer slowly over the layout, the name and
location of each REGION, group, component, port, net, and site are displayed
as tool tips and also appear in the status bar. The tool tips and status bar also
display the group name for components that are members of a group.

The Routing Mode toolbar allows you to select the types of elements that will
be displayed on the layout, including components, empty sites, pin wires,
routes, and timing paths. Routing Mode is available after placement and
routing.

Timing Analyzer
Timing Analyzer analyzes timing constraints that are present in the .ldc and
.pdc files. These timing constraints are defined in the Timing Constraint Editor
or in a text editor before the design is mapped. A Timing Analysis report file,
which shows the results of timing constraints, is generated each time you run
the LSE, Map Timing Analysis process, or the Place & Route Timing Analysis
(PAR) process. Place & Routing Timing Analysis results can then be viewed
in the Timing Analyzer windows.

The Map Timing Analysis report (.tw1) contains estimated routing that can be
used to verify the expected paths and to provide an estimate of the delays
before you run Place & Route. The PAR Timing Analysis report (.twr) contains
delays based on the actual placement and routing and is a more realistic
estimate of the actual timing.

Figure 73: Timing Analyzer

Timing Analyzer consists of five tabs of information:

 General Information
 Critical Paths Summary
 Critical Endpoint Summary
 Unconstrained Endpoint Summary
 Query

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Each tab can be detached from the main window, rearranged, and resized.
When you select a constraint from the Constraint pane, you can view the path
table details on one pane, and Timing Analyzer report in the other. For
detailed information about Timing Analyzer, see User Guides > Analyzing
Static Timing in the Radiant Software Help.

Using Standalone Timing Analyzer

Standalone Timing Analyzer can be run on designs using post-synthesis,
post-map, post-PAR Unified Design Database (.udb), and associated timing
constraints specified in the .pdc file of the design. Using these input files, it
provides static timing analysis, path tables, and a report of each timing
constraint like the Timing Analyzer in Radiant.

Running Standalone Timing Analyzer from Radiant

Timing Analyzer
When you open the Standalone Analyzer tool, it will automatically create the
Unified Design Database, which includes logic and physical data
(standalone_tav_*.udb). This file is saved to the current project. You can use
this database to run tavmain.exe.

To open and run a timing analysis in Standalone Timing Analyzer:

 In the Radiant software main window, click the button in the upper left.
You can select a different .udb file.
 If you wish to open the Standalone Timing Analyzer directly, click the
button in the upper left or choose Tools > Standalone Timing Analyzer.

See Also
 “Running Standalone Timing Analyzer from the Command Line” on
page 247

Loading Timing Constraint File and Running

Timing Analysis in Standalone Timing Analyzer

To load a timing constraint file and run timing analysis:

1. In the Timing Analyzer main window, choose File > Load Timing
Constraint File. This menu can be used after opening the design.
2. After selecting the constraint file, you can load the timing constraint and
do the timing analysis based on the selected constraint file.
3. If you select Load Timing Constraint File (Incremental Flow), do the timing
analysis based on the constraints in the .udb file and the selected
constraint file.

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Exporting Timing Report and Exporting Timing

Analysis Reports in Standalone Timing Analyzer

To export timing report and timing analysis report:

 In the Timing Analyzer main window, choose File > Export > Timing
Report For Setup/Hold. This menu can export timing analysis reports for
setup or hold (.twr).

Exporting Timing Constraints to PDC File in

Standalone Timing Analyzer

To export timing constraints to PDC file:

 In the Timing Analyzer main window, choose File > Export > Export
Timing Constraints To PDC file.
This menu can be used after opening the design.
 You can export timing constraints in the current .udb file to a .pdc file.

Saving Design Files in Standalone Timing Analyzer

To save design files in Standalone Timing Analyzer:

 You can save changes to design data. In the Timing Analyzer main
window, choose File > Save Design As.

Setting Options in Standalone Timing Analyzer

Setting options in Standalone Timing Analyzer is the same as setting options
in Radiant Timing Analyzer." Refer to the Radiant Help. See User Guides >
Analyzing Static Timing > Using Timing Analyzer > Setting Options in
Timing Analyzer.

To set options in Timing Analyzer:

 In the Timing Analyzer main window, choose Edit > Timing Option Setting,
or click the button in the upper left.
This menu can be used after opening the design.
 When loading the post-synthesis .udb file, you cannot change the speed
in the Timing Option Setting dialog box. This feature is the same as the
timing report.
 The default for the Report Format is Lattice Standard. You can change the
Report Format in the Timing Option Setting dialog box.

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Setting Operating Conditions in Standalone Timing

Analyzer

To set operating conditions in Standalone Timing Analyzer:

1. In the Timing Analyzer main window, choose Edit > Operating
Conditions Setting.
You can change the voltage and temperature based on the current design
data.
2. When you click the OK button, the timing analysis process starts based on
the edited design data.
3. When loading the post-synthesis .udb file, you cannot change the settings
in the Operating Conditions Setting dialog box. This feature is the same
as timing report.

Running Timing Constraint Editor in Standalone

Timing Analyzer

To run timing constraint editor in Standalone Timing Analyzer:

1. In the Timing Analyzer main window, choose Edit > Timing Constraint
Editor. After selecting the Timing Constraint Editor, you can edit the timing
constraint design based on the current design data.
2. When you close the Post-Synthesis Timing Constraint Editor window, a
dialog box appears. If you click yes, the timing analysis process starts
based on the edited design data.

Refreshing Timing in Standalone Timing Analyzer

To refresh timing in Standalone Timing Analyzer:

 In the Timing Analyzer main window, choose Edit > Refresh. Based on
the current timing constraint in the .pdc file, you can do the timing analysis
to check if the new constraint works as expected.

To edit the location of the current .pdc file: You can add the new
constraint in the current .pdc file.
Click the Refresh button to start the timing analysis process.
 To add the new constraint in the .pdc file, you can copy the text from the
timing table.
 If the location of the current .pdc file is not specified, you can also choose
File > Load Timing Constraint File to specify the .pdc file and start the
timing analysis process.

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Reveal Inserter
Reveal Inserter lets you add debug information to your design to allow
hardware debugging using Reveal Analyzer. Reveal Inserter enables you to
select the design signals to use for tracing, triggering, and clocking. Reveal
Inserter will automatically generate the debug core, and insert it into a
modified design with the necessary debug connections and signals. Reveal
Inserter supports VHDL and Verilog sources. After the design has been
modified for debug, it is mapped, placed and routed with the normal design
flow in the Radiant software.

For more information about Reveal Inserter, refer to the Reveal User Guide
for Radiant Software. Also, refer to User Guides > Testing and Debugging
On-Chip in the Radiant Software Help.

Using the Reveal Controller Simulation Model

The Reveal Controller Simulation Model replicates the functionality of Reveal
Controller in simulation.

To set up the Reveal Controller Simulation Model:

1. Choose Tools > Reveal Inserter to insert a reveal module into the
design.
2. Run Synthesize Design to generate the reveal_workspace file.
 If you insert Reveal Controller only, the tool will create the sim_src folder
with the pre-synthesis Reveal generated source file under
reveal_workspace.
 If you insert Reveal Controller and Analyzer, the Reveal engine will not
create the folder and no source files will be provided.
3. Click Tools > Simulation Wizard or click the icon in the toolbar.
4. In the Simulator Project Name and Stage dialog box, enter the project
name.
Click Next.
5. In the Add and Reorder Source dialog box, select and add the source files
from the sim_src folder.
Click Next.

The following compiler directives are all enabled in the source file. You can
use the OEM simulator or any stand-alone simulator to compile and simulate
the Controller:
 `define en_sw
 `define en_led
 `define en_user_mem
 `define en_user_creg
 `define en_user_sreg

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Data Capture Mode

The data capture mode specifies whether Reveal Analyzer can look for one
trigger or multiple triggers in a test run. Multiple Trigger Capture mode
provides the greatest flexibility during test runs. Single Trigger Capture mode
slightly reduces the amount of FPGA resources needed.

To set the data capture mode:

1. In the Data Capture Mode section, select one of the following:
 Single Trigger Capture. Reveal Analyzer captures the data for only
one trigger.
 Multiple Trigger Capture. Reveal Analyzer captures the data for
multiple triggers. The number of triggers is specified in Reveal
Analyzer unless you are creating a module to monitor the power-on
reset (POR) functions (see below).
2. If you select Multiple Trigger Capture, choose the “Minimum samples per
trigger.” The number of samples collected for each trigger is set in Reveal
Analyzer but cannot be smaller than this value.
3. If you select Multiple Trigger Capture and are creating a POR module,
choose the “Number of triggers for POR.” For an explanation of POR
modules, see “Power-on Reset (POR) Debug” on page 147.

Power-on Reset (POR) Debug

An automatic "trigger enable" signal must be built into the Reveal module to
monitor POR functions. Before Reveal Analyzer starts, these functions
happen immediately after the power-on of the test board. When the trigger
enables signal transitions to "active," the module will watch for the trigger and
collect samples. It is similar to clicking the Run button in Reveal Analyzer.
When Reveal Analyzer starts, it loads and displays any data collected by the
POR modules.

POR modules are not supported in iCE40UP devices.

To set a POR trigger enable:

1. In the POR Debug section, select Trigger Enable.
2. Find the POR trigger signal in the Design Tree view and drag it to the text
box in the POR Debug section.
3. Choose whether the signal is Active High or Active Low.

Configuring User Memory Setup

Setting up the User Memory setting consists of assigning six mandatory ports.
(which must be defined in user RTL design) The maximum data width is 32
bits.

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The user design must include a memory block (EBR, Distributed Memory or
PMI Memory) to be able setup User Memory.

The mandatory signals in the user design to setup User Memory are:
 Clock, Clock_enable, Wr_Rdn, Address, WData and RData.

To set up User Memory signals:

1. Select the top_Controller core in the Dataset view. (There can only be one
Controller core.)
When you select Add Controller, it displays the control panel. You can
enable User Memory by choosing the corresponding memory port names.
The Address and Data Width will be updated automatically.
2. Click the User Memory Setup tab.

3. Select signals in the Design Tree and drag the signals to the desired
position in the Setting List in the User Memory Setup tab. For help finding
signals, refer to the Radiant Software Help. See User Guides > Testing
and Debugging On-Chip > Creating Reveal Modules > About Reveal
Inserter > Searching for Signals.
4. Drag the desired signals in to the User Memory data panel to the right.
The width of the signals will automatically update between 4-32 entries at
the top.
5. Beside the title User Memory Setting, there is a check box in which
Controller function for User Memory signals can be enabled/disabled.

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Configuring User Control Register

Setup
The User Control Register Setup tab displays a table-like panel where you
can enable the Control Register. The Control Register address ranges from
0x81000000 up to 0x810000f8.

You can add up to 32-address locations with a maximum data-width of 8-bit. If

the signal has a data width greater than 8, it splits into 8-bit per address
location with a unique label.

The user design must include the control registers as wires, which should not
have any other drivers. They should be treated as asynchronous switches as
they are changed with the JTAG clock.

These signals are read-writable from the controller.

To set up User Control Register:

1. Click the User Control Register Setup tab.

2. Click the Add button. By default, a unique label is assigned to the Name
column. You can edit this label by double-clicking it.
3. Drag-and-drop the corresponding signals from Design View to the
Control Signals column.
Or
4. Select the existing row and double-click the Control Signals column.
The Edit Signals dialog box appears.
5. In the Edit Signals dialog box, do the following:
a. Choose signals from the Select Signals pane.

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b. Click the forward button to move the signals to the right-hand

pane.
c. Change the order of the signals as desired.
d. Click OK.
6. If you wish to delete a row from the Control Signals column, click the
Remove button to delete the selected row.

Configuring User Status Register Setup

The User Status Register Setup tab displays a table-like panel where you can
enable the Status Register. The Status Register address ranges from
0x81001000 up to 0x810010f8.

You can add up to 32-address locations with a maximum data-width of 8-bit. If

the signal has a data width greater than 8, it splits into 8-bit per address
location with a unique label.

The user design must include status registers as wires, which should be
driven by registers to show the status of the different functional blocks of the
design. These signals are read-only.

To set up User Status Register:

1. Click the User Status Register Setup tab.

2. Click the Add button. By default, a unique label is assigned to the Name
column. You can edit this label by double-clicking it.
3. Drag-and-drop the corresponding signals from Design View to the Status
Signals column.
Or

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4. Select the existing row and double-click the Status Signals column.
The Edit Signals dialog box appears.
5. In the Edit Signals dialog box, do the following:
a. Choose signals from the Select Signals pane.

b. Click the forward button to move the signals to the right-hand

pane.
c. Change the order of the signals as desired.
d. Click OK.
6. If you wish to delete a row from the Status Signals column, click the
Remove button to delete the selected row.

Reveal Analyzer
After you generate the bitstream, you can use Reveal Analyzer to debug your
FPGA circuitry. Reveal Analyzer gives you access to internal nodes inside the
device so that you can observe their behavior. It enables you to set and
change various values and combinations of trigger signals. After the specified
trigger condition is reached, the data values of the trace signals are saved in
the trace buffer. After the data is captured, it is transferred from the FPGA
through the JTAG ports to the PC.

For more information about Reveal Analyzer, refer to the Reveal User Guide
for Radiant Software. Also, refer to User Guides > Testing and Debugging
On-Chip in the Radiant Software Help.

User Memory Analysis

The second tab is for User Memory Analysis. The title indicates the range of
the User Memory map. Analysis follows no particular steps or order.
 Default Data: A value that will initialize all memory locations.
 Write Address/Data: Address and data in hex to be written.
 Read Address/Data: Enter address. The data is read back when ‘Read’ is
selected.
 Memory File: You can dump from/to a range of memory addresses to a
.mem file. A user can also Load MemFile to load a pre-configured
memory file.

Running User Control Register

1. In the User Control Register tab, select a label from the Name column,
then click the Rd button.
User Control Register reads the value of the corresponding address
location and executes the following TCL command:

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rva_run_controller -read_control "label"

2. Select a label from the Name column.
3. In the WR Value column, do the following:
a. Enter desired value.
b. Click the Wr button.
User Control Register executes the following TCL command:
rva_run_controller -write_control "label" -data value

4. Double-click a row in the Control Signals column to display the list of

signals with their corresponding value.
5. In the User Control Register tab, click the Apply All button to apply the
value of all address locations assigned by the Name column and execute
multiple TCL commands sequentially.
6. Click the Read All button to read the value of all address locations
assigned by the Name column and execute multiple TCL commands
sequentially.
7. Click the Load button to load the value from the register file to all address
locations of Control Register.
8. Click the Dump button to save the value of all address locations to a
register file.

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Running User Status Register

1. In the User Status Register tab, select a label from the Name column,
then click the Rd button.
User Status Register reads the value of the corresponding address
location and executes the following TCL command:
rva_run_controller -read_status "label"

2. On the bottom left corner, click the Read All button.

The Read All button reads the value of all address locations assigned by
the Name column and executes multiple TCL commands sequentially.
3. On the bottom right corner, click the Dump button.
The Dump button saves the value of all address locations to a register file.
4. Double-click a row in the Status Signals column to display the list of
signals with their corresponding value.

Running Reveal Eye-Opening Monitor

The Reveal Eye-Opening Monitor can be launched from the Reveal Analyzer/
Controller. You need to be connected to a board to be able to run the Eye-
Opening Monitor.

To launch the Eye-Opening Monitor:

1. In the Radiant software main window choose Tools > Reveal Analyzer/
Controller

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In the drop-down menu, choose top_Controller to display the Hard IP

tab.
2. Click the Hard IP tab.
If debugging a non-Avant device, scroll down to the PCS channels to
locate the Eye-Opening Monitor button.
If debugging an Avant device, the Eye-Opening Monitor button is located
at the upper-right of the current IP instance.
3. Click the Eye-Opening Monitor button. The Eye-Opening Monitor dialog
box is displayed.
The figure below shows the Eye-Opening Monitor dialog box when
debugging a non-Avant device.

The figure below shows the Eye-Opening Monitor dialog box when
debugging an Avant device. The Channel and Import options are added.

4. In the Eye-Opening Monitor dialog box, select the quality of the eye
diagram from the drop-down menu.
It is recommended to select normal or low quality for a faster result, and
select high quality for the final result. The default is normal quality.
If you are debugging Avant SerDes multiple channels, select the channel
to debug in the Channel drop-down menu.
5. Click the Run button to start the EOM process. You can stop the process
at any time by clicking the Stop button.

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6. After the EOM has finished running, it will display the eye diagram for the
current channel. The figure below shows the Eye Diagram when
debugging non- Avant devices.

Figure 74: Example of Eye Diagram for Non-Avant Devices

At the bottom of the eye diagram for non-Avant devices, you can click the
View Raw Data button to open the raw data file containing the number of
samples and errors used in calculating the density of the eye diagram.

 The raw data comes from the eom register.

 The numbers from nsample_cur, nsample_pre, nerrors_cur, and
nerrors_pre columns calculate the result.
 The numbers are collected by reading the eom register of the PCS IP.

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If you change the Reveal Controller options, you can re-run the EOM to
display the new eye diagram and view the new raw data until the desired
result is achieved.

Importing an Existing EOM Result

If you are debugging Avant SerDes, each time you run the EOM, the result is
automatically saved as a .txt file in the project folder. The file name provides
information on the EOM settings. For example, the file name
eom_normal_MPPHYX4Q1_L2.txt tells you that the EOM result was
generated using normal quality for the MPPHYX4Q1 instance with L2 or lane
2 as the selected channel.

To import an existing EOM result:

1. Click the Import button in the Eye-Opening Monitor dialog box.
2. The Select Existing EOM File dialog box is displayed.
Selecting AVANT EOM (*.txt) displays only the EOM results for debugging
the Avant device.
3. Select the .txt file and click Open. The Eye Diagram is displayed. The
figure below shows the Eye Diagram when debugging Avant devices.

Figure 75: Example of Eye Diagram for Avant Devices

Reveal Controller
Reveal Controller allows you to emulate an otherwise unavailable
environment for power debug. For example, your evaluation board would only
have a limited number of LEDs or switches but the virtual environment
enables up to 32 bits. Register memory mapping and dumping of values is
also easily manifested while visibility into Hard IP is also enabled.

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For more information about Reveal Controller, refer to the Reveal User Guide
for Radiant Software. Also, refer to User Guides > Testing and Debugging
On-Chip in the Radiant Software Help.

Power Calculator
Power Calculator estimates the power dissipation for your design. It uses
parameters such as voltage, temperature, process variations, air flow, heat
sink, resource utilization, activity and frequency to calculate the device power
consumption. It reports both static and dynamic power consumption.

To launch Power Calculator from the Radiant software, choose Tools >
Power Calculator or click the Power Calculator button on the toolbar.

Power Calculation Modes

Power Calculator opens in estimation mode or calculation mode, depending

on the status of the selected .pcf file. If it opens in calculation mode, the Bank
settings will be from background power database, not from the constraint file.
When you make certain design changes in calculation mode, Power
Calculator reverts to estimation mode.

Power Calculator Pages

When Power Calculator opens, it displays the Power Summary page, which
enables you to change the targeted device, operating conditions, voltage, and
other basic parameters. Updated estimates of power consumption are then
displayed based on these changes. Tabs for other pages, including Power
Matrix, Logic Block, Clocks, I/O, I/O Term, Block RAM, Graph, and Report,
are arranged across the bottom. The number and types of these pages
depends on the target device.

Figure 76: Power Calculator

Power Calculator is also available as a non-integrated tool, which you can

launch without opening the Radiant software. The non-integrated Power

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Calculator provides all the same functionality as the integrated version. To

open the non-integrated Power Calculator from the Windows Start menu,
select Lattice Radiant Software > Accessories > Power Calculator. The
Startup Wizard enables you to create a new Power Calculator project, based
on a selected device or a processed design, or to open an existing Power
Calculator project file (.pcf).

For more information on Power Calculator, see User Guides > Analyzing
Power Consumption in the Radiant Software Help.

ECO Editor
The Engineering Change Order (ECO) Editor enables you to safely make
changes to an implemented design without having to rerun the entire process
flow. Choose Tools > ECO Editor or click the ECO Editor button on the
toolbar.

Figure 77: ECO Editor

ECOs are requests for small changes to be made to your design after it has
been placed and routed. The changes are directly written into the Unified
Database (.udb) file without requiring that you go through the entire design
implementation process.

ECOs are usually intended to correct errors found in the hardware model
during debugging. They are also used to facilitate changes that had to be
made to the design specification because of problems encountered when
other FPGAs or components of the PC board design were integrated.

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The ECO Editor includes windows for editing I/O preferences, and memory
initialization values. It also provides a Change Log window that enables you to
track the changes between the modified .udb file and the post-PAR .udb file.

Note
After you edit your post-PAR UDB file, your functional simulation and timing
simulation will no longer match.

For more information, see Reference Guides > Command Line Reference
Guide > Command Line Tool Usage > Running Various Utilities from the
Command Line > ECO Editor in the Radiant Software Help.

Programmer
The Radiant Programmer is a system for programming devices. The software
supports serial programming of Lattice devices using PC and Linux
environments. The tool also supports embedded microprocessor
programming.

For more information about Programmer and related tools, refer to the
Programming Tools User Guide for Radiant Software. Also, refer to User
Guides > Programming the FPGA in the Radiant Software or Stand-Alone
Programmer Help.

Run Manager
Run Manager runs the processes for the different implementation/strategy
combinations. Choose Tools > Run Manager or click the Run Manager
button on the toolbar.

Run Manager takes the design through the entire process flow for each
selected implementation. If you are running on a multi-core system, Run
Manager will distribute the iterations so that they are executed in parallel. The
option “Maximum implementation processes running in Run Manager” is
available in the General section of the Options dialog box. Choose Tools >
Options to access it. This option enables you to set the maximum number of
processes to run in parallel. Generally, the maximum number of processes
should be the same as the number of cores in your processor; but if the
strategy is using the “Multi-Tasking Node List” option for Place & Route
Design, this number should be set to one.

You can use the Run Manager list to set an implementation as active. Right-
click the implementation/strategy pair and choose Set as Active.

For an implementation that uses multiple iterations of place-and-route, you

can select the iteration that you want to use as the active netlist for further
processes. Expand the implementation list, right-click the desired iteration,
and choose Set as Active. The active iteration is displayed in italics.

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To examine the reports from each process, set an implementation as active,

and then select the Reports view.

See the User Guides > Managing Projects section of the Radiant Software
Help for more information about using implementations, strategies, and Run
Manager.

Synplify Pro for Lattice

Synplify Pro for Lattice is an OEM synthesis tool used in the Radiant software
design flow. Synplify Pro runs in batch mode when you run the Synthesize
Design step in Process View. To examine the output report, select Synplify
Pro in the Process Reports folder of Reports View.

You can also run Synplify Pro in interactive mode. Choose Tools > Synplify
Pro for Lattice or click the Synplify Pro button on the toolbar.

For more information, see the Synplify Pro User Guide, which is available
from the Radiant Start Page or the Synplify Pro Help menu.

Mentor ModelSim
The Mentor® ModelSim® tool is an OEM simulation tool that is closely linked
to the Radiant software environment. It is not run as part of the Process
implementation flow. To run ModelSim, choose Tools > ModelSim Lattice-
Edition or click the ModelSim button on the toolbar.

See “Simulation Flow” on page 111 for more information about simulating your
design. See “Simulation Wizard Flow” on page 111 for information about
creating a simulation project to run in ModelSim.

For complete information about ModelSim, see ModelSim’s online

documentation, which is available from the ModelSim Help menu.

Simulation Wizard
The Simulation Wizard enables you to create a simulation project for your
design. To open Simulation Wizard, choose Tools > Simulation Wizard or
click on the icon in the Radiant software toolbar. The wizard leads you
through a series of steps that include selecting a simulation project name,
location, specifying the simulator type, selecting the process stage to use, and
selecting the source files. To learn more about the flow, view “Simulation
Wizard Flow” on page 111.

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Figure 78: Simulation Wizard

Source Template
Source Template provides templates for creating VHDL, Verilog, and
constraint files. Templates increase the speed and accuracy of design entry.
You can drag and drop a template directly to the source file. You can also
create your own templates. For more information, see “Source Template” on
page 33.

IP Catalog
IP Catalog is an easy way to use a collection of functional blocks from Lattice
Semiconductor. There are two types of functional blocks available through IP
Catalog: modules and IP. IP Catalog enables you to extensively customize
these blocks. They can be created as part of a specific project or as a library
for multiple projects.
 Modules: These basic, configurable blocks come with IP Catalog. They
provide a variety of functions including I/O, arithmetic, memory, and more.
Open IP Catalog to see the full list of what’s available.
 IP: Intellectual property (IP) are more complex, configurable blocks. They
are accessible through IP Catalog, but they do not come with the tool.
They must first be downloaded and installed in a separate step before
they can be accessed from IP Catalog.

Overview of the IP Catalog Process

Below are the basic steps of using IP Catalog modules and IP.

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1. Open IP Catalog. IP Catalog is accessed via a tab at the lower left.of the
Radiant software. Click the tab to view the list of available modules and IP.

2. Customize the module/IP. These modules and IP can be extensively

customized for your design. The options may range from setting the width
of a data bus to selecting features in a communications protocol. At a
minimum you need to specify the design language to use for the output.
3. Generate the module/IP and bring its .ipx file into your project. Prior to
generating the module/IP, select the option “Insert to project.” This will
then automatically bring the .ipx file into your project after the generation
step completes. If you do not select this option, add the .ipx file to your
project after generation as you would with any other source file (such as a
Verilog or VHDL file).
4. Instantiate the module/IP into the project’s design. An HDL instance
template is created during generation to simplify this step.
5. IP Catalog modules and IP can be further modified or updated later. After
the .ipx file has been added to the Radiant software project, it is visible in
the project’s file list. Double-clicking the .ipx file brings up the module/IP’s
configuration dialog box where changes can be made and the generation
process repeated.

For more information on IP Catalog, see User Guides > Entering the Design
> Designing with Soft IP, Modules, and PMI in the Radiant Software Help.

IP Packager
IP Packager is a tool for you to create and IP package easily. You can edit
ports, files, parameters, and memory in the IP Packager, and pack a
customized IP directly.

See Also
 “Running IP Packager and Viewing Documentation” on page 162
 “Installing IP Created with IP Packager into IP Catalog” on page 163

Running IP Packager and Viewing Documentation

IP Packager is a stand-alone tool. IP Packager can be run from both Windows
and Linux. IP Packager documentation is contained within the IP Packager
tool.

To run IP Packager:
 In Windows, go to the Windows Start menu and choose Programs >
Lattice Radiant Software > Accessories > IP Packager.

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 In Linux: from the ./<Radiant Software Install Path>/bin/lin64 directory,

enter the following on a command line:
./ippack.sh

The IP Packager tool opens.

To view IP Packager documentation:

 In the IP Packager main window, choose Help > Help.

The IP Packager can also be run from the command line. Refer to “IP
Packager” on page 245.

See Also
 “IP Packager” on page 162
 “Installing IP Created with IP Packager into IP Catalog” on page 163

Installing IP Created with IP Packager into IP

Catalog
You can download and add IP created with IP Packager into IP Catalog.

To download and add a User IP:

1. In the Radiant IP Catalog, click on the Install a User IP button.
2. In the Select user IP package file to install dialog box, browse to the IP
Package (.ipk) file, and click Open.
 The Soft IP will be installed into a folder in the user’s personal directory.
For example: C:/Users/<username>/RadiantIPLocal/<IP_name>.
 The Soft IP will be added into the IP Catalog.

See Also
 “IP Packager” on page 162
 “Running IP Packager and Viewing Documentation” on page 162

SEI Editor
SEI (Soft Error Injection) Editor allows you to generate single-bit errors, insert
them into a bitstream, and detect them for analysis, simulating the effect of
radiation damage on the device’s configuration memory.

SEI Editor is available after you have placed and routed your design and
generated a bitstream.

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Common Tasks
The Radiant software gathers the many FPGA implementation tools into one
central design environment. This gives you common controls for active tools,
and it provides shared data between views.

Controlling Tool Views

Tool views are highly configurable in the Radiant software environment. You
can detach a tool view to work with it as a separate window, or create tab
groups to display two views side-by-side.

Detaching and Attaching a Tool View

Each integrated tool view contains a Detach button in the upper-right
corner that allows you to work with the tool view as a separate window.

After a tool view is detached, the Detach button changes to an Attach

button , which reintegrates the view into the Radiant main window.

You can detach as many tool views as desired. The Window menu keeps
track of all open tool views and allows you to reintegrate one or all of them
with the main window or detach any of them. Those that are already
integrated are displayed with a check mark.

Figure 79: Window Integrate Tools Menu

Tab Grouping
The Radiant software allows you to split one or more active tools into a
separate tab group. Use the Window menu or the toolbar buttons to create the
tab group and control the display.

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Figure 80: Tab Controls in View Menu

The Split Tab Group command separates the currently active tool into a
separate tab group. Having two separate tab groups enables you to work with
two tool views side-by-side. This is especially useful for dragging and
dropping to make constraint assignments; for example, dragging a port from
Netlist View to Package View in order to assign it to a pin.

Having two separate tab groups is also useful for examining the same data
element in two different views, such as the Netlist Analyzer and Physical
Designer layouts.

Figure 81: Split Tab Group with Side-by-Side Layout Views

Move an active tool view from one tab group to another by dragging and
dropping it, or you can use the Move to Another Tab Group command.

To switch the positions of the two tab groups, click the Switch Tab Group
Position command.

To merge the split tab group back into the main group, click the Merge Tab
Group command.

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Using Zoom Controls

The Radiant software includes display zoom controls in the View toolbar.
There are controls for increasing or reducing the scale of the view, fitting the
display contents to the window view area, and fitting a selected area or object
to the window view area.

Use the mouse to quickly zoom in, out or pan graphical views, such as
Placement Mode and Routing Mode, by doing the following, as shown in
Figure 82:
 Zoom In: press and hold the left mouse button while dragging the mouse
down from upper right to left to zoom in.
 Zoom Out: press and hold the left mouse button while dragging the mouse
up from lower left to right to zoom out.
 Zoom To: press and hold the left mouse button while dragging the mouse
down from upper left to right to zoom into the box created.
 Zoom Fit: press and hold the left mouse button while dragging the mouse
up from lower right to left to reset the diagram so it fits on screen.
 Pan: Click Pan ( ) and drag the mouse in any direction to move the
diagram, or press and hold Ctrl and drag the mouse.

Figure 82: Zoom with Mouse

Zoom In Zoom Out

Zoom Area Zoom Fit

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Displaying Tool Tips

When you place the cursor over a graphical element in a tool view, a tool tip
appears with information on the element. The same information displayed in
the tool tip will also be temporarily shown in the status bar on the lower left of
the main window.

Setting Display Options

The Options dialog box, which is available from the Tools menu, enables you
to specify general environment options as well as customize the display for
the different tools. Tool options include selections for color, font, and other
graphic elements.

Tool Options

For more information about Options, refer to “Environment and Tool Options”
on page 350.

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 Chapter 8

Command Line Reference Guide

This help guide contains information necessary for running the core design
flow development from the command line. For tools that appear in the Radiant
software graphical user interface, use Tcl commands to perform commands
that are described in the Tcl Command Reference Guide.

Command Line Program Overview

Lattice FPGA command line programs can be referred to as the FPGA flow
core tools. These are tools necessary to run a complete design flow and are
used for tasks such as module generation, design implementation, design
verification, and design configuration. This topic provides an overview of
those tools, their functions, and provides links to detailed usage information
on each tool.

Each command line program provides multiple options for specifying device
information, applying special functions using switches, designating desired
output file names, and using command files. The programs also have
particular default behavior often precludes the need for some syntax, making
commands less complex. See Command Line General Guidelines and
Command Line Syntax Conventions.

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To learn more about the applications, usage, and syntax for each command
line program, click on the hyperlink of the command line name in the section
below.

Note
Many of the command line programs described in this topic are run in the background
when using the tools you run in the Radiant software environment. Please also note
that in some cases, command line tools described here are used for earlier FPGA
architectures only, are not always recommended for command line use, or are only
available from the command line.

Design Implementation Using Command Line Tools The table below

shows all of the command line tools used for various design functions, their
graphical user interface counterparts, and provides functional descriptions of
each.

Table 5: The Radiant Software Core Design and Tool Chart

Design Function Command Line Tool Radiant Process Description

Core Implementation and Auxiliary Tools

Encryption Encryption Encrypt Verilog/VHDL files Encrypts the input HDL

source file with provided
encryption key.

Synthesis SYNTHESIS Synthesis Design Runs input source files

through synthesis based on
Lattice Synthesis Engine
options set in Strategies.

Synthesis Synpwrap Synthesis Design Used to manage Synopsys

Synplify Pro synthesis
programs.

Mapping MAP Map Design Converts a design

represented in logical terms
into a network of physical
components or configurable
logic blocks.

Placement and Routing PAR Place & Route Design Assigns physical locations
to mapped components and
creates physical
connections to join
components in an electrical
network.

Static Timing Analysis Timing Post-Synthesis Timing Generates reports that can
Report, MAP Timing Report, be used for static timing
Place & Route Timing analysis.
Report

Back Annotation Backanno Tool does not exist in the Distributes the physical
Radiant software interface design information back to
as process but employed in the logical design to
file export. generate a timing simulation
file.

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Table 5: The Radiant Software Core Design and Tool Chart

Design Function Command Line Tool Radiant Process Description

Bitstream Generation BITGEN Bitstream Converts a fully routed

physical design into
configuration bitstream data.

Device Programming PGRCMD Device Programming Downloads data files to an

FPGA device.

IP Packager IP Packager IP Packager IP author select files from

disks and pack them into
one IPK file.

See Also
 Command Line Data Flow
 Command Line General Guidelines
 Command Line Syntax Conventions
 Invoking Core Tool Command Line Programs

Command Line Basics

This section provides basic instructions for running any of the core design
flow development and tools from the command line.

Topics include:
 Command Line Data Flow
 Command Line General Guidelines
 Command Line Syntax Conventions
 Setting Up the Environment to Run Command Line
 Invoking Core Tool Command Line Programs
 Invoking Core Tool Command Line Tool Help

Command Line Data Flow

The following chart illustrates the FPGA command line tool data flow through
a typical design cycle.

Command Line Tool Data Flow

See Also
 Command Line Reference Guide
 Command Line General Guidelines

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Command Line General Guidelines

You can run the FPGA family Radiant software design tools from the
command line. The following are general guidelines that apply.
 Files are position-dependent. Generally, they follow the convention
[options] <infile> <outfile> (although order of <outfile> and <infile> are
sometimes reversed). Use the -h command line option to check the exact
syntax; for example, par -h.
 For any Radiant software FPGA command line program, you can invoke
help on available options with the -h or -help command. See Invoking
Core Tool Command Line Programs for more information
 Command line options are entered on the command line in any order,
preceded by a hyphen (-), and separated by spaces.
 Most command line options are case-sensitive and must be entered in
lowercase letters. When an option requires an additional parameter, the
option and the parameter must be separated by spaces or tabs (i.e., -l 5 is
correct, -l5 is not).
 Options can appear anywhere on the command line. Arguments that are
bound to a particular option must appear after the option (i.e., -f
<command_file> is legal; <command_file> -f is not).
 For options that may be specified multiple times, in most cases the option
letter must precede each parameter. For example, -b romeo juliet is not
acceptable, while -b romeo -b juliet is acceptable.
 If you enter the FPGA family Radiant software application name on the
command line with no arguments and the application requires one or
more arguments (par, for example), you get a brief usage message
consisting of the command line format string.

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 For any Radiant software FPGA command line program, you can store
program commands in a command file. Execute an entire batch of
arguments by entering the program name, followed by the –f option, and
the command file name. This is useful if you frequently execute the same
arguments each time you execute a program or to avoid typing lengthy
command line arguments. See Using Command Files.

See Also
 Command Line Reference Guide
 Invoking Core Tool Command Line Tool Help
 Command Line Syntax Conventions
 Using Command Files
 Command Line Data Flow

Command Line Syntax Conventions

The following conventions are used when commands are described:

Table 6: Command Line Syntax Conventions

Convention Meaning

() Encloses a logical grouping for a choice between sub-

formats.

[] Encloses items that are optional. (Do not type the

brackets.) Note that <infile[.udb]> indicates that the
.udb extension is optional but that the extension must
be UDB.

{} Encloses items that may be repeated zero or more

times.

| Logical OR function. You must choose one or a

number of options. For example, if the command
syntax says pan up | down | right | left you enter pan
up or pan down or pan right or pan left.

<> Encloses a variable name or number for which you

must substitute information.

, (comma) Indicates a range for an integer variable.

- (dash) Indicates the start of an option name.

: The bind operator. Binds a variable name to a range.

bold text Indicates text to be taken literally. You type this text
exactly as shown (for example, “Type autoroute -all -i
5 in the command area.”) Bold text is also used to
indicate the name of an EPIC command, a Linux
command, or a DOS command (for example, “The
playback command is used to execute the macro you
created.”).

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Table 6: Command Line Syntax Conventions

Convention Meaning

Italic text or text enclosed in Indicates text that is not to be taken literally. You must
angle brackets <> substitute information for the enclosed text. Italic text is
also used to show a file directory path, for example,
“the file is in the /cd/data/Radiant directory”).

Monospace Indicates text that appears on the screen (for example,

“File already exists.”) and text from Linux or DOS text
files. Monospace text is also used for the names of
documents, files, and file extensions (for example,
“Edit the autoexec.bat file”

See Also
 Command Line Reference Guide
 Command Line General Guidelines
 Invoking Core Tool Command Line Tool Help
 Using Command Files

Setting Up the Environment to Run

Command Line
For Windows The environments for both the Radiant Tcl Console window
or Radiant Standalone Tcl Console window (pnmainc.exe) are already set.
You can start entering Tcl tool command or core tool commands in the
console and the software will perform them.

When running the Radiant software from the Windows command line (via
cmd.exe), you will need to add the following values to the following
environment variables:
 PATH includes, for 64-bit
<Install_directory>\bin\nt64;<Install_directory>\ispfpga\bin
\nt64
Example <Install_directory>:
c:\lscc\radiant\1.0\bin\nt64;c:\lscc\radiant\1.0\ispfpga\bin
\nt64
 FOUNDRY includes
set FOUNDRY= <Install_directory>\ispfpga

For Linux On Linux, the Radiant software provides a similar standalone Tcl
Console window (radiantc) that sets the environment. The user can enter Tcl
commands and core tool commands in it.

If you do not use the Tcl Console window, you need to run "bash" to switch to
BASH" first, then run the following command.

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 For BASH (64-bit):

export bindir=<Install_directory>/bin/lin64
source $bindir/radiant_env

After setting up for either Windows or PC, you can run the Radiant software
executable files directly. For example, you can invoke the Place and Route
program by:
par test_map.udb test_par.udb

See Also
 Invoking Core Tool Command Line Programs
 Invoking Core Tool Command Line Tool Help

Invoking Core Tool Command Line

Programs
This topic provides general guidance for running the Radiant software FPGA
flow core tools. Refer to Command Line Program Overview to see what these
tools include and for further information.

For any the Radiant software FPGA command line programs, you begin by
entering the name of the command line program followed by valid options for
the program separated by spaces. Options include switches (-f, -p, -o, etc.),
values for those switches, and file names, which are either input or output
files. You start command line programs by entering a command in the Linux™
or DOS™ command line. You can also run command line scripts or command
files.

SeeTable 6 on page 172 for details and links to specific information on usage
and syntax. You will find all of the usage information on the command line in
the Running FPGA Tools from the Command Line > Command Line Tool
Usage book topics.

See Also
 Command Line Reference Guide
 Command Line Syntax Conventions
 Invoking Core Tool Command Line Tool Help
 Setting Up the Environment to Run Command Line
 Using Command Files

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Invoking Core Tool Command Line Tool

Help
To get a brief usage message plus a verbose message that explains each of
the options and arguments, enter the FPGA family Radiant software
application name on the command line followed by -help or -h. For example,
enter bitgen -h for option descriptions for the bitgen program.

To redirect this message to a file (to read later or to print out), enter this
command:

command_name -help | -h > filename

The usage message is redirected to the filename that you specify.

For those FPGA family Radiant software applications that have architecture-
specific command lines (e.g., iCE UltraPlus), you must enter the application
name, -help (or -h), and the architecture to get the verbose usage message
specific to that architecture. If you fail to specify the architecture, you get a
message similar to the following:

Use '<appname> -help <architecture>' to get detailed usage for a particular

architecture.

See Also
 Command Line Reference Guide
 Command Line Data Flow
 Command Line General Guidelines
 Command Line Syntax Conventions
 Setting Up the Environment to Run Command Line
 Using Command Files

Command Line Tool Usage

This section contains usage information of all of the command line tools and
valid syntax descriptions for each.

Topics include:
 Running cmpl_libs.tcl from the Command Line
 Running HDL Encryption from the Command Line
 Running Synthesis from the Command Line
 Running Postsyn from the Command Line
 Running MAP from the Command Line
 Running PAR from the Command Line
 Running Timing from the Command Line

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 Running Backannotation from the Command Line

 Running Bit Generation from the Command Line
 Running Various Utilities from the Command Line
 Using Command Files
 Using Command Line Shell Scripts

Running cmpl_libs.tcl from the

Command Line
The cmpl_libs.tcl command allows you to perform simulation library
compliation from the command line.

The following information is for running cmpl_libs.tcl from the command line
using the tclsh application. The supported TCL version is 8.5 or higher.

If you do not have TCL installed, or you have an older version, perform the
following:
 Add <Radiant_install_path>/tcltk/windows/BIN to the front of your PATH,
and
 For Linux users only, add <Radiant_install_path>/tcltk/linux/bin to the front
of your LD_LIBRARY_PATH

Note
The default version of TCL on Linux could be older and may cause the script to fail.
Ensure that you have TCL version 8.5 or higher.

To check TCL version, type:

tclsh
% info tclversion
% exit

For script usage, type:

tclsh cmpl_libs.tcl [-h|-help|]

Notes
 If Siemens Questa is already in your PATH and preceding any Aldec tools, you can
use:
'-sim_path .' for simplification; '.' will be added to the front of your PATH.
 Ensure the FOUNDRY environment variable is set. If the FOUNDRY environment
variable is missing, then you need to set it before running the script. For details,
refer to Setting Up the Environment to Run Command Line.
 To execute this script error free, Siemens Questa 2020.4 or a later version should
be used for compilation.

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Check log files under <target_path> (defualt = .) for any errors, as follows:
 For Linux, type:
grep -i error *.log

 For Windows, type:

find /i "error" *.log

Subjects included in this topic:

 Running compl_lib.tcl
 Command Line Syntax
 cmpl_libs.tcl Options
 Examples

Running compl_lib.tcl cmpl_libs.tcl allows you to compile simulation

libraries from the command line.

Command Line Syntax

tclsh <Radiant_install_path>/cae_library/simulation/scripts/cmpl_libs.tcl -
sim_path <sim_path> [-sim_vendor \{mentor<default>|cadence|aldec}] [-
device \{ice40up|lifcl|lfcpnx|lfd2nx|lfmxo5-25|lfmxo5-15d|lfmxo5-100t|lfmxo5-
55t|lavat|ut24c|ut24cp|all<default>}] [-target_path <target_path>]

cmpl_libs.tcl Options

The table below contains all valid options for cmpl_libs.tcl

Table 7: cmpl_libs.tcl Command Line Options

Option Description

-sim_path <sim_path> The -sim_path argument specifies the path to the

simulation tool executable (binary) folder. This option is
mandatory. Currently only ModelSim and QuestaSim
simulators from Mentor, Xcelium simulator from
Cadence and Active-HDL simulator from Aldec are
supported. NOTE: If <sim_path> has spaces, then it
must be surrounded by " ". Do not use { }.

[-sim_vendor The -sim_vendor argument specifies simulation vendor.

{mentor<default>|cadence This argument is optional. If you don't use this
|aldec}] argument, Mentor is chosen by default, and the libraries
are compiled for ModelSim. If you are using QuestaSim
choose mentor, Xcelium choose cadence, Active-HDL
choose aldec for -sim_vendor.

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Table 7: cmpl_libs.tcl Command Line Options

Option Description

[-device The -device argument specifies the Lattice FPGA device

\{ice40up|lifcl|lfcpnx|lfd2nx to compile simulation libraries for. This argument is
|lfmxo5-25|lfmxo5- optional, and the default is to compile libraries for all the
15d|lfmxo5-100t|lfmxo5- Lattice FPGA devices.
55t|lavat|ut24c|ut24cp|all<
default>}]

[-target_path The -target_path argument specifies the target path,

<target_path>] where you want the compiled libraries and modelsim.ini
file to be located. This argument is optional, and the
default target path is the current folder. NOTES: (1) This
argument is recommended if the current folder is tthe
Radiant software's startup (binary) folder, or if the
current folder is write-protected. (2) If <target_path> has
spaces, then it must be surrounded by " ". Do not use { }.

Examples

This section illustrates and describes a few examples of Simulation Libraries

Compilation Tcl command.

Example 1

The following command will compile all the Lattice FPGA libraries for Verilog
simulation, and place them under the folder specified by -target_path. The
path to Modelsim is specified by -sim_path.
tclsh <c:/lscc/radiant/1.0/>/cae_library/simulation/script/
cmpl_libs.tcl -sim_path C:/modeltech64_10.0c/win64 -target_path
c:/mti_libs

See Also
 Command Line Program Overview

Running HDL Encryption from the

Command Line
Radiant software allows you to encrypt the individual HDL source files.

The tool supports encryption of Verilog HDL and VHDL files. Per command’s
execution, single source file is encrypted.

The HDL file can be partially or fully encrypted depending on pragmas’

placements within the HDL file. To learn more about pragmas’ placements,
see Defining Pragmas.

Running HDL Encryption

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Before running the utility, you need to annotate the HDL file with the
appropriate pragmas. Additionally, you may need to create a key file
containing an encryption key. To view the key file’s proper formating, see Key
File.

Command Line Syntax

encrypt_hdl [-k <keyfile>] [-l language]
[-o <output_file>] [-comment <comment>] <input_HDL_file>

Encryption Option The table below contains descriptions of all valid

options for HDL encryption.

Table 8: Encryption Command Line Options

Option Description

-h(elp) Print command help message.

-k <keyfile> A key repository file. Depending on the location of the key, this
option is required or optional.
 If the HDL source file contains no pragma, the key file is
required. The tool encrypts the entire HDL file using all key
sets declared in the key file.
 If the HDL source file contains only begin and end pragmas
and no key pragmas, the key file is required. The tool
encrypts the section between begin and end using all key
sets declared in the key file.
 If the HDL source file contains the proper key pragma,
key_keyowner, key_keyname, but the key file is missing the
provided key_public_key, the tool fetches the first public key
string matching the key_keyowner and key_keyname
requirement in the key file
If the HDL source file contains the proper definition of key, this
option is not required.
NOTE: If the same key name is defined in both, HDL source file
and key.txt file, the key defined in HDL source file has a
precedence.

-l <language> Directive language, vhdl or verilog (default).

-o <output_file> An encrypted HDL file. This is an optional field. If not defined

during the encryption, the tool generates a new output file
<input_file_name>_enc.v.

<input> Input Verilog or VHDL file.

-comment Additional comment.

<comment>

Examples

This section illustrates and describes a few examples of HDL encryption using
Tcl command.

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Example1:

This example shows a successful encryption of HDL file with default options.
It is assumed that key is properly defined in HDL file. Since output file name
was not specified, the tool generates an output file <file_name>_enc.v in the
same directory as the location of the input file.

Example2:

This example shows a successful encryption of HDL file by generating a new

output file.

Example3:

This example shows unsuccessful HDL encryption due to a missing key file.
To correct this issue, the user must either define the appropriate key file
key.txt or annotated the HDL file with appropriate pragmas. To correct the
issue, define the key either in key.txt file or directly in HDL source file.

NOTE
A key is always required in the encryption tool while key file is optional. If the
complete key: key_keyowner, key_keyname, key_method, and
key_public_key, is defined within HDL source file, key file is not required.

For specific steps and information on how to encrypt HDL files in the Radiant
software, refer to the following section in the Radiant Software Help: User
Guides > Securing the Design.

Defining Pragmas
Pragmas are used to specify the portion of the HDL source file that must be
encrypted. Pragma’ definition is compliant with IEEE 1735-2014 V1 standard.

Pragma syntax in Verilog HDL file:

‘pragma protect <pragma’s option>

Pragma synax in VHDL file:

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‘protect <pragma’s option>

Table 9: List of available Pragma Options

Name Available Values Description

version 1 (default) Specifies the current Radiant software encryption version.

author string Specifies the file creator.

author_info string Additional information you would like to include in file.

encoding base64 The output format of processed data.

begin The start point for data obfuscation.

end The end point for data obfuscation.

key_keyowner string The key creator.

key_keyname string The RSA key name to specify the private key.

key_method rsa The cryptographic algorithm used for key obfuscation.

key_public_key The RSA public key file name.

data_method aes128-cbc The AES encryption data method.

aes256-cbc (default)

To encrypt HDL source file, encryption version, encoding type, and key
specific pragmas must be defined in the HDL source file by HDL designer;
only the content within the pragmas is encrypted.

NOTE
Multiple key sets can be declared in a single key file.

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Example of Verilog source file marked with Pragmas:

The encrypted file may contain multiple encrypted key sets.

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Example of encrypted Verilog file:

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Example of VHDL source file marked by Pragmas:

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Example of encrypted VHDL file:

See Also
 Running HDL Encryption from the Command Line
 Key File

Key File
The key repository file defines the cryptographic public key used for RSA
encryption. In Radiant software, the key file contains Lattice public key.
Additionally, it may contain some of the common EDA vendors public keys.

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The Lattice public key file key.txt is located at <Radiant_installed_directory>/

ispfpga/data/ folder. Aside of Lattice public key, the current version contains
the public key for Synopsys, Aldec, and Cadence.

NOTE
If using Synplify Pro synthesis tool, both, the Lattice Public Key and the Synplify Pro
Public Key must be defined in the key file. The Synplify Pro Public Key is used during
the synthesis step to decrypt an encrypted design. The Lattice Public Key is used
during the post-synthesis flow to decrypt an encrypted design.

A key file must contain properly declared pragmas such as key_keyowner,

key_keyname, key_method, and key_public_key for each of the specified
keys. The key value follows the key_public_key pragma.

The key file typically also contains the data_method pragma. It defines the
algorithm used in data block encryption of HDL source file.

Example of a Key File:

See Also
 Running HDL Encryption from the Command Line
 Defining Pragmas

Running Synthesis from the Command

Line
The Lattice Synthesis command tool allows you to synthesize Verilog and
VHDL HDL source files into netlists for design entry into the Radiant software
environment. Based on your strategy settings you specify in the Radiant
software, a synthesis project (.synproj) file is created and then used by
synthesis using the -f option. The Radiant software translates strategy options
into command line options described in this topic.

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Verilog source files are passed to the program using the -ver option and
VHDL source files are passed using the -vhd option. For mixed language
designs the language type is automatically determined by synthesis based on
the top module of the design. For IP design, you must also specify IP location
(-ip_dir), IP core name (-corename), and encrypted RTL file name (-
ertl_file).

Subjects included in this topic:

 Running Synthesis
 Command Line Syntax
 SYNTHESIS Options
 Examples

Running Synthesis Synthesis will convert your input netlist (.v) file into a
structural Verilog file that is used for the remaining mapping process.
 To run synthesis, type synthesis on the command line with valid options.
A sample of a typical synthesis command would be as follows:

There are many command line options that give you control over the way
synthesis processes the output file. Please refer to the rest of the subjects in
this topic for more details. See examples.

Command Line Syntax synthesis [-a <arch>] [-p <device>] [-sp

<performance_grade>] [-t <package_name>] [{-path <searchpath>}] [-top
<top_module_name>] [-ver {<verilog_file.v>}] [-lib <libname>] [-vhd
{<vhdl_file.vhd/vhdl>}] [-udb <udb_file.udb>] [-hdl_param < param_name
param_value >] [-vh2008] [-optimization_goal <area | timing | balanced
(default)>] [-force_gsr <auto(default) | yes | no>] [-ramstyle <auto(default) |
distributed | block_ram(EBR) | registers>] [-romstyle <auto(default) | logic |
EBR>] [-output_edif <filename.edf>] [-output_hdl <filename.v>] [-sdc
<sdc_file.ldc>] [-logfile <synthesis_logfile>] [-frequency <target_frequency
(default 200.0MHz (ICE40))>] [-max_fanout <max_fanout (default 1000)>] [-
bram_utilization <bram_utilization (default 100%)>] [-use_dsp
<0|1(default)>] [-dsp_utilization <dsp_utilization (default 100%)>][-
fsm_encoding_style <auto(default) | one-hot | gray | binary>] [-
resolve_mixed_drivers <0(default)|1>] [-fix_gated_clocks <0|1(default)] [-
use_carry_chain <0|1(default)>] [-carry_chain_length <chain_length>] [-
use_io_insertion <0|1(default)>] [-use_io_reg <0|1|auto(default)>] [-
resource_sharing <0|1(default)>] [-propagate_constants <0|1(default)>] [-
remove_duplicate_regs <0|1(default)>] [-loop_limit <max_loop_iter_cnt
(default 1950)>] [-twr_paths <timing_path_cnt>] [-dt] [-comp] [-syn] [-ifd] [-f
<project_file_name>]

Synthesis Options

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The table below contains descriptions of all valid options for synthesis.

Table 10:
Table 11: Command Line Options
Option Description

-a <arch> Sets the FPGA architecture. This synthesis option must

be specified and if the value is set to any unsupported
FPGA device architecture the command will fail.

-p <device> Specifies the device type for the architecture (optional).

-sp <performance_grade> Sets the device performance speed grade. If no

performance grade specified, default performance value
is used.

-f <proj_file_name> Specifies the synthesis project file name (.synproj). The

project file can be edited by the user to contain all
desired command line options.

-t <package_name> Specifies the package type of the device.

-path <searchpath> Add searchpath for Verilog “include” files (optional).

-top <top_module_name> Name of top module (optional, but better to have to

avoid ambiguity).

-lib <lib_name> Name of VHDL library (optional).

-vhd <vhdl_file.vhd/vhdl> Names of VHDL design files (must have, if language is

VHDL or mixed language).

-ver <verilog_file.v> Names of Verilog design files (must have, if language is

Verilog, or mixed language).

-sver Names of SystemVerilog design files (must have, if

<systemverilog_file.sv> language is SystemVerilog or mixed language).

-hdl_param Allows you to override HDL parameter pairs in the

<param_name design file.
param_value>

-optimization_goal <area The synthesis tool allows you to choose among the
| timing (default)> following optimization options:
 balanced balances the levels of logic.

 area optimizes the design for area by reducing the

total amount of logic used for design implementation.
 timing optimizes the design for timing.

The default setting depends on the device type. Smaller

devices, such as ice40tp default to balanced.

-force_gsr <no(default) | Enables (yes) or disables (no) forced use of the global
yes> set/reset routing resources. When the value is auto, the
synthesis tool decides whether to use the global set/
reset resources.

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Table 10:
Table 11: Command Line Options
Option Description

-ramstyle <auto(default) | Sets the type of random access memory globally to

distributed | distributed, embedded block RAM, or registers.The
block_ram(EBR) | default is auto which attempts to determine the best
registers> implementation, that is, synthesis tool will map to
technology RAM resources (EBR/Distributed) based on
the resource availability.
This option will apply a syn_ramstyle attribute globally in
the source to a module or to a RAM instance. To turn off
RAM inference, set its value to registers.
 registers causes an inferred RAM to be mapped to
registers (flip-flops and logic) rather than the
technology-specific RAM resources.
 distributed causes the RAM to be implemented
using the distributed RAM or PFU resources.
 block_ram (EBR) causes the RAM to be
implemented using the dedicated RAM resources. If
your RAM resources are limited, for whatever
reason, you can map additional RAMs to registers
instead of the dedicated or distributed RAM
resources using this attribute.
 no_rw_check (Certain technologies only). You
cannot specify this value alone. Without
no_rw_check, the synthesis tool inserts bypass logic
around the RAM to prevent the mismatch. If you
know your design does not read and write to the
same address simultaneously, use no_rw_check to
eliminate bypass logic. Use this value only when you
cannot simultaneously read and write to the same
RAM location and you want to minimize overhead
logic.

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Table 10:
Table 11: Command Line Options
Option Description

-romstyle <auto (default) | Allows you to globally implement ROM architectures

logic | EBR> using dedicated, distributed ROM, or a combination of
the two (auto). This applies the syn_romstyle attribute
globally to the design by adding the attribute to the
module or entity. You can also specify this attribute on a
single module or ROM instance.
Specifying a syn_romstyle attribute globally or on a
module or ROM instance with a value of:
 auto allows the synthesis tool to choose the best
implementation to meet the design requirements for
performance, size, etc.
 EBR causes the ROM to be mapped to dedicated
EBR block resources. ROM address or data should
be registered to map it to an EBR block. If your ROM
resources are limited, for whatever reason, you can
map additional ROM to registers instead of the
dedicated or distributed RAM resources using this
attribute.
Infer ROM architectures using a CASE statement in
your code. For the synthesis tool to implement a ROM,
at least half of the available addresses in the CASE
statement must be assigned a value. For example,
consider a ROM with six address bits (64 unique
addresses). The case statement for this ROM must
specify values for at least 32 of the available addresses.

-output_edif Specifies the name of the output EDIF netlist file.

<filename.edf>

-output_hdl <filename.v> Specifies the name of the output Verilog netlist file.

-sdc <sdc_file.ldc> Specifies a Lattice design constraint (.ldc) file input.

-loop_limit Specifies the iteration limits for “for” and “while” loops in
<max_loop_iter_cnt the user RTL for loops that have the loop index as a
(default 1950)> variable and not a constant.
The higher the loop_limit, the longer the run time. Also,
for some designs, a higher loop limit may cause stack
overflow during some of the optimizations during
compile/synthesis.
The default value is 1950. Setting a higher value may
cause stack overflow during some of the optimizations
during synthesis.

-logfile Specifies the name of the synthesis log file in ASCII

<synthesis_logfile> format. If you do not specify a name, synthesis will
output a file named synthesis.log by default.

-frequency Specifies the target frequency setting. Default frequency

<target_frequency (default value is 200.0 MHz.
200.0MHz (ICE40))>

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Table 10:
Table 11: Command Line Options
Option Description

-max_fanout Specifies maximum global fanout limit to the entire

<max_fanout (default design at the top level. Default value is 1000 fanouts.
1000)>

-bram_utilization Specifies block RAM utilization target setting in percent

<bram_utilization (default of total vacant sites. Default is 100 percent.
100%)>

-use_dsp <0|1(default)> Specifies how DSP modules are implemented and

allows DSP inference.

-dsp_utilization Specifies the percentage of DSP that is allowed to be

<dsp_utilization (default used.
100%)>

-mux_style <auto(default) Specifies the MUX style setting, which controls the way
| pfu_mux | L6Mux_single | the macrogenerator implements the multiplexer macros.
L6Mux_multiple>
Valid options are auto, L6Mux Multiple, L6Mux Single,
and PFU Mux. The default value is auto, meaning that
the tool looks for the best implementation.

-fsm_encoding_style Specifies One-Hot, Gray, or Binary style. The -

<auto(default) | one-hot | fsm_encoding_style. Allows the user to determine which
gray | binary> style is faster based on specific design implementation.
Valid options are auto, one-hot, gray, and binary. The
default value is auto, meaning that the tool looks for the
best implementation.

-use_carry_chain Turns on (1) or off (0) carry chain implementation for

<0|1(default)> adders. The 1 or true setting is the default.

-carry_chain_length Specifies the maximum length of the carry chain.

<chain_length>

-use_io_insertion Specifies the use of I/O insertion. The 1 or true setting is

<0|1(default)> the default.

-use_io_reg Packs registers into I/O pad cells based on timing

<0|1|auto(default)> requirements for the target Lattice families. The value 1
enables and 0 disables (default) register packing. This
applies it globally forcing the synthesis tool to pack all
input, output, and I/O registers into I/O pad cells.
NOTE: You can place the syn_useioff attribute on an
individual register or port. When applied to a register, the
synthesis tool packs the register into the pad cell, and
when applied to a port, packs all registers attached to
the port into the pad cell.
The syn_useioff attribute can be set on a:
 top-level port

 register driving the top-level port

 lower-level port, only if the register is specified as

part of the port declaration

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Table 10:
Table 11: Command Line Options
Option Description

-resource_sharing Specifies the resource sharing option. The 1 or true

<0|1(default)> setting is the default.

-propagate_constants Prevents sequential optimization such as constant

<0|1(default)> propagation, inverter push-through, and FSM extraction.
The 1 or true setting is the default.

-remove_duplicate_regs Specifies the removal of duplicate registers. The 1 or

<0|1(default)> true setting is the default.

-twr_paths Specifies the number of critical paths.

<timing_path_cnt>

-dt Disables the hardware evaluation capability. (This option

is for internal use only.)

-comp Indicates HDL compilation only without synthesis. (This

option is for internal use only.)

-syn Allows you to synthesize without HDL compilation.

Reads the .db file. (This option is for internal use only.)

-udb <udb_file.udb> Writes UDB output.

-ifd Sets option to dump intermediate files. If you run the tool
with this option, it will dump about 20 intermediate
encrypted Verilog files. If you supply Lattice with these
files, they can be decrypted and analyzed for problems.
This option is good to for analyzing simulation issues.

-fix_gated_clocks Allows you to enable/disable gated clock optimization.

<0|1(default)> By default, the option is enabled.

-vh2008 Enables VHDL 2008 support.

Examples

The following are examples of synthesis command lines and their respective
description:

synthesis -a "ice40tp" -p itpa08 -t SG48 -sp "6" -mux_style Auto

-use_io_insertion 1

-sdc "C:/my_radiant_tutorial/impl1/impl1.ldc"

-path "C:/lscc/radiant/1.0/ispfpga/ice40tp/data" "C:/my_radiant_tutorial/impl1"

"C:/my_radiant_tutorial"

-ver "C:/my_radiant_tutorial/impl1/source/LED_control.v"

"C:/my_radiant_tutorial/impl1/source/spi_gpio.v"

"C:/my_radiant_tutorial/impl1/source/spi_gui_led_top.v"

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-path "C:/my_radiant_tutorial"

-top spi_gui_led_top

-output_hdl "LEDtest_impl1.vm"

See Also
 Command Line Program Overview

Running Postsyn from the Command

Line
The Postsyn process converts synthesized VM and integrates IPs into a
completed design in UDB format for the remaining mapping process.

Command Line Syntax

postsyn [-w] [-a <architecture>] [-p <device>] [-t <package>]
[-sp <performance>] [-oc <operating_condition>] [-ldc
<ldc_file>] [-iplist <iplist_file>] [-macro <macro_list_file>]
[-gui] [-msgset <msgtypefile>] [-verbose] [-o <output.udb>] [-
keeprtl] [-top] [-cont_on_sdc_err] <input.vm>

Table 12:
Option Description

-h(elp) Print command help message.

-w Overwrite output file.

-a Target architecture name.

-p Target device name.

-t Target package name.

-sp Target performance grade.

-oc Target operating condition: commercial | industrial |

automotive.

-ldc Load LDC file.

-iplist Load IP list file.

-macro Load list file if any macro is used in the design.

-o Output UDB file.

-keeprtl Keep RTL view if it exists in UDB file.

-cont_on_sdc_err Continue on SDC error instead of exit.

-verbose Print more detailed messages.

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Table 12:
Option Description

-top Indicate that the input is for the top design.

<input.vm> Input structural Verilog file.

See Also
 Command Line Program Overview

Running MAP from the Command Line

The Map Design process in the Radiant software environment can also be
run through the command line using the map program. The map program
takes an input database (.udb) file and converts this design represented as a
network of device-independent components (e.g., gates and flip-flops) into a
network of device-specific components (e.g., PFUs, PFFs, and EBRs) or
configurable logic blocks in the form of a Unified Database (.udb) file.

Subjects included in this topic:

 Running MAP
 Command Line Syntax
 MAP Options
 Examples

Running MAP

MAP uses the database (.udb) file that was the output of the Synthesis
process and outputs a mapped Unified Database (.udb) file with constraints
embedded.
 To run MAP, type map on the command line with, at minimum, the
required options to describe your target technology (i.e., architecture,
device, package, and peformance grade), the input .udb along with the
input .ldc file. The output .udb file specified by the -o option. That
additional physical constraint file (*.pdc) can be applied optionally. A
sample of a typical MAP command would be as follows:
map counter_impl1_syn.udb impl1.pdc -o counter_impl1.udb

Note
The -a (architecture) option is not necessary when you supply the part number with the
-p option. There is also no need to specify the constraint file here, but if you do, it must
be specified after the input .udb file name. The constraint file automatically takes the
name “output” in this case, which is the name given to the output .udb file. If the output
file was not specified with the -o option as shown in the above case, map would place
a file named input.udb into the current working directory, taking the name of the input
file. If you specify the input.ldc file and it is not there, map will error out.

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There are many command line options that give you control over the way
MAP processes the output file. Please refer to the rest of the subjects in this
topic for more details.

Command Line Syntax

map [ -h <arch> ] <infile[.udb]> [<options>]

MAP Options

The table below contains descriptions of all valid options for MAP.

Table 13: MAP Command Line Options

Option Description

-h <arch> Displays all of the available MAP command options

for mapping to the specified architecture.

<infile[.udb]> Specifies the output design file name in .udb format.

The .udb extension is optional.

-help Print usage.

-inferGSR GSR inferencing if applicable.

-o <name[.udb]> Optional output design file (.udb).

-mp <name[.mrp]> Optional report file (.mrp).

-xref_sig Report signal cross reference for renamed signals.

-xref_sym Report symbol cross reference for renamed

symbols.

-hierrpt Print out hierarchical resource usage in .hrr file.

-cont_on_sdc_err Ignore Constraint errors.

-u Unclip unused instances.

Examples

Following are some examples of MAP command lines and a description of

what each does.

Example 1

The following command maps an input database file named mapped.udb and
outputs a mapped Unified Database file named mapped.udb.

map counter_impl1_syn.udb impl1.pdc -o counter_impl1.udb

See Also
 Command Line Data Flow
 Command Line Program Overview

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Running PAR from the Command Line

The Place & Route Design process in the Radiant software environment can
also be run through the command line using the par program. The par
program takes an input mapped Unified Database (.udb) file and further
places and routes the design, assigning locations of physical components on
the device and adding the inter-connectivity, outputting a placed and routed
.udb file.

The Implementation Engine multi-tasking option available in Linux is

explained in detail here because the option is not available for PCs.

Subjects included in this topic:

 Running PAR
 Command Line Syntax
 General Options
 Placement Options
 Routing Options
 PAR Explorer (-exp) Options
 Examples
 PAR Multi-Tasking Options

Running PAR

PAR uses your mapped Unified Database (.udb) file that were the outputs of
the Map Design process or the map program. With these inputs, par outputs
a new placed-and-routed .udb file, a PAR report (.par) file, and a PAD
(specification (.pad) file that contains I/O placement information.
 To run PAR, type par on the command line with at minimum, the name of
the input .udb file and the desired name of the output .udb file. Design
constraints from previous stages are automatically embedded in the input
.udb file, however the par program can accept additional constraints with
either a .pdc or .sdc file. A sample of a basic PAR command would be as
follows:

par input.udb output.udb

There are many command line options that give you control over PAR. Please
refer to the rest of the subjects in this topic for more details.

Command Line Syntax

par [-w] [-n <iterations:0,100>] [-t <iteration:0,100>] [-stopzero] [-s

<savecount:0,100>] [-m <nodelistfile>] [-cores <number of cores>] [-r ] [-k] [-p
] [-x] [-pack <density:0,100>] [-sp <setupspeedgrade>] [-hsp
<holdspeedgrade>] [-dh] [-hos] [-sort <method>] <infile> <outfile> [<pdcfile>]

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Note
All filenames without special switches must be in the order <infile> <outfile> <pdcfile>.
Options may exist in any order.

General Options

Table 14: General PAR Command Line Options

Option Description

-f Read par command line arguments and switches

from file.

-w Overwrite. Allows overwrite of an existing file

(including input file).

-n Number of iterations (seeds). Use "-n 0" to run until

fully routed and a timing score of zero is achieved.
Default: 1.

-t Start at this placer cost table entry. Default

is 1.

-stopzero Stop running iterations once a timing score of zero is

achieved.

-s Save "n" best results for this run. Default: Save All.

-m Multi task par run. File "<node list file>", contains a

list of node names to run the jobs on.

-cores Run multiple threads on the local machine. You can

specify "<number of cores>" to run the jobs. For
cases when the user specifies both -cores and -m
with a valid node list file, PAR should apply both
settings (merge). If the user repeats the host
machine in the node list file, the settings in the node
list file take precedence over the setting in -cores (for
backwards compatibility).

-p Don't run placement.

-r Don't run router.

-k Keep existing routing in input UDB file.

Note: only meaningful when used with -p.

-x Ignore timing constraints.

-pack Set the packing density parameter.

Default: auto.

-sp Change performance grade for setup optimization.

Default: Keep current performance grade.

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Table 14: General PAR Command Line Options

Option Description

-hsp Change performance grade for hold optimization.

Default: M.

-dh Disable hold timing correction.

-hos Prioritize hold timing correction over setup

performance.

-sort Set the sorting method for ranking multiple

iterations. <method> "c" sorts by cumulative slack,
"w" sorts by worst slack.
Default: c.

<infile> Name of input UDB file.

<outfile> Name of output UDB file.

Table 15: PAR Placement Command Line Options

Option Description

<pdcfile> Name of optional constraint file.

Note: the contents of <pdcfile> will overwrite all
constraints saved in the input UDB file <infile>.

Examples Following are a few examples of PAR command lines and a

description of what each does.

Example 1

The following command places and routes the design in the file input.udb and
writes the placed and routed design to output.udb.

par input.udb output.udb

Example 2

The following command runs 20 place and route iterations. The iterations
begin at cost table entry 5. Only the best 3 output design files are saved.

par -n 20 -t 5 -s 3 input.udb output.udb

Example 3

(Lattice FPGAs only) This is an example of par using the -io switch to
generate .udb files that contain only I/O for viewing in the PAD Specification
file for adjustment of ldc_set_location constraints for optimal I/O placement.
You can display I/O placement assignments in the Radiant Spreadsheet View
and choosing View > Display IO Placement.

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par -io -w lev1bist.udb lev1bist_io.udb

Using the PAR Multi-Tasking (-m) Option

This section provides information about environment setup, node list file
creation, and step-by-step instructions for running the PAR Multi-tasking (-m)
option from the command line. The PAR -m option allows you to use multiple
machines (nodes) that are networked together for a multi-run PAR job,
significantly reducing the total amount of time for completion. Before the multi-
tasking option was developed, PAR could only run multiple jobs in a linear or
serial fashion. The total time required to complete PAR was equal to the
amount of time it took for each of the PAR jobs to run.

For example, the PAR command:

par -n 10 mydesign.udb output.udb

tells PAR to run 10 place and route passes (-n 10). It runs each of the 10 jobs
consecutively, generating an output .udb file for each job, i.e., output_par.dir/
5_1.udb, output_par.dir/5_2.udb, etc. If each job takes approximately one
hour, then the run takes approximately 10 hours.

Suppose, however, that you have five nodes available. The PAR Multi-tasking
option allows you to use all five nodes at the same time, dramatically reducing
the time required for all ten jobs.

To run the PAR multi-tasking option from the command line:

1. First generate a file containing a list of the node names, one per line as in
the following example:
# This file contains a profile node listing for a PAR multi
# tasking job.
[machine1]
SYSTEM = linux
CORENUM = 2
[machine2]
SYSTEM = linux
CORENUM = 2
Env = /home/user/setup_multipar.lin
Workdir = /home/user/myworkdir

You must use the format above for the node list file and fill in all required
parameters. Parameters are case insensitive.The node or machine
names are given in square brackets on a single line.
The System parameter can take linux or pc values depending upon your
platform. However, the PC value cannot be used with Linux because it is
not possible to create a multiple computer farm with PCs. Corenum refers
to the number of CPU cores available. Setting it to zero will disable the
node from being used. Setting it to a greater number than the actual
number of CPUs will cause PAR to run jobs on the same CPU lengthening
the runtime.
The Env parameter refers to a remote environment setup file to be
executed before PAR is started on the remote machine. This is optional. If

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the remote machine is already configured with the proper environment,

this line can be omitted. To test to see if the remote environment is
responsive to PAR commands, run the following:
ssh <remote_machine> par <par_option>

See the System Requirements section below for details on this

parameter.
Workdir is the absolute path to the physical working directory location on
the remote machine where PAR should be run. This item is also optional.
If an account automatically changes to the proper directory after login, this
line can be omitted. To test the remote directory, run the following,
ssh <remote_machine> ls <udb_file>

If the design can be found then the current directory is already available.
2. Now run the job from the command line as follows:
par -m nodefile_name -n 10 mydesign.udb output.udb

This runs the following jobs on the nodes specified.

Starting job 5_1 on node NODE1 at ...
Starting job 5_2 on node NODE2 at ...
Starting job 5_3 on node NODE3 at ...
Starting job 5_4 on node NODE4 at ...
Starting job 5_5 on node NODE5 at ...
As the jobs finish, the remaining jobs start on the nodes until all 10 jobs
are complete. Since each job takes approximately one hour, all 10 jobs
will complete in approximately two hours.

Note
If you attempt to use the multi-tasking option and you have specified only one
placement iteration, PAR will disregard the -m option from the command and run
the job in normal PAR mode. In this case you will see the following message:
WARNING - par: Multi task par not needed for this job. -m switch will be ignored.

System Requirements ssh must be located through the PATH variable. On

Linux, the utility program’s secure shell (ssh) and secure shell daemon
(sshd) are used to spawn and listen for the job requests.

The executables required on the machines defined in the node list file are as
follows:
 /bin/sh
 par (must be located through the PATH variable)

Required environment variable on local and remote machines are as follows:

 FOUNDRY (points at FOUNDRY directory structure must be a path
accessible to both the machine from which the Implementation Engine is
run and the node)
 LM_LICENSE_FILE (points to the security license server nodes)

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 LD_LIBRARY_PATH (supports par path for shared libraries must be a

path accessible to both the machine from which the Implementation
Engine is run and the node)

To determine if everything is set up correctly, you can run the ssh command
to the nodes to be used.

Type the following:

ssh <machine_name> /bin/sh -c par

If you get the usage message back on your screen, everything is set correctly.
Note that depending upon your setup, this check my not work even though
your status is fine.

If you have to set up your remote environment with the proper environment
variables, you must create a remote shell environment setup file. An example
of an ASCII file used to setup the remote shell environment would be as
follows for ksh users:
export FOUNDRY=<install_directory>/ispfpga/bin/lin64
export PATH=$FOUNDRY/bin/lin64:$PATH
export LD_LIBRARY_PATH=$FOUNDRY/bin/lin:$LD_LIBRARY_PATH
64

For csh users, you would use the setenv command.

Screen Output

When PAR is running multiple jobs and is not in multi-tasking mode, output
from PAR is displayed on the screen as the jobs run. When PAR is running
multiple jobs in multi-tasking mode, you only see information regarding the
current status of the feature.

For example, when the job above is executed, the following screen output
would be generated:
Starting job 5_1 on node NODE1
Starting job 5_2 on node NODE2
Starting job 5_3 on node NODE3
Starting job 5_4 on node NODE4
Starting job 5_5 on node NODE5

When one of the jobs finishes, this message will appear:

Finished job 5_3 on node NODE3

These messages continue until there are no jobs left to run.

See Also
 User Guides > Implementing the Design in the Radiant Software Help
 Command Line Data Flow
 Command Line Program Overview

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Running Timing from the Command

Line
The MAP Timing and Place & Route Timing processes in the Radiant
software environment can also be run through the command line using the
timing program. Timing can be run on designs using the placed and routed
Unified Design Database (.udb) and associated timing constraints specified in
the design's (.ldc,.fdc, .sdc or .pdc) file or device constraints extracted from
the design. Using these input files, timing provides static timing analysis and
outputs a timing report file (.tw1/.twr).

Timing checks the delays in the Unified Design Database (.udb) file against
your timing constraints. If delays are exceeded, Timing issues the appropriate
timing error. See “Implementing the Design” in the Radiant Software Help and
associated topics for more information.

Subjects included in this topic:

 Running Timing
 Command Line Syntax
 Timing Options
 Examples

Running Timing

Timing uses your input mapped or placed-and-routed Unified Design

Database (.udb) file and associated constraint file to create a Timing Report.
 To run Timing, type timing on the command line with, at minimum, the
names of your input .udb and sdc files to output a timing report (.twr) file.
A sample of a typical Timing command would be as follows:
timing design.udb (constraint is embedded in udb)

Note
The above command automatically generates the report file named design.twr which is
based on the name of the .udb file.

There are several command line options that give you control over the way
Timing generates timing reports for analysis. Please refer to the rest of the
subjects in this topic for more details. See Examples.

Command Line Syntax timing <udb file name> [ -sdc <sdc file name> ]
[ -hld | -sethld ] [ -o <output file name> ] [ -v <integer> ] [-endpoints
<integer>] [-help]

Timing Options

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The following tables contain descriptions of all valid options for Timing.

Table 16: Compulsory Timing Command Line Options

Compulsory Option Description

-db-file arg design database file name.

Table 17: Optional Timing Command Line Options

Optional Option Description

-endpoints arg (=10) number of end points.

-u arg (=10) number of unconstrained end points printed in the

table.

-ports arg (=10) number of top ports printed in the table.

-help print the usage and exit.

-hld hold report only.

-sp arg (=None) Setup speed grade.

-hsp arg (=M) Hold speed grade.

-rpt-file arg timing report file name.

-o arg timing report file name.

-alt_report Diamond like report.

-report_sdc Parsed file appears in report file.

-sdc-file arg sdc file name.

-sethld both setup and hold report.

-v arg (=10) number of paths per constraint.

-time_through_async Timer will time through async resets.

-iotime compute the input setup/hold and clock to output

delays of the FPGA.

-io_allspeed Get worst IO results for all speed grades.

-pwrprd Output clock information for PowerCalculator.

-nperend arg (=1) Number of paths per end point.

-html HTML format report.

-gui Call from GUI.

-msg arg Message log file.

-msgset arg Message setting.

-io_allspeed Get worst IO results for all speed grades.

-dump_cdc Dump CDC registers.

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Table 17: Optional Timing Command Line Options

Optional Option Description

-false_covers False path improves coverage

-dump_uncovered Dump load pins of connections that are not covered.

Examples

Following are a few examples of Timing command lines and a description of

what each does.

Example 1

The following command verifies the timing characteristics of the design

named design1.udb, generating a summary timing report. Timing constraints
contained in the file group1.prf are the timing constraints for the design. This
generates the report file design1.twr.

timing design1.udb (constraint is embedded in udb)

Example 2

The following command produces a file listing all delay characteristics for the
design named design1.udb. Timing constraints contained in the file group1.prf
are the timing constraints for the design. The file output.twr is the name of the
verbose report file.

timing -v design1.udb -o output.twr

Example 3

The following command analyzes the file design1.udb and reports on the
three worst errors for each constraint embedded in design1.udb and in
additional timing constraint file (e.g. test.ldc). The report is called design1.twr.

timing -e 3 -sdc-file test.ldc design1.udb

Example 4

The following command analyzes the file design1.udb and produces a

verbose report to check on hold times on any timing constraints embedded in
design1.udb. With the output report file name unspecified here, a file using
the root name of the .udb file (i.e., design1.twr) will be output by default.

timing -v -hld design1.udb

Example 5

The following command analyzes the file design1.udb and produces a

summary timing report to check on both setup and hold times on any timing
constraints embedded in design1.udb. With the output report file name

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unspecified here, a file using the root name of the .udb file (i.e., design1.twr)
will be output by default.

timing -sethld design1.udb

See Also
 Command Line Program Overview
 Command Line Data Flow

Running Backannotation from the

Command Line
The Generate Timing Simulation Files process in the Radiant software
environment can also be run through the command line using the backanno
program. The backanno program back-annotates physical information (e.g.,
net delays) to the logical design and then writes out the back-annotated
design in the desired netlist format. Input to backanno is a Unified Database
file (.udb) a mapped and partially or fully placed and/or routed design.

Subjects included in this topic:

 Running Backanno
 Command Line Syntax (Verilog)
 Backanno Options
 Examples

Running Backanno

Backanno uses your input mapped and at least partially placed-and-routed

Unified Database (.udb) file to produce a back-annotated netlist (.v) and
standard delay (.sdf) file. This tool supports all FPGA design architecture
flows. Only Verilog netlist is generated.
 To run backanno, type backanno on the command line with, at minimum,
the name of your input .udb file. A sample of a typical backanno command
would be as follows:
backanno backanno.udb

Note
The above command back annotates backanno.udb and generates a Verilog file
backanno.v and an SDF file backanno.sdf. If the target files already exist, they will not
be overwritten in this case. You would need to specify the -w option to overwrite them.

There are several command line options that give you control over the way
backanno generates back-annotated netlists for simulation. Please refer to
the rest of the subjects in this topic for more details.

Command Line Syntax (Verilog)

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backanno [-w] [-pre <prfx>] [-sp <grade>] [-neg] [-pos ] [-sup] [-min] [-x] [-fc
] [-slice] [-slice0] [-slice1] [-noslice] [-t] [-dis [<del>]] [-m [<limit>]] [-u] [-i] [-
nopur] [-l <libtype>] [-s <separator>] [-o <verilog<<.v>>] [-d <delays[.sdf]>] [-
gui] [-msg <msglogfile>] [-msgset <msgtypefile>] [<udbfile>]

Backanno Options

The table below contains descriptions of all valid options for backanno.

Table 18: Backanno Options

Option Description

-w Overwrite the output files.

-sp <grade> Override performance grade for backannotation.

-pre <prfx> Prefix to add to module name to make them

unique for multi-chip simulation.

-min Override performance grade to minimum timing

for hold check.

-dis <del> Distribute routing delays by splitting the signal

and inserting buffers. <del> is the maximum delay
(in ps) between each buffer (1000ps by default).

-m <limit> Shortens the block names to a given character

limit in terms of some numerical integer value.

-u Add pads for top-level dangling nets.

-neg Negative setup/hold delay support. Without this

option, all negative numbers are set to 0 in SDF.

-pos Write out 0 for negative setup/hold time in SDF for

SC.

-x Generate x for setup/hold timing violation.

-i Create a buffer for each block input that has

interconnection delay.

-nopur Do not write PUR instance in the backannotation

netlist. Instead, user has to instantiate it in a test
bench.

<type> Netlist type to write out.

<libtype> Library element type to use.

<netfile> The name of the output netlist file. The extension

on this file will change depending on which type of
netlist is being written. Use -h <type>, where
<type> is the output netlist type, for more specific
information.

<udb file> Input file '.udb '.

Examples

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Following are a few examples of backanno command lines and a description

of what each does.

Example 1

The following command back annotates design.udb and generates a Verilog

file design.vo and an SDF file design.sdf. If the target files exist, they will be
overwritten.
backanno -w design.udb

Example 2

The following command back annotates design.udb and generates a Verilog

file backanno.vo and an SDF file backanno.sdf. Any signal in the design that
has an interconnection delay greater than 2000 ps (2 ns) will be split and a
series of buffers will be inserted. The maximum interconnection delay
between each buffer would be 2000 ps.
backanno -dis 2000 -o backanno design.udb

Example 3

The following command re-targets backannotation to peformance grade -2,

and puts a buffer at each block input to isolate the interconnection delay (ends
at that input) and the pin to pin delay (starts from that input).
backanno -sp 2 -i design.udb

Example 4

The following command generates Verilog netlist and SDF files without setting
the negative setup/hold delays to 0:
backanno -neg -n verilog design.udb

See Also
 Command Line Program Overview
 Command Line Data Flow

Running Bit Generation from the

Command Line
The Bitstream process in the Radiant software environment can also be run
through the command line using the bit generation (bitgen) program. This
topic provides syntax and option descriptions for usage of the bitgen program
from the command line. The bitgen program takes a fully routed Unified
Database (.udb) file as input and produces a configuration bitstream (bit
images) needed for programming the target device.

Subjects included in this topic:

 Running BITGEN

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 iCE40UP Command Line Syntax

 All devices except iCE40UP Command Line Syntax
 BITGEN Options
 Example 1

Running BITGEN

BITGEN uses your input, fully placed-and-routed Unified Database (.udb) file
to produce bitstream (.bit, .msk, or .rbt) for device configuration.
 To run BITGEN, type bitgen on the command line with, at minimum, the
bitgen command. There is no need to specify the input .udb file if you run
bitgen from the directory where it resides and there is no other .udb
present.

There are several command line options that give you control over the way
BITGEN outputs bitstream for device configuration. Please refer to the rest of
the subjects in this topic for more details.

iCE40UP Command Line Syntax

bitgen [-d] [-b] [-a] [-w] [-noebrinitq1] [-noebrinitq2] [-noebrinitq3] [-

noheader] [-simbitmap] [-nvcm] [-freq <frequency_bit_setting>] [-
spilowpower] [-warmboot ] [-nvcmsecurity] {-g <setting_value>} <infile>
[<outfile>]

All devices except iCE40UP Command Line Syntax

bitgen [-d] [-w] [-m <format>] [-g <opt:val>] [-f <*.t2b>] [-s <*.secproj>] {-site
<seirule>} {-site <seitype>} <infile> [<outfile>]

BITGEN Options

The table below contains descriptions of all valid options for BITGEN.

Note
Many BITGEN options are only available for certain architectures. Please use the
bitgen -h <architecture> help command to see a list of valid bitgen options for the
particular device architecture you are targeting.

Table 19: iCE40UP BITGEN Command Line Options

Option Description

-d Disable DRC.

-b Produce .rbt file (ASCII form of binary).

-a Produce .hex file.

-w Overwrite an existing output file.

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Table 19: iCE40UP BITGEN Command Line Options

Option Description

-freq Can setup different frequency: 0 = slow, 1 = medium, 2

<frequency_bit_setting> = fast.
Depending on the speed of external PROM, this
options adjusts the frequency of the internal oscillator
used by the iCE40UP device during configuration.
This is only applicable when the iCE40UP device is
used in SPI Controller Mode for configuration.

-nvcm Produce NVCM file.

-nvcmsecurity Set security. Ensures that the contents of the Non-

Volatile Configuration Memory (NVCM) are secure and
the configuration data cannot be read out of the
device.

-spilowpower SPI flash low power mode. Places the PROM in low-
power mode after configuration.
This option is applicable only when the iCE40UP
device is used as SPI Controller Mode for
configuration.

-warmboot Enable warm boot. Enables the Warm Boot

functionality, provided the design contains an instance
of the WARMBOOT primitive.

-noheader Don’t include the bitstream header.

-noebrinitq0 Don’t include EBR initialization for quadrant 0.

-noebrinitq1 Don’t include EBR initialization for quadrant 1.

-noebrinitq2 Don’t include EBR initialization for quadrant 2.

-noebrinitq3 Don’t include EBR initialization for quadrant 3.

-g NOPULLUP:ENABLED No IO pullup. Removes the pullup on the unused I/Os,

except Bank 3 I/Os which do not have pullup.

-h <architecture> or -help Display available BITGEN command options for the

<architecture> specified architecture. The bitgen -h command with
no architecture specified will display a list of valid
architectures.

<infile> The input post-PAR design database file (.udb).

<outfile> The output file. If you do not specify an output file,

BITGEN creates one in the input file's directory If you
specify -b, the extension is .rbt. If you specify –a, the
extension is .hex. If you specify –nvcm, the extension
is .nvcm. Otherwise the extension is .bin.
A report (.bgn) file containing all of BITGEN's output is
automatically created under the same directory as the
output file.

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Table 20: BITGEN Command Line Options (all devices except iCE40UP)
Option Description

-d Disable DRC.

-w Overwrite an existing output file.

-m <format> Create "mask" and "readback" files. Valid formats are:

0: Output files in ASCII
1: Output files in binary.

-g <opt:val> Set option to value, options are (First is default):

CfgMode Disable, Flowthrough, Bypass
RamCfg Reset, NoReset
DONEPHASE T3, T2, T1, T0
GOEPHASE T1, T3, T2
GSRPHASE T2, T3, T1
GWEPHASE T2, T3, T1
ES Yes, No.

-f <*.t2b> Load additional command line arguments from a .t2b

file.

-s <*.secproj> Load a bitstream security settings file.

-h <architecture> or -help Display available BITGEN command options for the

<architecture> specified architecture. The bitgen -h command with
no architecture specified will display a list of valid
architectures.

<infile> The input post-PAR design database file (.udb).

<outfile> The output file. If you do not specify an output file,

BITGEN creates one in the input file's directory If you
specify -b, the extension is .rbt. If you specify –a, the
extension is .hex. If you specify –nvcm, the extension
is .nvcm. Otherwise the extension is .bin.
A report (.bgn) file containing all of BITGEN's output is
automatically created under the same directory as the
output file.

Example 1

The following command tells bitgen to overwrite any existing bitstream files
with the -w option, prevents a physical design rule check (DRC) from running
with -d, specifies a raw bits (.rbt) file output with -b. Notice how these three
options can be combined with the -wdb syntax.
bitgen -wdb <design.udb>

Example 2

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There are two command line options to set the SEI Editor tool with the
following examples:
 1-bit Error Injection

bitgen –w <other options> -ebit 1 -sei unused –site

<unused site type> <des>.udb <output file>
where <unused site type> = [PFU | DSP |ANY]

 Unused
bitgen –w -ebit 1 –sei unused –site PFU des.udb
des_partial.bit

 Random
bitgen –w -ebit 1 –sei random - des.udb des_partial.bit

 2-bit Error Injection

bitgen –w <other options> -ebit 2 -sei unused –site

<unused site type> <des>.udb <output file>
where <unused site type> = [PFU | DSP |ANY]

 Unused
bitgen –w -ebit 2 –sei unused –site DSP des.udb
des_partial.bit

bitgen -b -ebit 2 -sei unused -site DSP,DSP < udb design

>
 Random
bitgen –w -ebit 2 –sei random des.udb des_partial.bit

Note
The <other options> option, does not support compressed or encrypted partial
bitstream, and if it includes “-b”, it generates an ASCII bitstream output file.

See Also
 Command Line Program Overview
 Command Line Data Flow

Running Programmer from the

Command Line
You can run Programmer from the command line. The PGRCMD command
uses a keyword preceded by a hyphen for each command line option.

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Running PGRCMD PGRCMD allows you to download data files to an

FPGA device.
 To run PGRCMD, type pgrcmd on the command line with, at minimum,
the pgrcmd command.

There are several command line options that give you control over the way
PGRCMD programs devices. Please refer to the rest of the subjects in this
topic for more details.

Command Line Syntax

The following describes the PGRCMD command line syntax:

pgrcmd [-help] [-infile <input_file_path>] [-logfile <log_file_path>] [-

cabletype <cable>]
-cabletype
lattice [ -portaddress < 0x0378 | 0x0278 | 0x03bc | 0x<custom
address> > ]
usb [ -portaddress < EZUSB-0 | EZUSB-1 | ... | EZUSB-15 > ]
usb2 [ -portaddress < FTUSB-0 | FTUSB-1 | ... | FTUSB-15 > ]
TCK [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10]

PGRCMD Options

The following are PGRCMD options.

Help (Optional)

Option Description

-help or -h Displays the Programmer command line options.

Input File (required)

Option Description

-infile filename.xcf Specifies the chain configuration file (.xcf). If the file path includes spaces, enclose the
path in quotes.

Log File (optional)

Option Description

-logfile logfilename.log Specifies the location of the Programmer log file.

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Cable Type (optional)

Option Description

-cabletype lattice Lattice HW-DLN-3C parallel port programming cable

(default).

-cabletype usb Lattice HW-USBN-2A USB port programming cable.

-cabletype usb2 Lattice FHW-USBN-2B (FTDI) USB programming cable

and any FTDI based demo boards.

Parallel Port Address (optional)

Option Description

-portaddress 0x0378 LPT1 parallel port (default)

-portaddress 0x0278 LPT2 parallel port

-portaddress 0x03BC LPT3 parallel port

-portaddress 0x<custom Custom parallel port address

address>

This option is only valid with parallel port cables.

USB Port Address (optional)

Option Description

-portaddress EZUSB-0 ... HW-USBN-2A USB cable number 0 through 15

EZUSB-15

-portaddress FTUSB-0 ... FTDI based demo board or FTDI USB2 cable
FTUSB-15 number 0 through 15

Default is EZUSB-0 and FTUSB-0. Only valid with the USB port cables.

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FTDI Based Demo Board or Cable Frequency Control (optional)

Option Description

-TCK 0, 1, 2, 3, 4, ,5 ,6 7, 8, 9, 0 = 30 Mhz
10
1 = 15 Mhz (default)
2 = 10 Mhz
3 = 7.5 Mhz
4 = 6 Mhz
5 = 5 Mhz
6 = 4 Mhz
7 = 3 Mhz
8 = 2 Mhz
9 = 1 Mhz
10 = 900 Khz

Calculation formula for USB-2B (2232H FTDI USB host chip): Frequency = 60
MHz / (1 + ClockDivider) *2

Calculation formula for USB-2B (2232D FTDI USB host chip): Frequency = 12
MHz / (1 + ClockDivider) *2

Only applicable for FTDI based demo boards or programming cable.

Return Codes

Code Definition

0 Success

-1 Log file error

-2 Check configuration setup error

-3 Out of memory error

-4 NT driver error

-5 Cable not detected error

-6 Power detection error

-7 Device not valid error

-8 File not found error

-9 File not valid error

-10 Output file error

-11 Verification error

-12 Unsupported operation error

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Code Definition

-13 File name error

-14 File read error

-17 Build SVF file error

-18 Build VME file error

-19 Command line syntax error

Examples

The following is a PGRCMD example.

pgrcmd -infile c:\test.xcf

See Also
 Command Line Data Flow
 Command Line Program Overview

Running the Deployment Tool from the

Command Line
You can run the Deployment Tool from the command line. The DDTCMD
command uses a keyword preceded by a hyphen for each command line
option.

Note
If you use the Deployment Tool GUI, the correct command line for the operation you
are performing will be displayed in the GUI in the “Step 4 of 4 - Generate Deployment”
dialog box. The command line is also recorded in the Deployment Project File (*.ddt).
You can view the Deployment Project File with a text editor and view or copy the
command line.

Subjects included in this topic:

 Running DDTCMD
 Command Line Syntax
 DDTCMD Options
 Examples

Running DDTCMD

DDTCMD allows you to convert data files to other formats for one device at a
time and devices in a chain. DDTCMD can also use the data files it produces
to generate other data file formats.

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 To run DDTCMD, type ddtcmd on the command line with, at minimum,

the ddtcmd command.

There are several command line options that give you control over the way
DDTCMD converts data files. Please refer to the rest of the subjects in this
topic for more details.

Command Line Syntax

The following describes the DDTCMD command line syntax:

<install_path>\ddtcmd
[ -h] |
-oft <-bit | rbt >
[ -dev <Device Name> ]
-if "<Data File Path>"
[ -of "<Data File Path>"]
[ -compress <on | off>]
[ -verifyid <on | off> ]
[ -freq ]
[ -crc <frame | global>]
[ -mirror]
[ -header]
[ -secure <on | off>]
[ -overwriteues on <Hex Value>]
[ -encryption -key hex <Valid Key Value>
-config_mode <slave_scm | slave_pcm | jtag | spi | spim |
master_pcm | slave_spi>]
|
-oft <-int | mot | xtek>
[ -dev <Device Name> ]
-if "<Data File Path>"
[ -of "<Data File Path>"]
[ -compress <on | off>]
[ -verifyid <on | off> ]
[ -freq ]
[ -crc <frame | global>]
[ -mirror]
[ -header]
[ -secure <on | off>]

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[ -overwriteues on <Hex Value>]

[ -encryption -key hex <Valid Key Value>
-config_mode <slave_scm | slave_pcm | jtag | spi | spim |
master_pcm | slave_spi>]
[ -address <hex address>]
[ -fast]
|
-oft -svf
[ -dev <Device Name>]
-if "<Data File Path>"
[ -of "<Data File Path>"]
-op <Operation>
[ -nocomments]
[ -revd]
[ -runtest]
[ -skipverify]
[ -reset]
[-maxdata <8 | 16 | 32 | 64 | 128 | 256> ]
|
-oft -svfchain
-if "<Data File Path>"
[ -of "<Data File Path>"]
[ -nocomments]
[ -revd]
[ -runtest]
[ -skipverify]
[ -reset]
[ -maxdata <8 | 16 | 32 | 64 | 128 | 256>]
|
-oft -stp
[ -dev <Device Name>]
-if "<Data File Path>"
[ -of "<Data File Path>"]
-op <Operation>
[ -nocompress]
[ -print]

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[ -skipverify]
|
-oft -stpchain
-if "<Data File Path>"
[ -of "<Data File Path>"]
[ -nocompress]
[ -print]
[ -skipverify]
|
oft -ate
-if "<Data File Path>"
[ -of "<Data File Path>"]
-type <tst | gr | hp3070 | hp3065 | t1800 | t200>
[ -ispdcd]
[ -skipverify]
[ -headerfile <file path>]
[ -splitfile [ -init] [ -vectors <# vectors/file>] [ -splitatlow]]
|
-oft -fullvme
-if "<Data File Path>"
[ -of "<Data File Path>"]
[ -maxdata <8 | 16 | 32 | 64 | 128 | 256>]
[ -hex]
[ -nocompress]
[ -compact]
[ -fixedpulse]
[ -verifyues]
[ -noheader]
[ -comment]
|
-oft -slimvme
-if "<Data File Path>"
[ -ofa <Algorithm File Path>]
[ -ofd "<Data File Path>"]
[ -nocompress]
[ -hex]

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|
-oft -sspi
-if "<Data File Path>"
[ -ofa <Algorithm File Path>]
[ -ofd "<Data File Path>"]
[ -nocompress]
[ -hex]
[ -op <Operation>]
|
-oft -i2c
-if "<Data File Path>"
[ -ofa <Algorithm File Path>]
[ -ofd "<Data File Path>"]
[ -nocompress]
[ -hex]
[ -op <Operation>]
-address <80 | (User Specified)>
[ -comment]
[ -fixedpulse]
|
-oft -cpu
-if "<Data File Path>"
[ -of "<Data File Path>"]
- type <cpu | c | hex | txt>
[ -verify]
[ -comment]
[ -nocompress]
[ -mirror]
|
-oft -boot
[ -dev <Device Name>]
-golden "<Data File Path>"
-primary "<Data File Path>"
-format <int | mot | xtek>
[ -of "<Data File Path>"]
-flashsize <1 | 2 | 4 | 8 | 16 | 32 | 64 | 128 | 256>

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[ -protect]
[ -mirror]
[ -header]
[ -preamble]
[ -optimize] [ -fast | -dualio | -quad 1]
[ -asc <1 | 2 | 3 | 4 | 5 | 6 | 7 | 8>
-ascfile “<Data File Path>”
[ -ascfile “<Data File Path>”] … [ -ascfile “<Data File Path>”]]
|
-oft -jed
-if “<Data File Path>”
[ -dev <Device Name>]
[ -of “<Data File Path>”]
[ -overwriteues <on "<hex value>" | checksum | disable>]
[ -comment “<Header File Path>”]
[ -encryption -key hex “<valid key value>”]
|
-oft -advanced
[ -dev <Device Name>]
-if “<Data File Path>”
-format <int | mot | xtek>
[ -of “<Data File Path>”]
-flashsize <512 | 1 | 2 | 4 | 8 | 16 | 32 | 64 | 128 | 256 | 513>
[ -mirror]
[ -header]
[ -optimize]
[ -preamble]
[ -userdata <1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
16>
-usermirror
-userfile “<Data File Path>”
-address <hex address value>
[ -userfile “<Data File Path>”
-address <hex address value>] ...
[ -userfile “<Data File Path>”
-address <hex address value>]]

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[ -ice [ -warm <1 | 2 | 3 | 4>]

-patterns <2,3,4>
-bootfile “<Data File Path>”
-address <hex address value>
[ -bootfile “<Data File Path>”
-address <hex address value>] ...
[ -bootfile “<Data File Path>”
-address <hex address value> ]]
[ -fast | -dualio | -quad 1>]
[ -multi <1 | 2 | 3 | 4>
-golden "<Data File Path>"
-altfile “<Data File Path>”
-address <hex address value>
-next <primary | alt1 | alt2 | alt3 | alt4> [
-altfile “<Data File Path>”
-address <hex address value>
-next <primary | alt1 | alt2 | alt3 | alt4>] ...
[-altfile “<Data File Path>”
-address <hex address value>
-next <primary|alt1|alt2|alt3|alt4>]]
|
-oft -merge
-ifdev1 “<Data File Path>”
-ifdev2 “<Data File Path>”
-format <int | mot| xtek>
[ -of “<Data File Path>”]
[ -mergeformat <intelligent | combine>
[ -frequency <freq>]
[ -scoutput <dout | qout>]]
[ -mirror]
[ -header]
|
-oft -bsm
-ifd “<Data File Path>”
-ifb “<BSDL File Path>”
[ -dev <Device Name>]

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[ -of “<Data File Path>”]

[ -convertbidi]

DDTCMD Options

The following are DDTCMD options.

Option Description

-h Displays the Deployment Tool command line usage in the terminal or DOS window.

-oft <File Type> Indicates which file type(s) will be generated.

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Option Description

-bit Generate binary bitstream file.

-dev <Device Name>: Indicates the name of the device (optional). The device name must
be the full device name with the performance grade replaced with two X’s, and minus the
industry rating or the code name.
Example:
LFE3-17EA-XXFN484 (with performance grade replaced with two X's).
The device name will default to the device name in the data file. If a device name cannot
be found in the file, it will return an error unless the name has been given with the -dev
option.
-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes (optional). Default file name is the same name as the input file.
binary bitstream files should end with the *.bit extension.
-compress <on | off>: Specifies compression (optional). Default is off.
-verifyid: On: Include the Verify ID frame. Off: Replaces Verify ID frame with NOOP
(optional). Default is off.
-freq: Specifies the frequency of the master bitstream.
Possible frequencies valid for LatticeEC/P, LatticeECP2/M, LatticeECP3, and LatticeXP/2
devices only are: 2.5, 4.3, 5.4, 6.9, 8.1, 9.2, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, 60,
and 130 MHz. Possible frequencies valid for for MachXO2 and MachXO3L devices only
are: 2.1, 2.5, 3.2, 4.3, 5.5, 7, 8.3, 9.2, 10, 13, 15, 20, 27, 30, 33, 38, 44, 53, 66, 89, and
133 MHz. Possible frequencies valid for for ECP5 devices only are: 2.4, 3.2, 4.1, 4.8, 6.5,
8.2, 9.7, 12.9, 15.5, 16.3, 19.4, 20.7, 25.8, 31, 34.4, 38.8, 44.3, 51.7, 62, 77.5, 103.3, and
155 MHz.
-crc <frame | global>: The “frame” option includes the CRC checking for each data frame.
The "global option disables the frames CRC but still calculates the global CRC at the end
of the configuration data. Default uses the settings of the input file. Valid for ECP5.
LatticeECP2/M, LatticeECP2S/SM, LatticeECP3, MachXO3L, MachXO2, and LatticeXP/2
devices only.
-secure <on | off>: Specifies program security (optional). On: Programs the Security Fuse
(blocks read back). Off: Does not program the Security Fuse (allows read back).Default
uses the settings of the input file.
-overwriteues on: Overwrites (or replaces) the USERCODE value contained in the input
file with the hex value passed in.
Note: The encryption software patch must be installed before using the following -
encryption -key and -config_mode commands.
-encryption -key hex <Valid Key Value>: Encrypts the input file using the -key 128-bit
encryption key.
-config_mode <slave_scm | slave_pcm | jtag | spi | spim | master_pcm | slave_spi>]:
Selects the appropriate configuration mode for the bitstream encryption. Valid for
LatticeECP2S/MS and LatticeECP3 devices only.

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Option Description

-rbt Generate ASCII Bitstream file.

-dev <Device Name>: Indicates the name of the device (optional). The device name must
be the full device name with the performance grade replaced with two X’s, and minus the
industry rating or the code name.
Example:
LFE3-17EA-XXFN484 (with performance grade replaced with two X's).
The device name will default to the device name in the data file. If a device name cannot
be found in the file, it will return an error unless the name has been given with the -dev
option.
-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes. Optional. Default file name is the same name as the input file.
ASCII bit files should end with the *.rbt extension.
-compress <on | off>: Specifies compression (optional). Default is off.
-verifyid: On: Include the Verify ID frame. Off: Replaces Verify ID frame with NOOP
(optional). Default is off.
-freq: Specifies the frequency of the master bitstream.
Possible frequencies valid for LatticeEC/P, LatticeECP2/M, LatticeECP3, and LatticeXP/2
devices only are: 2.5, 4.3, 5.4, 6.9, 8.1, 9.2, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, 60,
and 130 MHz. Possible frequencies valid for for MachXO2 and MachXO3L devices only
are: 2.1, 2.5, 3.2, 4.3, 5.5, 7, 8.3, 9.2, 10, 13, 15, 20, 27, 30, 33, 38, 44, 53, 66, 89, and
133 MHz. Possible frequencies valid for for ECP5 devices only are: 2.4, 3.2, 4.1, 4.8, 6.5,
8.2, 9.7, 12.9, 15.5, 16.3, 19.4, 20.7, 25.8, 31, 34.4, 38.8, 44.3, 51.7, 62, 77.5, 103.3, and
155 MHz.
-crc <frame | global>: The “frame” option includes the CRC checking for each data frame.
The "global option disables the frames CRC but still calculates the global CRC at the end
of the configuration data. Default uses the settings of the input file. Valid for LatticeECP2/
M, LatticeECP2S/SM, LatticeECP3, ECP5, MachXO3L, MachXO2, and LatticeXP/2
devices only.
-secure <on | off>: Specifies program security (optional). On: Programs the Security Fuse
(blocks read back). Off: Does not program the Security Fuse (allows read back).Default
uses the settings of the input file.
-overwriteues on: Overwrites (or replaces) the USERCODE value contained in the input
file with the hex value passed in.
Note: The encryption software patch must be installed before using the following -
encryption -key and -config_mode commands.
-encryption -key hex <Valid Key Value>: Encrypts the input file using the -key 128-bit
encryption key.
-config_mode <slave_scm | slave_pcm | jtag | spi | spim | master_pcm | slave_spi>]:
Selects the appropriate configuration mode for the bitstream encryption. Valid for
LatticeECP2S/MS and LatticeECP3 devices only.

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Option Description

-int Generate Intel 32-bit hex file.

-dev <Device Name>: Indicates the name of the device. Optional. The device name must
be the full device name with the performance grade replaced with two X’s, and minus the
industry rating or the code name.
Example:
LFE3-17EA-XXFN484 (with performance grade replaced with two X's).
The device name will default to the device name in the data file. If a device name cannot
be found in the file, it will return an error unless the name has been given with the -dev
option.
-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes. Optional. Default file name is the same name as the input file.
Intel files should end with the *.mcs extension.
-compress <on | off>: Specifies compression (optional). Default is off.
-verifyid: On: Include the Verify ID frame. Off: Replaces Verify ID frame with NOOP
(optional). Default is off.
-freq: Specifies the frequency of the master bitstream.
Possible frequencies valid for LatticeEC/P, LatticeECP2/M, LatticeECP3, and LatticeXP/2
devices only are: 2.5, 4.3, 5.4, 6.9, 8.1, 9.2, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, 60,
and 130 MHz.
Possible frequencies valid for for MachXO2 and MachXO3L devices only are: 2.1, 2.5,
3.2, 4.3, 5.5, 7, 8.3, 9.2, 10, 13, 15, 20, 27, 30, 33, 38, 44, 53, 66, 89, and 133 MHz.
Possible frequencies valid for for ECP5 devices only are: 2.4, 3.2, 4.1, 4.8, 6.5, 8.2, 9.7,
12.9, 15.5, 16.3, 19.4, 20.7, 25.8, 31, 34.4, 38.8, 44.3, 51.7, 62, 77.5, 103.3, and 155
MHz.
-crc <frame | global>: The “frame” option includes the CRC checking for each data frame.
The "global option disables the frames CRC but still calculates the global CRC at the end
of the configuration data. Default uses the settings of the input file. Valid for ECP5,
LatticeECP2/M, LatticeECP2S/SM, LatticeECP3, MachXO3L, MachXO2, and LatticeXP/2
devices only.
-mirror: Flips each byte. Default: bytes are not flipped. Optional.
-header: Retains the input file header in the output file. Default: Replaces header with all
ones (0xFF). Optional.
-secure <on | off>: Specifies program security (optional). On: Programs the Security Fuse
(blocks read back). Off: Does not program the Security Fuse (allows read back). Default
uses the settings of the input file.
-overwriteues on: Overwrites (or replaces) the USERCODE value contained in the input
file with the hex value passed in.
Note: The encryption software patch must be installed before using the following -
encryption -key and -config_mode commands.
-encryption -key hex <Valid Key Value>: Encrypts the input file using the -key 128-bit
encryption key.

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Option Description

-int (cont.) -config_mode <slave_scm | slave_pcm | jtag | spi | spim | master_pcm | slave_spi>]:
Selects the appropriate configuration mode for the bitstream encryption. Valid for
LatticeECP2S/MS and LatticeECP3 devices only.
-address <hex address> Specifies the starting address of the memory device to store
the input file.
-fast: Using this option, the FPGA will issue the Fast Read command (0x0B) to the SPI
Flash, instead of the Slow Read command (0x03). Valid for ECP5.

-mot Generate Motorola 32-bit hex file.

-dev <Device Name>: Indicates the name of the device. Optional. The device name must
be the full device name with the performance grade replaced with two X’s, and minus the
industry rating or the code name.
Example:
LFE3-17EA-XXFN484 (with performance grade replaced with two X's).
The device name will default to the device name in the data file. If a device name cannot
be found in the file, it will return an error unless the name has been given with the -dev
option.
-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes. Optional. Default file name is the same name as the input file.
Motorola files should end with the *.exo extension.
-compress <on | off>: Specifies compression (optional). Default is off.
-verifyid: On: Include the Verify ID frame. Off: Replaces Verify ID frame with NOOP
(optional). Default is off.
-freq: Specifies the frequency of the master bitstream.
Possible frequencies valid for LatticeEC/P, LatticeECP2/M, LatticeECP3, and LatticeXP/2
devices only are: 2.5, 4.3, 5.4, 6.9, 8.1, 9.2, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, 60,
and 130 MHz.
Possible frequencies valid for for MachXO2 and MachXO3L devices only are: 2.1, 2.5,
3.2, 4.3, 5.5, 7, 8.3, 9.2, 10, 13, 15, 20, 27, 30, 33, 38, 44, 53, 66, 89, and 133 MHz.
Possible frequencies valid for for ECP5 devices only are: 2.4, 3.2, 4.1, 4.8, 6.5, 8.2, 9.7,
12.9, 15.5, 16.3, 19.4, 20.7, 25.8, 31, 34.4, 38.8, 44.3, 51.7, 62, 77.5, 103.3, and 155
MHz.
-crc <frame | global>: The “frame” option includes the CRC checking for each data frame.
The "global option disables the frames CRC but still calculates the global CRC at the end
of the configuration data. Default uses the settings of the input file. Valid for ECP5,
LatticeECP2/M, LatticeECP2S/SM, LatticeECP3, MachXO3L, MachXO2, and LatticeXP/2
devices only.
-mirror: Flips each byte. Default: bytes are not flipped. Optional.
-header: Retains the input file header in the output file. Default: Replaces header with all
ones (0xFF). Optional.
-secure <on | off>: Specifies program security (optional). On: Programs the Security Fuse
(blocks read back). Off: Does not program the Security Fuse (allows read back). Default
uses the settings of the input file.

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Option Description

-mot (cont.) -overwriteues on: Overwrites (or replaces) the USERCODE value contained in the input
file with the hex value passed in.
Note: The encryption software patch must be installed before using the following -
encryption -key and -config_mode commands.
-encryption -key hex <Valid Key Value>: Encrypts the input file using the -key 128-bit
encryption key.
-config_mode <slave_scm | slave_pcm | jtag | spi | spim | master_pcm | slave_spi>]:
Selects the appropriate configuration mode for the bitstream encryption. Valid for
LatticeECP2S/MS and LatticeECP3 devices only.
-address <hex address> Specifies the starting address of the memory device to store
the input file.
-fast: Using this option, the FPGA will issue the Fast Read command (0x0B) to the SPI
Flash, instead of the Slow Read command (0x03). Valid for ECP5.

-xtek Generate Tektronix Extended hex file

-dev <Device Name>: Indicates the name of the device (optional). The device name must
be the full device name with the performance grade replaced with two X’s, and minus the
industry rating or the code name.
Example:
LFE3-17EA-XXFN484 (with performance grade replaced with two X's).
The device name will default to the device name in the data file. If a device name cannot
be found in the file, it will return an error unless the name has been given with the -dev
option.
-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes. Optional. Extended Tektronix files should end with the *.xtek
extension.
-compress <on | off>: Specifies compression (optional). Default is off.
-verifyid: On: Include the Verify ID frame. Off: Replaces Verify ID frame with NOOP
(optional). Default is off.
-freq: Specifies the frequency of the master bitstream.
Possible frequencies valid for LatticeEC/P, LatticeECP2/M, LatticeECP3, and LatticeXP/2
devices only are: 2.5, 4.3, 5.4, 6.9, 8.1, 9.2, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, 60,
and 130 MHz.
Possible frequencies valid for MachXO2 and MachXO3L devices only are: 2.1, 2.5, 3.2,
4.3, 5.5, 7, 8.3, 9.2, 10, 13, 15, 20, 27, 30, 33, 38, 44, 53, 66, 89, and 133 MHz.
Possible frequencies valid for ECP5 devices only are: 2.4, 3.2, 4.1, 4.8, 6.5, 8.2, 9.7, 12.9,
15.5, 16.3, 19.4, 20.7, 25.8, 31, 34.4, 38.8, 44.3, 51.7, 62, 77.5, 103.3, and 155 MHz.
-crc <frame | global>: The “frame” option includes the CRC checking for each data frame.
The "global option disables the frames CRC but still calculates the global CRC at the end
of the configuration data. Default uses the settings of the input file. Valid for ECP5,
LatticeECP2/M, LatticeECP2S/SM, LatticeECP3, MachXO3L, MachXO2, and LatticeXP/2
devices only.

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Option Description

-xtek (cont.) -mirror: Flips each byte. Default: bytes are not flipped (optional).
-header: Retains the input file header in the output file. Default: Replaces header with all
ones (0xFF) (optional).
-secure <on | off>: Specifies program security (optional). On: Programs the Security Fuse
(blocks read back). Off: Does not program the Security Fuse (allows read back).Default
uses the settings of the input file.
overwriteues on: Overwrites (or replaces) the USERCODE value contained in the input
file with the hex value passed in.
Note: The encryption software patch must be installed before using the following -
encryption -key and -config_mode commands.
-encryption -key hex <Valid Key Value>: Encrypts the input file using the -key 128-bit
encryption key.
-config_mode <slave_scm | slave_pcm | jtag | spi | spim | master_pcm | slave_spi>]:
Selects the appropriate configuration mode for the bitstream encryption. Valid for
LatticeECP2S/MS and LatticeECP3 devices only.
-address <hex address> Specifies the starting address of the memory device to store
the input file.
-fast: Using this option, the FPGA will issue the Fast Read command (0x0B) to the SPI
Flash, instead of the Slow Read command (0x03). Valid for ECP5.

-svf Generate SVF file for a single device.

-dev <Device Name>: Indicates the name of the device. Optional. The device name must
be the full device name with the performance grade replaced with two X’s, and minus the
industry rating or the code name.
Example:
LCMXO2-256ZE-XXMG64 (with performance grade replaced with two X's).
The device name will default to the device name in the data file. If a device name cannot
be found in the file, it will return an error unless the name has been given with the -dev
option.
-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes (optional). Default file name is the same name as the input file.
SVF files should end with the *.svf extension.
-op Indicates the operation. The operation list varies depending on the device family. Use
the Deployment Tool GUI to create the command line.
-nocomments: Omit Header and Comments from SVF file (optional). Default includes
Header and Comments.
-revd: Generate Rev D standard SVF file (optiona)l. Default generates Lattice Extended
SVF file (not supported by all third party tools).
-runtest: Uses RUNTEST format from SVF revision C (optional). Default is revision D
SVF file.
-skipverify: Generates an SVF without the verify portion (optional).
-reset: Writes RESET in the SVF file (optional).
-maxdata [<8 | 16 | 32 | 64 | 128 | 256> ]: Specifies the maximum data size per row (in
Kbits) (optional).

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Option Description

-svfchain Generate SVF file for chain of devices.

-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes (optional). Default file name is the same name as the input file.
SVF files should end with the *.svf extension.
-nocomments: Omit Header and Comments from SVF file (optional). Default includes
Header and Comments.
-revd: Generate Rev D standard SVF file (optional). Default generates Lattice Extended
SVF file (not supported by all third party tools).
-runtest: Uses RUNTEST format from SVF revision C (optional). Default is revision D
SVF file.
-skipverify: Generates an SVF without the verify portion (optional).
-reset: Writes RESET in the SVF file (optional).
-maxdata [<8 | 16 | 32 | 64 | 128 | 256> ]: Specifies the maximum data size per row (in
Kbits) (optional).

-stp Generate Standard Test and Programming Language (STAPLE) file.

-dev <Device Name>: Indicates the name of the device (optional). The device name must
be the full device name with the performance grade replaced with two X’s, and minus the
industry rating or the code name.
Example:
LCMXO2-256ZE-XXMG64 (with performance grade replaced with two X's).
The device name will default to the device name in the data file. If a device name cannot
be found in the file, it will return an error unless the name has been given with the -dev
option.
-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes (optional). Default uses the input file name with *.stp
extension.
-op Indicates the operation. The operation list varies depending on the device family. Use
the Deployment Tool GUI to create the command line.
-nocompress: < ON | OFF >: Generates a compressed or uncompressed STAPL file.
Default is ON.
-print < ON | OFF >: Generates a STAPL file with all the comment statements. Default is
OFF.
-skipverify: < ON | OFF >: Generates a STAPL file without the Verify portion (optional).

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Option Description

-stpchain Generate Standard Test and Programming Language (STAPL) file for a chain of devices.
-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes. Optional. Default uses the input file name with *.stp extension.
-nocompress: < ON | OFF >: Generates a compressed or uncompressed STAPL file.
Default is ON.
-print < ON | OFF >: Generates a STAPL file with all the comment statements. Default is
OFF.
-skipverify: < ON | OFF >: Generates a STAPL file without the Verify portion (optional).

-ate Generate ATE file.

-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes (optional). Default uses the input file name with *.tst, *.gr, *.pcf,
or *.asc extension, descending type.
-type: <tst | gr | hp3070 | hp3065 | t1800 | t200>
-ispdcd: Generates vectors in ispDCD Format.
-skipverify: For Erase, Program, and Verify Operations, Skip Verify.
-headerfile <file path>: Specifies a customer header file.
-splitfile [ -init] [ -vectors <# vectors/file>] [ -splitatlow]: Split each file at active Low.
Default: Split each file at active high.

-fullvme Generate JTAG Full VME Embedded file.

-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes (optional). Default uses the input file name with *.vme
extension.
-maxdata <8 | 16 | 32 | 64 | 128 | 256>: Maximum Memory Allocation Size Per Row of
Data (Kbytes) (optional).
-hex: Generate a Hex (.c) file along with the VME file (optiona)l.
-nocompress: Do not compress data (optional).
-compact: Compact VME file. Optional.
-fixedpulse: Generate a fixed pulse width VME file (optional).
-verifyues: Test the USERCODE. Program the device if USERCODE fails verify
(optional).
-noheader: Omit header from VME file (optional).
-comment: Include comments in VME file (optional).

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Option Description

-slimvme Generate JTAG Slim VME Embedded file.

-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-ofa "<Algorithm File Path>": Programming Algorithm file (optional). Default use input with
*.algo.vme.
-ofd "<Data File Path>": Programming Data file (optional). Default uses input with
*.data.vme.
-nocompress: Do not compress data (optional).
-hex: Generate a Hex (.c) file along with the Slim VME file (optional).

-sspi Generate Target SPI embedded file.

-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-ofa "<Algorithm File Path>": Programming Algorithm file (optional). Default use input with
*.algo.vme.
-ofd "<Data File Path>": Programming Data file (optional). Default uses input with
*.data.vme.
-nocompress: Do not compress data (optional).
-hex: Generate a Hex (.c) file along with the Target SPI Embedded file (optional).
-op Indicates the operation. This is required when the input file is JEDEC. When the input
file is an XCF, the XCF contains the operation.

-i2c Generate I2C embedded file.

-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-ofa "<Algorithm File Path>": Programming Algorithm file (optional). Default use input with
*.algo.vme.
-ofd "<Data File Path>": Programming Data file (optional). Default uses input with
*.data.vme.
-nocompress: Do not compress data (optional).
-hex: Generate a Hex (.c) file along with the VME file (optional).
-op Indicates the operation. This is required when the input file is JEDEC. When the input
file is an XCF, the XCF contains the operation.
-address <80 | (User Specified)> Specifies the slave I2C address.
-comment: Include comments in I2C embedded file (optional).
-fixedpulse: Generate a fixed pulse width I2C embedded file (optional).

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Option Description

-cpu Generates sysCONFIG CPU Embedded file.

-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes (optional). Default uses the input file name with the extension
of the selected -type.
-type <cpu | c | hex | txt>: Indicates whether file is in binary embedded (cpu), C-code (c),
Intel Hex (hex), or Text debug only (txt) format.
-verify: Generates a sysCONFIG Embedded file that includes a verify operation.
-comment: Include comments in sysCONFIG Embedded file (optional).
-nocompress: Do not compress data (optional).
-mirror: Flips each byte. Default: bytes are not flipped (optional).

-boot Generate Dual Boot Hex file.

-dev <Device Name>: Indicates the name of the device (optional). The device name must
be the full device name with the performance grade replaced with two X’s, and minus the
industry rating or the code name.
Example:
LFE3-17EA-XXFN484 (with performance grade replaced with two X's).
The device name will default to the device name in the data file. If a device name cannot
be found in the file, it will return an error unless the name has been given with the -dev
option.
-golden "<Golden File Path>" -primary "<Primary File Path>": Merges the Golden,
Primary, and a JUMP command into one Hex file. The address location of the Golden,
Primary, and JUMP command depends on the files sizes and the target device. The
Deployment Toll will record the address location of each in the Status window and log file.
-format < intel | motorola | xtek >: Specifies the output format as Intel, Motorola, or
Tektronix Extended Hex. The default format is Intel Hex (optional). Default uses the input
file name with *.mcs, *exo, or *.xtek extension, depending on format type selected.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes (optional). Default uses the input file name with *.mcs, *exo, or
*.xtek extension, depending on format type selected.
-flashsize: Specifies size in Mb.
Possible PROM sizes are 1, 2, 4, 8, 16, 32, 64, 128, 256, and 513 (512Mb).
Default: 1.

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Option Description

-boot (cont.) -protect: Inserts the Golden File at the beginning of the upper half of the SPI flash
(optional). This allows the upper half of the SPI flash to be write-protected, which protects
the Golden File from accidental erase or reprogram.
-mirror: Flips each byte. Default: bytes are not flipped (optional).
-header: Retains the input file header in the output file. Default: Replaces header with all
ones (0xFF) (optional).
-preamble: Replaces the header Preamble of the primary bitstream with 0xFFs (for Fail
Safe Upgrade feature) (optional).
-optimize: Uses the files size of the input files to determine SPI flash sector addresses for
each input file. Use this option to minimize wasted memory space. The default is to use
worst case file size fo the target device, which is an uncompressed file with all EBR and
PCS, depending on the family. Using the worst case will ensure that all files will always be
located at the same address even if any of the files/designs are updated at a later date.
-asc <1 | 2 | 3 | 4 | 5 | 6 | 7 | 8> Indicates the number of ASC devices connected to the
MachXO2 or Platform Manager 2 device. The maximum number that can be used with
the MachXO2 device is 8. The maximum number that can be used with the Platform
Manager 2 device is 7. The input JEDEC file and the ASC Hex files will be merged into
one Hex file that can be programmed into an external SPI Flash device for Dual Boot
support. Optional.
-ascfile "<Data File Path>": Specifies the ASC Hex file path and name. If the file path
includes spaces, enclose the path in quotes. There must be one "-ascfile" and path for
each ASC specified by the "-asc" Optional.
<-fast | -dualio | -quad 1>: With the -fast option, the FPGA will issue the Fast Read
command (0x0B) to the SPI Flash. The -dualio option must be used if a Dual I/O SPI
Flash is used. The -quad 1 option must be used if a Quad I/O SPI Flash is used. Only one
of these options (-fast, -dualio, -quad 1) can be used. Without any of these options, the
FPGA uses the Slow Read command (0x03). Valid for ECP5.
-encryption -key hex <Valid Key Value>: Encrypts the input file using the -key 128-bit
encryption key.

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Option Description

-jed Generates JEDEC file.

-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-dev <Device Name>: Indicates the name of the device (optional). The device name must
be the full device name with the performance grade replaced with two X’s, and minus the
industry rating or the code name.
Example:
LCMXO2-256ZE-XXMG64 (with performance grade replaced with two X's).
The device name will default to the device name in the data file. If a device name cannot
be found in the file, it will return an error unless the name has been given with the -dev
option.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes (optional). Default uses the input file name with *.jed
extension.
-overwriteues <on>: Overwrites (or replaces) the USERCODE value contained in the
input file with the hex value passed in. The Checksum option overwrites the USERCODE
with the JEDEC file fuse checksum value. The Disable option omits the USERCODE from
the JEDEC file.
Note: The encryption software patch must be installed before using the following -
encryption -key commands.
-encryption -key hex <Valid Key Value>: Encrypts the input file using the -key 128-bit
encryption key.

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Option Description

-advanced Generates Advanced SPI Flash Hex file.

-dev <Device Name>: Indicates the name of the device (optional). The device name must
be the full device name with the performance grade replaced with two X’s, and minus the
industry rating or the code name.
Example:
LFE3-17EA-XXFN484 (with performance grade replaced with two X's).
The device name will default to the device name in the data file. If a device name cannot
be found in the file, it will return an error unless the name has been given with the -dev
option.
-if <Data File Path>: Indicates the input data file full path and file name. If the file path
includes spaces, enclose the path in quotes.
-format < intel | motorola | xtek >: Specifies the output format as Intel, Motorola, or
Tektronix Extended Hex. The default format is Intel Hex (optional).
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes (optional). Default uses the input file name with *.mcs. *.exo, or
*.xtek extension, depending on the format selected.
-flashsize: Specifies size in Mb. Possible PROM sizes are 512 (512Kb), 1, 2, 4, 8, 16, 32,
64, 128 , 256, and 513 (512Mb). Default: 1.
-mirror: Flips each byte. Default: bytes are not flipped (optional).
-header: Retains the input file header in the output file. Default: Replaces header with all
ones (0xFF) (optional).
-preamble: Replaces the header Preamble of the bitstream with 0xFFs (for Fail Safe
Upgrade feature) (optional).
-userdata <1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16> Number of data
files.
-userdata: Flips each byte of the user data files. Default: bytes are not flipped (optional).
-userfile “<Data File Path>” Indicates the input user data file path and file name. Must be
specified for each user data file (-userdata).
-address <hex address value>: SPI flash address location for the user data file. Must be
specified for each user data file (-userdata).
-optimize: Uses the files size of the input files to determine SPI flash sector addresses for
each input file. Use this option to minimize wasted memory space. The default is to use
worst case file size fo the target device, which is an uncompressed file with all EBR and
PCS, depending on the family. Using the worst case will ensure that all files will always be
located at the same address even if any of the files/designs are updated at a later date.
-ice: iCE40 warm boot cold boot.
-warm <1 | 2 | 3 | 4>: Optional. Default is cold boot. The -warm selects warm boot. The
number selects the first boot configuration file.
-patterns <2,3,4>: Specifies the number of iCE40 configuration files.
-bootfile “<Data File Path>”: Indicates the input configuration file path and name. Must be
specified for each configuration file (-patterns).
-address <hex address value>: SPI flash address location for the configuration file. Must
be specified for each configuration file (-patterns).
<-fast | -dualio | -quad 1>: With the -fast option, the FPGA will issue the Fast Read
command (0x0B) to the SPI Flash. The -dualio option must be used if a Dual I/O SPI
Flash is used. The -quad option must be used if a Quad I/O SPI Flash is used. Only one
of these options (-fast, -dualio, -quad 1) can be used. Without any of these options, the
FPGA uses the Slow Read command (0x03). Valid for ECP5.

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Option Description

-advanced (cont.) -multi <1 | 2 | 3 | 4> Optional. The -multi option selects Multiple Boot. The number selects
the number of alternate files. Must be used in conjunction with Dual Boot, since dual boot
is a subset of Multiple Boot feature. The Golden file must also be selected. The data file
passed in using the -if option is considered the Primary file.
-golden "<Data File Path>" Indicates the Golden file path and file name.
-altfile “<Data File Path>” Indicates the alternate file path and name. Must specify the
alternate file for each number following the -multi option.
-address <hex address value> SPI Flash address location for the alternate file. Must be
specified for each alternate file (-altfile).
-next <primary | alt1 | alt2 | alt3 |alt4> Indicates which will be the next pattern to boot from
when the PROGRAMN pin is toggle, or the Refresh command is issued. Must be
specified for each alternate file (-altfile).

-merge -ifdev1 “<Data File Path>” Indicates the input dta file full path and file name for the first
device in the chain. If the file path includes spaces.
-ifdev2 “<Data File Path>” “Second device in the chain.”
-format < intel | motorola | xtek >: Specifies the output format as Intel, Motorola, or
Tektronix Extended Hex. The default format is Intel Hex (optional).
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes (optional). Default uses the input file name with *.mcs. *.exo, or
*.xtek extension, depending on the format selected.
-mergeformat <intelligent | combine> Intelligent merge will set the appropriate bits in the
bitstream to support sysCONFIG Daily Chaining. Combine will merge the two files without
changing any bits in the bitstreams.
-freq: Specifies the frequency of the master bitstream.
Possible frequencies valid for LatticeEC/P, LatticeECP2/M, LatticeECP3, and LatticeXP/2
devices only are: 2.5, 4.3, 5.4, 6.9, 8.1, 9.2, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, 60,
and 130 MHz.
Possible frequencies valid for for MachXO2 and MachXO3L devices only are: 2.1, 2.5,
3.2, 4.3, 5.5, 7, 8.3, 9.2, 10, 13, 15, 20, 27, 30, 33, 38, 44, 53, 66, 89, and 133 MHz.
Possible frequencies valid for for ECP5 devices only are: 2.4, 3.2, 4.1, 4.8, 6.5, 8.2, 9.7,
12.9, 15.5, 16.3, 19.4, 20.7, 25.8, 31, 34.4, 38.8, 44.3, 51.7, 62, 77.5, 103.3, and 155
MHz.
-scoutput <dout | qout>: For LatticeSC/M devices, indicates if the output pin is Dout or
Qout.
-mirror: Flips each byte. Default: bytes are not flipped (optional).
-header: Retains the input file header in the output file. Default: Replaces header with all
ones (0xFF). Optional.

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Option Description

-bsm Generates Application Specific BSDL file.

-ifd “<Data File Path>”: Indicates the input data file full path and file name.If the file name
includes spaces ...
-ifb “<BSDL File Path>”: Indicates the input BSDL file full path and file name. If the file
path includes spaces ...
-dev <Device Name>: Indicates the name of the device (optional). The device name must
be the full device name with the performance grade replaced with two X’s, and minus the
industry rating or the code name.
Example:
LCMXO2-256ZE-XXMG64 (with performance grade replaced with two X's).
The device name will default to the device name in the data file. If a device name cannot
be found in the file, it will return an error unless the name has been given with the -dev
option.
-of "<Data File Path>": Indicates the output file path. If the file path includes spaces,
enclose the path in quotes (optional). Default uses the input file name with *.???
extension.
-convertbidi: Converts bidirectional I/Os to input or output only, based on the user’s
design. Default is to keep al bidirectional I/Os as bidirectional (optional).

-jed2hex Generates an ASCII Raw Hex file.

-jed2bin Generates a Binary Raw Hex file.

Examples The following are DDTCMD examples.

Tester Examples:

SVF - Single Device:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -svfsingle -if

"C:/example/lfxp2_05ef256.jed" -dev LFXP2-5E -op "FLASH
Erase,Program,Verify" -of "C:/ example/
lfxp2_05ef256.svf"

SVF - JTAG Chain:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -svfchain -if

"C:/example/demo.xcf" -of "C:/ example/demo.svf"

STAPL - Single Device:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -stpsingle -if

"C:/example/ isppac_powr1220at8.jed" -dev ispPAC-
POWR1220AT8 -op "Erase,Program,Verify" -of "C:/ example/
isppac_powr1220at8.svf"

STAPL - JTAG Chain:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -stpchain -if

"C:/example/demo.xcf" -of "C:/example/demo.svf"

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ATE - Generic Vector Format:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -ate -if " C:/

example/demo.xcf " -type tst -of " C:/example/demo.tst"

ATE - GenRad:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -ate -if " C:/

example/demo.xcf " -type gr -of " C:/example/demo.gr"

ATE - HP3070:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -ate -if " C:/

example/demo.xcf " -type hp3070 -of " C:/example/
demo.pcf"

ATE - HP3065:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -ate -if " C:/

example/demo.xcf " -type hp3065 -of " C:/example/
demo.pcf"

ATE - Teradyne 1800:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -ate -if " C:/

example/demo.xcf " -type t1800 -of " C:/example/demo.asc"

ATE - Teradyne L200/300:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -ate -if " C:/

example/demo.xcf " -type t200 -of " C:/example/demo.asc"

Embedded System Examples:

JTAG Full VME Embedded:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -fullvme -if

"C:/example/demo.xcf" -of "C:/example/demo.vme"

JTAG Slim VME Embedded:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -slimvme -if

"C:/example/demo.xcf" -ofa "C:/ example/demo_algo.vme" -
ofd "C:/ example/demo_data.vme"

Slave SPI Embedded:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -sspi -if "C:/

example/demo.xcf" -ofa "C:/example/demo_algo.sea" -ofd
"C:/example/demo_data.sed"

I2C Embedded:

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"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -i2c -if "C:/

example/demo.xcf" -ofa "C:/example/demo_algo.iea" -ofd
"C:/example/demo_data.iea"

sysCONFIG (CPU) Embedded - Binary:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -cpu -if "C:/

example/demo.xcf" -type cpu -of "C:/example/
demo_algo.cpu"

sysCONFIG (CPU) Embedded - C-Code:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -cpu -if "C:/

example/demo.xcf" -type c -of "C:/example/demo_algo.c"

sysCONFIG (CPU) Embedded - Intel Hex:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -cpu -if "C:/

example/demo.xcf" -type hex -of "C:/example/
demo_algo.hex"

sysCONFIG (CPU) Embedded - Text (Debug Only):

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -cpu -if "C:/

example/demo.xcf" -type txt -of "C:/example/
demo_algo.txt"

External Memory Examples:

Hex Conversion - Intel Hex:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -int -dev LFE2-

6E -if "C:/example/lfec2_06ef256.bit" -of "C:/example/
lfec2_06ef256.mcs"

Hex Conversion - Motorola Hex:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -mot -dev LFE2-

6E -if "C:/example/lfec2_06ef256.bit" -of "C:/example/
lfec2_06ef256.exo"

Hex Conversion - Extended Tektronix Hex:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -xtek -dev LFE2-

6E -if "C:/example/lfec2_06ef256.bit" -of "C:/example/
lfec2_06ef256.xtek"

Dual Boot - Intel Hex:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -boot -dev LFE3-

95E -golden "C:/example/lfec3_095_golden.bit" -primary
"C:/example/lfec3_095.bit" -format int -flashsize 64 -of
"C:/example/lfec3_095_dual_boot.mcs"

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Dual Boot - Motorola Hex:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -boot -dev LFE3-

95E -golden "C:/example/lfec3_095_golden.bit" -primary
"C:/example/lfec3_095.bit" -format mot -flashsize 64 -of
"C:/example/lfec3_095_dual_boot.exo"

Dual Boot - Extended Tektronix Hex:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -boot -dev LFE3-

95E -golden "C:/example/lfec3_095_golden.bit" -primary
"C:/example/lfec3_095.bit" -format xtek -flashsize 64 -of
"C:/example/lfec3_095_dual_boot.xtek"

File Conversion Examples:

Bitstream - Binary Bitstream:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -bit -dev LFXP2-

5E -if "C:/example/lfxp2_05ef256.jed" -of "C:/example/
lfxp2_05ef256.bit"

Bitstream - ASCII Bitstream:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd" -oft -rbt -dev LFE2-

6E -if "C:/example/lfec2_06ef256.bit" -of "C:/example/
lfec2_06ef256.rbt"

JEDEC - Hex and JEDEC - Binary:

"C:/lscc/radiant/3.5/bin/nt/ddtcmd -oft <jed2hex|jed2bin>

[-dev <Device Name>] -if "<Data File Path>" [-of "<Data
File Path>"]

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Return Codes

Code Definition

0 CMD_SUCCESS

-1 ERROR_LOG_FILE

-2 OUT_MEMORY

-3 CANNOT_WRITE_DIRECTORY

-4 ERROR_CONFIGURATION_SETUP

-5 DEVICE_NAME_NOT_FOUND

-6 FILE_NOT_FOUND

-7 FILE_NOT_VALID

-8 UNKNOWN_OPERATION

-9 TOO_MANY_CHIPS

-10 FILE_NOT_JEDEC

-11 ERROR_OUTPUT_FILE

-12 OPERATION_NOT_SUPPORT

-13 FILE_NAME_ERROR

-14 FILE_READ_ERROR

-15 ERROR_BUILD_SVP_FILE

-16 ERROR_BUILD_BJD_FILE

-17 ERROR_BUILD_SVF_FILE

-18 CANNOT_WRITE_LOG_FILE

-19 MISSING_START_FILE

-20 UNKNOWN_DEVICE

-21 ERRROR_BUILD_BIT_FILE

-22 MULTIPLE_DEVICES_FOUND

-23 DEVICE_NOT_MATCH_FILE

-24 ERROR_COMMAND_LINE_SYNTAX

-25 ERROR_BUILD_ISC_FILE

-26 ERROR_BUILD_SPLIT_BITSTREAM_FILE

-27 ERROR_BUILD_MERGE_BITSTREAM_FILE

-28 ERROR_INPUT_FILE

-29 ERROR_BUILD_BITSTREAM_FILE

-30 ERROR_BUILD_JED_FILE

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Code Definition

-31 ERROR_BUILD_PROM_FILE

-32 DEVICE_NOT_SUPPORTED

See Also
 Command Line Data Flow
 Command Line Program Overview

Running Various Utilities from the

Command Line
The command line utilities described in this section are not commonly used by
command line users, but you often see them in the auto-make log when you
run design processes in the Radiant software environment. Click each link
below for its function, syntax, and options.

Note
For information on commonly-used FPGA command line tools, see Command Line
Basics.

Synpwrap
The synpwrap command line utility (wrapper) is used to manage Synplicity
Synplify and Synplify Pro synthesis programs from the Radiant software
environment processes: Synplify Synthesize Verilog File or Synplify
Synthesize VHDL File.

The synpwrap utility can also be run from the command line to support a
batch interface. For details on Synplify see the Radiant Software Help. The
synpwrap program drives synplify_pro programs with a Tcl script file
containing the synthesis options and file list.

Note
This section supersedes the “Process Optimization and Automation” section of the
Synplicity Synplify and Synplify Pro for Lattice User Guide.

This section illustrates the use of the synpwrap program to run Synplify Pro
for Lattice synthesis scripts from the command line. For more information on
synthesis automation of Synplify Pro, see the “User Batch Mode” section of
the Synplicity Synplify and Synplify Pro for Lattice User Guide.

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If you use Synplify Pro, the Lattice OEM license requires that the command
line executables synplify_pro be run by the Lattice “wrapper” program,
synpwrap.

Command Line Syntax

synpwrap [-nolog] [-int <command_file>] [-gui] [-int <prj_file> | -prj

<project_file>] [-notoem] [-notpro] [-options <arguments>]

Table 21: SYNPWRAP Command Line Options

Option Description

-options <arguments> Passes all arguments to Synplify/Synplify Pro. Ignores all

other options except -notOEM and -notPro. It must be at
the end of other options.

-gui Invokes the Synplify GUI instead of batch running.

-notOEM Does not use the Lattice OEM version of Synplify/Synplify

Pro.

-notPro Does not use Synplify Pro. It will automatically use

Synplify if SynplifyPro does not exist.

-int <prj_file> Same as the -gui and -prj <file> options. Invokes Synplify
GUI with project per command file.

-nolog Does not print out the log file after the process is finished
if there is no error (batch mode only).

-prj <project_file> Uses Synplify .prj file instead of the command file
(recommended).

-fg Forces to run in foreground mode, and waits for Synplify

to quit. Only available with the -options command.

-h|-help Prints this usage. Same as running the process without

any arguments.

Example

Below shows a synpwrap command line example.

synpwrap -gui -prj C:/lscc/radiant/2023.2/sample/sample.prj

See Also
 Command Line Program Overview
 Command Line Data Flow

IP Generation
The IP generation command allows you to generate or update existing IPs in
the design.

Command Line Syntax

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ipgen.EXE [-h] [-o OUTPUT_DIR] [-proj_dir PROJ_DIR] [-ip

IP_MODULE_DIR] [-cfg IP_CONFIG_FILE] [-skip_uniquify
SKIP_UNIQUIFY_HDL] [-cfg_value IP_CONFIG_VALUE] -name
IP_INSTANCE_NAME [-platform IPGEN_PLATFORM] [-vlnv IPGEN_VLNV]
[-rtl_library_path RTL_LIBRARY_PATH] [-a ARCHITECTURE] [-p DEVICE]
[-t PACKAGE] [-sp PERFORMANCE] [-f FAMILY]

Table 22: IP Generation Command Line Options

Option Description

-h, --help Shows this help message.

-o OUTPUT_DIR Location where the IP instance package will be

generated. Default is the current directory.

-proj_dir PROJ_DIR Location of the Radiant project, which owns generated IP

instance package. Default is the current directory.

-ip IP_MODULE_DIR Location of the IP module package.

-cfg IP_CONFIG_FILE Location of the IP configuration file.

-skip_uniquify Controls whether uniquified HDL files are True or False.

SKIP_UNIQUIFY_HDL

-cfg_value IP configuration value: 'id:value; id1:value1'

IP_CONFIG_VALUE

-name Name of the IP instance package.

IP_INSTANCE_NAME

-platform Name of ipgen's runtime environment: Radiant or Propel.

IPGEN_PLATFORM The default is Radiant.

-vlnv IPGEN_VLNV Location of the IP configuration file by vendor library

name and version.

-rtl_library_path The RTL library path for IP.

RTL_LIBRARY_PATH

-a ARCHITECTURE Target architecture name.

-p DEVICE Target device name.

-t PACKAGE Target package name.

-sp PERFORMANCE Target performance name.

-f FAMILY Target family name.

See Also
 Command Line Program Overview
 Command Line Data Flow

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IP Packager
The IP Packager (ippkg) tool can be run from the command line, allowing IP
developers to select files from disks and pack them into one IPK file.

The process of IP packager is as following:

 IP author prepares metadata files, RTL files, HTML files, etc (all files of a
Soft IP).
 IP Packager GUI provides UI for IP author to select files from the disk, and
call IP Packaging engine to pack them into an IPK file.
 IP Packaging engine encrypts RTL files if IEEE P1735-2014 V1 pragmas
are specified in RTL source

Command Line Syntax

ippkg [-h] (-metadata METADATA_FILE | -metadata_files

METADATA_LIST_NAME) (-rtl RTL_FILE | -rtl_files RTL_LIST_NAME) [-
encrypt FORCE_ENCRYPT_FILE | -encrypt_files
FORCE_ENCRYPT_LIST_NAME] [-plugin PLUGIN_FILE] [-ldc LDC_FILE]
[-fdc FDC_FILE] [-testbench TESTBENCH_FILE | -testbench_files
TESTBENCH_LIST_NAME] [-driver_file DRIVER_FILE | -driver_files
DRIVER_LIST_NAME] [-eval_file EVAL_FILE | -eval_files
EVAL_LIST_NAME] (-help_file HELP_FILE | -help_files
HELP_LIST_NAME) [-license_file LICENSE_FILE] [-o OUTPUT_ZIP_FILE]
[-key_file KEY_FILE]

Table 23: IPPKG Command Line Options

Option Description

-metadata The file name will be fixed to ‘metadata.xml.

-metadata_files Location of the file which stores the metadata files. One
line is a file path in specified file. Must have a file named
metadata.xml.

-rtl Specify the IP RTL file.

-rtl_files One line is a file path in specified file.

-encrypt Encrypt the whole RTL files.

-encrypt_files One line is a file path in specified file.

-plugin The file name will be fixed to ‘plugin.py’.

-ldc Specify the LDC file.

-fdc Specify the FDC file.

-testbench Specify the testbench file.

-testbench_files One line is a file path in specified file.

-driver Specify the driver file.

-driver_files One line is a file path in specified file.

-eval Specify the IP evaluation file.

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Table 23: IPPKG Command Line Options

Option Description

-eval_files One line is a file path in specified file.

-help_file Specify the help file, must be <path>/introduction.html.

-help_files One line is a file path in specified file.

-license_file Specify the license file.

-o Specify the output zip file.

-key_file Specify the key file to encrypt the RTL files.

Example

The following is an ippkg command line example:

ippkg –metadata c:/test/test.xml –rtl_files c:/test/rtl_list –
help_file c:/test/introduction.html

See Also
 Command Line Program Overview
 Command Line Data Flow

ECO Editor
The ECO Editor tool can be run from the command line too.

ECO Editor is also able to dump the ECO TCL commands which user acted in
GUI view without saving any UDB file.

In the meanwhile, we will have one non-GUI ECO engine tool, it accepts the
dumped TCL script file with a UDB file and output a new UDB file.

User can set ‘Place & Route design‘ milestone post-script by Tcl command
prj_set_postscript par <eco.tcl>, then Radiant flow runs the ECO Tcl script
automatically after running place & route.

Command Line Syntax

ecoc [-s <script_file>] [-o <output.udb>] <input.udb>]

Table 24: ECO Editor Command Line Options

Option Description

-s ECO Tcl script file.

-o Output UDB file.

<input.udb> Input UDB file.

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Example

The following is an ecoc command line example:

ecoc -s mem.tcl ebr_test_impl_1.udb

See Also
 Command Line Program Overview
 Command Line Data Flow

Running Standalone Timing Analyzer from the

Command Line
The Standalone Timing Analyzer can be run from the command line too.

Command Line Syntax

tavmain <udb file name> [<pdc file name>]

Example

The following is a tavmain command line example:

tavmain design.udb design.pdc

See Also
 Command Line Program Overview
 Command Line Data Flow

Using Command Files

This section describes how to use command files.

Creating Command Files

The command file is an ASCII file containing command arguments,

comments, and input/output file names. You can use any text editing tool to
create or edit a command file, for example, vi, emacs, Notepad, or Wordpad.

Here are some guidelines when you should observe when creating command
files:
 Arguments (executables and options) are separated by space and can be
spread across one or more lines within the file.
 Place new lines or tabs anywhere white space would otherwise be
allowed on the Linux or DOS command line.
 Place all arguments on the same line, or one argument per line, or any
combination of the two.
 There is no line length limitation within the file.

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 All carriage returns and other non-printable characters are treated as

space and ignored.
 Comments should be preceded with a # (pound sign) and go to the end of
the line.

Command File Example

This is an example of a command file:

#command line options for par for design mine.udb
-a -n 10
-w
-l 5
-s 2 #will save the two best results
/home/users/jimbob/designs/mine.udb
#output design name
/home/users/jimbob/designs/output.dir
#use timing constraint file
/home/users/jimbob/designs/mine.prf

Using the Command File

The –f Option

Use the –f option to execute a command file from any command line tool. The
–f option allows you to specify the name of a command file that stores and
then executes commonly used or extensive command arguments for a given
FPGA command line executable tool. You can then execute these arguments
at any time by entering the Linux or DOS command line followed by the name
of the file containing the arguments. This can be useful if you frequently
execute the same arguments each time you perform the command, or if the
command line becomes too long. This is the recommended way to get around
the DOS command line length limitation of 127 characters. (Equivalent to
specifying a shell Options file.)

The –f indicates fast startup, which is performed by not reading or executing

the commands in your .cshrc | .kshrc | .shrc (C-shell, Korn-shell, Bourne-
shell) file. This file typically contains your path information, your environment
variable settings, and your aliases. By default, the system executes the
commands in this file every time you start a shell. The –f option overrides this
process, discarding the 'set' variables and aliases you do not need, making
the process much faster. In the event you do need a few of them, you can add
them to the command file script itself.

Command File Usage Examples

You can use the command file in two ways:

 To supply all of the command arguments as in this example:

par -f <command_file>

where:

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<command_file> is the name of the file containing the command line

arguments.
 To insert certain command line arguments within the command line as in
the following example:

par -i 33 -f placeoptions -s 4 -f routeoptions design_i.udb design_o.udb

where:

placeoptions is the name of a file containing placement command

arguments.

routeoptions is the name of a file containing routing command arguments.

Using Command Line Shell Scripts

This topic discusses the use of shell scripts to automate either parts of your
design flow or entire design flows. It also provides some examples of what
you can do with scripts. These scripts are Linux-based; however, it is also
possible to create similar scripts called batch files for PC but syntax will vary
in the DOS environment.

Creating Shell Scripts

A Linux shell script is an ASCII file containing commands targeted to a

particular shell that interprets and executes the commands in the file. For
example, you could target Bourne Shell (sh), C-Shell (csh), or Korn Shell
(ksh). These files also can contain comment lines that describe part of the
script which then are ignored by the shell. You can use any text editing tool to
create or edit a shell script, for example, vi or emacs.

Here are some guidelines when you should observe when creating shell
scripts:
 It is recommended that all shell scripts with “#!” followed by the path and
name of the target shell on the first line, for example, #!/bin/ksh. This
indicates the shell to be used to interpret the script.
 It is recommended to specify a search path because oftentimes a script
will fail to execute for users that have a different or incomplete search
path. For example:
PATH=/home/usr/lsmith:/usr/bin:/bin; export PATH
 Arguments (executables and options) are separated by space and can be
spread across one or more lines within the file.
 Place new lines or tabs anywhere white space would otherwise be
allowed on the Linux command line.
 Place all arguments on the same line, or one argument per line, or any
combination of the two.
 There is no line length limitation within the file.

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 All carriage returns and other non-printable characters are treated as

space and ignored.
 Comments are preceded by a # (pound sign) and can start anywhere on a
line and continue until the end of the line.
 It is recommended to add exit status to your script, but this is not required.
# Does global timing meet acceptable requirement range?
if [ $timing -lt 5 -o $timing -gt 10 ]; then
echo 1>&2 Timing \"$timing\" out of range
exit 127
fi
etc...
# Completed, Exit OK
exit 0

Advantages of Using Shell Scripts

Using shell scripts can be advantageous in terms of saving time for tasks that
are often used, in reducing memory usage, giving you more control over how
the FPGA design flow is run, and in some cases, improving performance.

Scripting with DOS

Scripts for the PC are referred to as batch files in the DOS environment and
the common practice is to ascribe a .bat file extension to these files. Just like
Linux shell scripts, batch files are interpreted as a sequence of commands
and executed. The COMMAND.COM or CMD.EXE (depending on OS)
program executes these commands on a PC. Batch file commands and
operators vary from their Linux counterparts. So, if you wish to convert a shell
script to a DOS batch file or vice-versa, we suggest you find a good general
reference that shows command syntax equivalents of both operating systems.

Examples

The following example shows running design “counter” on below device

package

Architecture: iCE40UP

Device: iCE40UP3K

Package: UWG30

Performance: Worst Case

Command 1: logic synthesis
synthesis -f counter_impl1_lattice.synproj
which the *.synproj contains
-a "iCE40UP"
-p iCE40UP3K
-t UWG30
-sp "Worst Case"
-optimization_goal Area
-bram_utilization 100
-ramstyle Auto

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-romstyle auto
-dsp_utilization 100
-use_dsp 1
-use_carry_chain 1
-carry_chain_length 0
-force_gsr Auto
-resource_sharing 1
-propagate_constants 1
-remove_duplicate_regs 1
-mux_style Auto
-max_fanout 1000
-fsm_encoding_style Auto
-twr_paths 3
-fix_gated_clocks 1
-loop_limit 1950
-use_io_reg auto
-use_io_insertion 1
-resolve_mixed_drivers 0
-sdc "impl1.ldc"
-path "C:/lscc/radiant/1.0/ispfpga/ice40tp/data" "impl1"
-ver "C:/lscc/radiant/1.0/ip/pmi/pmi.v"
-ver "count_attr.v"
-path "."
-top count
-udb "counter_impl1.udb"
-output_hdl "counter_impl1.vm"

Command 2: post synthesis process

postsyn -a iCE40UP -p iCE40UP3K -t UWG30 -sp Worst Case -top -
ldc counter_impl1.ldc -keeprtl -w -o counter_impl1.udb
counter_impl1.vm

Command 3: Mapper
map "counter_impl1_syn.udb" "impl1.pdc" -o "counter_impl1.udb"

Command 4: Placer and router

par -f "counter_impl1.p2t" "counter_impl1_map.udb"
"counter_impl1.udb"

Command 5: Timer
timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -html -rpt
"counter_impl1_twr.html" "counter_impl1.udb"

Command 6: back annotation

backanno "counter_impl1.udb" -n Verilog -o
"counter_impl1_vo.vo" -w -neg

Command 7: bitstream generation

bitgen -w "counter_impl1.udb" -f "counter_impl1.t2b"

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 Chapter 9

Tcl Command Reference Guide

The Radiant software supports Tcl (Tool Command Language) scripting and
provides extended Radiant software Tcl commands that enable a batch
capability for running tools in the Radiant software’s graphical/console
interface. The command set and the Tcl Console used to run it affords you the
speed, flexibility and power to extend the range of useful tasks that the
Radiant software tools are already designed to perform.

In addition to describing how to run the Radiant software’s Tcl Console, this
guide provides you with a reference for Tcl command line usage and syntax
for all Radiant software point tools within the graphical user interface so that
you can create command scripts, modify commands, or troubleshoot existing
scripts.

About the Radiant software Tcl Scripting Environment

The Radiant software development software features a powerful script

language system. The user interface incorporates a complete Tcl command
interpreter. The command interpreter is enhanced further with additional
Radiant software-specific support commands. The combination of
fundamental Tcl along with the commands specialized for use with the
Radiant software allow the entire Radiant software development environment
to be manipulated.

Using the command line tools permits you to do the following:

 Develop a repeatable design environment and design flow that eliminates
setup errors that are common in GUI design flows
 Create test and verification scripts that allow designs to be checked for
correct implementation
 Run jobs on demand automatically without user interaction

The Radiant software command interpreter provides an environment for

managing your designs that are more abstract and easier to work with than

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using the core Radiant software engines. The Radiant software command
interpreter does not prevent use of the underlying transformation tools. You
can use either the Tcl commands described in this section or you can use the
core engines described in the Command Line Reference Guide.

Information about TCL features and flow are listed below:

 Launching the Tcl Console
 Running Radiant Tcl
 Log and Tcl Files
 Lattice Implementation Directory
 Attributes
 Understanding Design Flows
 Using Implementation Strategies and Options
 Running Project Flow
 Running Non-Project Flow
 Switching From Project Flow to Non-Project Flow
 Running Milestone Results in Non-Project Flow
 Opening GUI in Non-Project Flow
 Design Flow Examples
 Accessing Command Help and Command Options in the Tcl Console
 Changes in the Interface
 Creating and Running Custom Tcl Scripts
 Running Tcl Scripts When Launching the Radiant Software
 Radiant Software Tool Tcl Command Syntax
 Radiant Software Tcl Console Commands
 Radiant Software Timing Constraints Tcl Commands
 Radiant Software Physical Constraints Tcl Commands
 Technology Mapping Tcl Commands
 Synthesis Tcl Command
 Design Object Tcl Commands
 System Tcl Commands
 Radiant Software Project Tcl Commands
 Design Tcl Commands
 Device Tcl Commands
 Place & Route Tcl Commands
 Timing Analysis Tcl Commands
 Simulation Libraries Compilation Tcl Commands
 Reveal Inserter Tcl Commands

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 Reveal Analyzer Tcl Commands

 Power Calculator Tcl Commands
 Programmer Tcl Commands
 Engineering Change Order Tcl Commands
 IP Version Update Tcl Commands
 Message Control Tcl Commands
 Placement Tcl Commands
 Routing Tcl Commands
 Bitstream Generation Tcl Commands

Additional References

If you are unfamiliar with the Tcl language you can get help by visiting the Tcl/
tk web site at https://www.tcl.tk. If you already know how to use Tcl, see the
Tcl Manual supplied with this software. For information on command line
syntax for running core tools that appear as Radiant software processes, such
as synthesis, map, par, backanno, and timing, see the Command Line
Reference Guide.

Launching the Tcl Console

The Radiant software Tcl Console environment is made available for your use
in multiple different ways. In order to take full advantage of the FPGA
development process afforded by the Radiant software you must gain access
to the Radiant Tcl Console user interface.

On Windows

In Windows you can interact with the Tcl Console by anyone of the following
methods:
 To launch the Radiant software GUI from the Windows Start menu,
choose Start > Lattice Radiant Software (version_number) > Radiant
Software.
After the Radiant software loads, you can click on the Tcl Console tab.
With the Tcl Console tab active, you are able to start entering standard
syntax TCL commands or the Radiant software-specific support
commands.
 To launch the Tcl Console independently from the Radiant software GUI
from the Windows Start menu choose Start > Lattice Radiant Software
(version_number) > Tcl Console.
A Windows command interpreter will be launched that automatically runs
the Tcl Console.
 To run the interpreter from the command line, type the following:
c:/lscc/radiant/<version_number>/bin/nt64/pnmainc

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The Radiant Tcl Console is now available to run.

 To run the interpreter from a Windows PowerShell from the Windows Start
menu choose Start > Windows PowerShell > Windows PowerShell
(x86).
A PowerShell interpreter window will open. At the command line prompt
type the following:
c:/lscc/radiant/<version_number>/bin/nt64/pnmainc

The Radiant Tcl Console is now available to run.

Note
The arrangement and location of each of the programs in the Windows Start menu will
differ depending on the version of Windows you are running.

On Linux In Linux operating systems you can interact with the Tcl Console
by one of the following methods:
 To launch the Radiant software GUI from the command line, type the
following:
/usr/<user_name>/radiant/<version_number>/bin/lin64/radiant

The path provided assumes the default installation directory and that the
Radiant software is installed. After the Radiant software loads you can
click on the Tcl Console tab. With the Tcl Console tab active, you are
able to start entering standard syntax Tcl commands or the Radiant
software specific support commands.
 To launch the Tcl Console independently from the Radiant software GUI
from the command line, type the following:
/usr/<user_name>/Radiant/<version_number>/bin/lin64/radiantc

The path provided assumes the default installation directory and that the
Radiant software is installed, and that you have followed the Radiant
software for Linux installation procedures. The Radiant Tcl Console is
now ready to accept your input.
The advantage of running the Tcl Console from an independent
command interpreter is the ability to directly pass the script you want to
run to the Tcl interpreter. Another advantage is that you have full control
over the Tk graphical environment, which allows you to create you own
user interfaces.

Running Radiant Tcl

This section describes the following features:
 How to run Radiant Tcl
 Using log/tcl files

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 Accessing the Lattice run directory

Tcl supports the following command modes:

 GUI Mode (radiant) – you can use the radiant command to launch the
GUI mode. Radiant's Tcl Console window is still accessible, however it
currently only accepts project commands.
 Pure interactive shell mode (radiantc) – starts a pure interactive shell
mode. If a tcl file is specified in the command line, the run is done in batch
mode. Both project and non-project commands are supported by radiantc.
 Interactive shell/GUI mode (radiantc -gui) – starts as a shell mode. The
gui_start command can be used to launch GUI views. When GUI views
are closed, it returns to shell mode.

Log and Tcl Files

When using radiantc, the log message is automatically stored in the
radiantc.log file, and the tcl commands are kept in the radiant.tcl file. The
log message from the prior Radiant run is still stored in the automake.log file.

With radiantc mode, you can do following:

 Use the RAT_LOG_DIR environment variable to specify the directory
where you want to keep the log/tcl files.
If there is no environment variable, the log/tcl directory is set as
C:\Users\<User dir>\AppData\Roaming\LatticeSemi\DiamondNG\tcl if you
are using NT, and the current directory ./ when using Linux.
 Specify the run name to be used as the prefix of log/tcl file names.
For example, if you run radiantc -run mytest, the log file will be named
mytest.log and the tcl file will be named mytest.tcl.
 Run radiantc multiple times in the same directory.
The most recent run result is always stored in the radiantc.log and
radiantc.tcl files. It will be renamed to radiantc.log.<#> and
radiantc.tcl.<#>, respectively, if you have any older radiantc.log and
radiantc.tcl files.
From all these log and tcl files, you can see the historical runs of the same
design. For example, if you run radiantc three times at the same
directory, you will have the following files:
-rw-r--r-- 1 <command_name> ldc 8 Jun 21 14:55
radiantc.tcl.1 > First run
-rw-r--r-- 1 <command_name> ldc 8 Jun 21 14:57
radiantc.tcl.2 > Second run
rw-r--r-- 1 <command_name> ldc 8 Jun 21 15.02 radiantc.tcl
> Last run

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Lattice Implementation Directory

In non-project flow, the lattice working directory lattice_workdir keeps the
intermediate files during the run. The directory is created under your
implementation directory.
 Under lattice_workdir, you can find map, plc, and rte subdirectories which
keep the intermediate run results for technology map (map), placement
(plc), and routing (rte).
 For example, if you want to find the placement log file <file_name>.par,
you can find it under the plc subdirectory.

Attributes
In Radiant Tcl system, attributes are used for objects, such as system, design,
or instance.

For example:
 des_set_attribute is used to set design attributes.
 des_list_attribute is used to list the current design attributes.

Understanding Design Flows

Radiant Tcl supports both project and non-project flows.

In project flow, you can do the following:

 Create a new project or load a saved project from an existing project file.
 You can then add, delete, or list project files (i.e., RTL, constraint, and
strategy setting files). During the whole project flow, you can save it into a
project (.rdf) file any time.

For non-project flow:

 With two specific commands, Radiant Tcl may start a non-project flow
from an existing project flow. The Radiant database (.udb) file can be read
as input to begin the non-project flow, after which the design process can
continue.

There are four major differences between project and non-project

flows:
1. The project flow design is saved as disk files instead of being stored in
memory. You can use different strategies to create different
implementations for the same project. On the other hand, design in non-
project flow is kept in memory and can be accessed or changed
interactively using commands.
For example, you can use timing analysis commands to report timing
results at different paths.

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2. In project flow, you need to add project files. The time stamps of these
files are checked for any new commands. If there are any changes in the
project files, the flow will ask you to rerun the design at the right stages.
For example, if you change a post-synthesis constraint (.pdc) file, you
need to rerun technology mapping. However, if you change any RTL files
or the pre-synthesis constraint files, you need to rerun logic synthesis.
In non-project flow, the input file is a Radiant database (.udb) file, and the
time stamp of such file is not checked during the design flow.
3. You cannot skip any design stage from the run commands in non-project
flow.
For example, you need to run placement (plc_run) before you run routing
(rte_run) in non-project flow. However, you can use one of the prj_run
commands (prj_run_bitstream, prj_run_map, prj_run_par,
prj_run_synthesis) in project flow to run the design flow automatically from
the current stage to the target stage.
4. Implementation strategies are used in project flow and implementation
options in non-project flow.
Implementation strategy is a subset of implementation options.

Using Implementation Strategies and

Options
In Radiant, strategies are used to specify how to run specific tasks, such as
logic synthesis, technology mapping, and placement and routing.

To see the list of strategies in Radiant:

 In the toolbar, click Project > Active Strategy.
The list of strategies appear.

 For instance, if you click Place & Route Design Settings from the list, it
redirects to the Place & Route Design section in the Strategies dialog
box.

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In TCL, options are used to specify how to run specific tasks.

 For example, you can use par_list_option after a design has been
loaded to check the current placement and routing option setting, and use
par_set_option to change them:
% par_list_option
PAR Options:
command_line_options :
disable_auto_hold_timing_correction :
false
disable_timing_driven :
false
multi_tasking_node_list :
number_of_host_machine_cores : 1
placement_iteration_start_point : 1
placement_iterations : 1
placement_save_best_run : 1
prioritize_hold_correction_over_setup_performance :
false
run_placement_only :
false
set_speed_grade_for_hold_optimization : m
set_speed_grade_for_setup_optimization :
default
stop_once_timing_is_met :
false

Strategy and Option Guidelines:

1. Both strategy and option are device-dependent. You can only change
them after a device is selected.
2. You do not need to specify all options in the Radiant Strategy Settings.
However, all strategies used in Radiant must be converted to options with
the following rules:

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 If you are using options, change the space ( ) used in strategy to an

underscore (_) to separate words.
 In strategy, each word is capitalized. You need to change them to the
lower case format if you are using options.
 For example:
 Strategy uses the following format: Disable Auto Hold Timing
Correction
 Option uses the following format:
disable_auto_hold_timing_correction

Running Project Flow

Running the project flow in Radiant Tcl is the same as the current process.
You can use the Radiant software tools to add project files, run the design
flow, and output specific timing reports at different design stages.
Most prj_<command_name> commands are designed for project flow run
except prj_open_milestone. This command is used to switch from project
flow to non-project flow.
% help prj_open_milestone
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-postsyn boolflag (false) Open post-syn logical netlist
-postmap boolflag (false) Open post-map physical
netlist
-postpar boolflag (false) Open post-par physical
netlist

Running Non-Project Flow

You must load the design from a disk file in order to start a non-project flow.
For instance, the following commands load a mapped.udb file into
memory, report the current design, and run placement.
des_read_udb mydb_map.udb
des_report
plc_run

Switching From Project Flow to Non-

Project Flow
In project flow, you can use prj_open_milestone to open the run result at a
given design stage and switch to non-project flow.

For instance, you can see the postsyn run result after opening the
mydb_syn.rdf project by using the commands listed below.

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The design is currently in memory, and you can report and save it as a
Radiant database (.udb) file.
prj_open mydb_syn.rdf
prj_open_milestone -postsyn
des_report
des_write_udb -w mydb_syn.udb

Using syn_run instead of prj_run_synthesis for logic synthesis is another

way to transition to a non-project flow from a project flow.
 When syn_run is used, the tool will first execute logical synthesis using
the designated vendor tool before loading the post-synthesis design into
memory.
 After that, the flow switches to non-project flow, and you can use non-
project commands to complete the rest of the design process.
prj_create -name mytest -dev "LIFCL-40-8BG400C" -performance
"8_High-Performance_1.0V" -impl impl_prj_flow -impl_dir
impl_prj_flow -synthesis synplify
prj_add_source ./source/001_register_simple.v
prj_add_source ./others/constraints.sdc
prj_add_source ./others/register_simple1.sty
syn_run
des_report
des_write_udb -w mydb_syn.udb

With one of the two methods described above, you can change from project
flow to non-project flow. Once the design is in memory (i.e., in non-project flow
mode), it is not advised to use project commands.

Running Milestone Results in Non-

Project Flow
In non-project flow, the current design is stored in memory, unlike in project
flow which keeps previous designs at different milestones. To rerun a previous
step due to constraint or option changes, you need to reload the previous
milestone result and make a change, then rerun the command.

Note:
Milestone refers to processing tasks, which include synthesizing, mapping, placing,
and routing a design.

To rerun par_run with new par options, you need to do the following:
% par_run
% des_write_udb -w mydb_par.udb
% des_reload_milestone -postmap <your_mapped_udb>
% par_set_option (set your par run option)
% par_run

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To add a new constraint as a post-synthesis constraint, reload the post-syn

milestone as the constraints need to be processed through technology
mapping.
% par_run
% des_write_udb -w mydb_par.udb
% des_reload_milestone -postsyn <your_synthesized_udb>
% ldc_set_location (set your constraint)
% map_run
% par_run

To modify timing constraints for logical synthesis, change your constraint file
and restart the process from the beginning.

Opening GUI in Non-Project Flow

In order to open Radiant GUI views in non-project flow, you must run radiantc
with -gui option to enable the linking of the GUI libraries during the run. You
can open a post-par udb and use gui_start command to open GUI views.
>radiantc -gui
% des_read_udb <your_post_par.udb>
% gui_start

Certain GUI views require a post-synthesis netlist as the netlist view, which
can be added by incrementally reloading the post-synthesis udb.
>radiantc -gui
% des_read_udb <your_post_par.udb>
% des_reload_milestone -inc -postsyn <your_synthesized_udb>
% gui_start

Design Flow Examples

1. Running Pure-Project Flow
Tcl commands for pure-project run is shown in this use-case. To run a
pure-project, add Register Transfer Level (RTL) files, constraint files then
run the project using one of the prj_run commands (prj_run_bitstream,
prj_run_map, prj_run_par, prj_run_synthesis) and save the project files at
different stages.

Note:
Pure-project design flow is saved as disk file and not kept in memory. As a
result, you cannot run any non-project commands in a project flow. For
further information, refer to Opening a Post-Synthesis Milestone.

Open your console and type the following commands to create, add, run
and exit the program:
 To create a project, use prj_create command followed by choosing the
right device and synthesis tool name:

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prj_create -name mytest -dev "LIFCL-40-8BG400C" -

performance "8_High-Performance_1.0V" -impl impl_prj_flow
-impl_dir impl_prj_flow -synthesis synplify

 To add project files, use prj_add_source command followed by the

path of the file you want to add:
prj_add_source ./source/001_register_simple.v
prj_add_source ./others/constraints.sdc
prj_add_source ./others/register_simple1.sty

 To save an updated project file, use prj_save command:

prj_save mydb_syn.rdf
prj_save new_test.rdf
prj_save mydb_map.rdf
prj_save mydb_par.rdf

 To run synthesis project files, use the prj_run_synthesis command.

prj_run_synthesis

 To end the program, quit the command to end the flow:

quit
2. Creating Project Files
This section illustrates how to create project files, add Register Transfer
Level (RTL) file, and constraint files.
 To create a project, use prj_create command followed by choosing the
right device and synthesis tool name:
prj_create -name mytest -dev "LIFCL-40-8BG400C" -
performance "8_High-Performance_1.0V" -impl impl_prj_flow
-impl_dir impl_prj_flow -synthesis synplify
 To add project files, use prj_add_source command followed by the file
directory path you want to add:
prj_add_source ./source/001_register_simple.v
prj_add_source ./others/constraints.sdc
prj_add_source ./others/register_simple1.sty
 To switch from project flow to non-project flow, use the syn_run
command:
syn_run
Use syn_run instead of prj_run_synthesis to change from project
flow to non-project flow. After execution, the design is in memory and
you can continue the rest of the flow with non-project commands.

Note:
It is not recommended to run the flow with any of the prj_run commands
(prj_run_synthesis, prj_run_map, prj_run_par, prj_run_bitstream) once switched to
non-project flow.

 To run the design information, use des_report command:

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des_report
 To run the map tool, use map_run command, followed by
des_write_udb -w command to save the current design:
map_run
des_write_udb -w mydb_map.udb
 To run the placement tool and show the report placement information,
use plc_run and plc_report commands followed by des_write_udb -w
command to save the current design:
plc_run
plc_report
des_write_udb -w mydb_plc.udb
 To run the routing tool and show the routing result, use rte_run and
rte_report commands followed by des_write_udb -w command to save
the current design:
rte_run
rte_report
des_write_udb -w mydb_rte.udb
 To view the detailed report or summary timing, use the following
command:
sta_report_timing -summary
 To generate bitsream file, use bit_generate command followed by -w
command to force to overwrite the existing file:
bit_generate -w mydb_bit
 To end the program, quit the command to end the flow:
quit

3. Reading Post-Synthesis Design

This section shows you how to read in a design database and continue
the design flow.
 To read the post-synthesis database, use des_read_udb command
followed by the database file name. To view the report design
information, use des_report command:
des_read_udb mydb_syn.udb
des_report
 To set design attributes, use des_set_attribute command followed by -
impl_dir to implement name:
des_set_attribute -impl_dir impl_rdb_syn
 To run the map tool and to write the design as .udb file, use map_run
command followed by des_write_udb and overwrite to save using -w
command to completely run the design:
map_run
des_write_udb -w myrdbsyn_map.udb
 To run the placement tool and show the report placement information,
use plc_run command and plc_report command followed by
des_write_udb -w command to save the current design:

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plc_run
plc_report
des_write_udb -w myrdbsyn_plc.udb
 To run the routing tool and show the routing result, use rte_run and
rte_report commands followed by des_write_udb -w command to save
the current design:
rte_run
rte_report
des_write_udb -w myrdbsyn_rte.udb
 To view the detailed report or summary timing, use sta_report_timing -
summary command:
sta_report_timing -summary
 To generate bitstream file, use bit_generate command followed by -w
command to force to overwrite the existing file:
bit_generate -w mydb_bit
 To end the program, quit the command to end the flow:
quit
4. Reading the Post-Map UDB File
This section shows you how to read a post-map .udb file and continue the
design process.
 To read the post-map UDB file, use des_read_udb command followed
by the database file name. In the next line, use des_set_attribute
command followed by - impl_dir to define the directory where the
project file is stored:
des_read_udb mydb_map.udb
des_set_attribute -impl_dir impl_udb_map
 To run the placement tool and show the report placement information,
use plc_run and plc_report commands followed by des_write_udb -w
command to save the current design:
plc_run
plc_report
des_write_udb -w myudbmap_plc.udb
 To end the program, quit the command to end the flow:
quit
5. Reading and Routing the Post-Placement Design
This section describes the process of reading the post-placement
database, routing, and saving the design.
 To read the post-synthesis database, use des_read_udb command
followed by the database file name. Execute using des_set_attribute
command followed by - impl_dir to define the directory where the
project file is stored.
des_read_udb mydb_plc.udb
des_set_attribute -impl_dir impl_rdb_plc

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 To run the routing tool and show the routing result, use rte_run and
rte_report commands followed by des_write_udb -w command to save
the current design.
Use sta_report_timing - summary command to view the detailed report
or timing summary and use des_write_udb command with -w
command to overwrite or save the design.
rte_run
rte_report
sta_report_timing –summary
des_write_udb -w myrdbplc_rte.udb
 To end the program, quit the command to end the flow.
quit
6. Opening a Post-Synthesis Milestone
This section shows how to open a post-synthesis milestone in a project,
and load the run result in memory. When the design is in memory, you can
continue to use non-project commands to continue the flow and access
the design data.
 To open a project, use prj_open command followed by the file name.
prj_open mydb_syn.rdf
 To open a project milestone, use prj_open_milestone command
followed by - postsyn to open the logical netlist.
prj_open_milestone -postsyn
 To run the map tool and write the design as a .udb file, use map_run
command followed by des_write_udb and save using -w command to
run the design.
map_run
des_write_udb -w myprjsyn_map.udb
 To end the program, quit the command to end the flow
quit

See Also
 Launching the Tcl Console
 Running Radiant Tcl
 Accessing Command Help and Command Options in the Tcl Console
 Creating and Running Custom Tcl Scripts
 Running Tcl Scripts When Launching the Radiant Software
 Radiant Software Tool Tcl Command Syntax
 Tcl Manual

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Accessing Command Help and Command Options in

the Tcl Console
There are two ways to find all the Tcl command syntax help to generate all the
tools in the Tcl console.

To access command syntax help in the Tcl Console:

1. n the prompt, type help <tool_*keyword*> and press Enter:
% help {des_*instance*}
A list of valid command options appears in the Tcl Console.
2. In the Tcl Console, type the name of the command or function for more
details on syntax and usage.
For example:
 des_list_instance is used to list design instances.
 des_report_instance is used to report instance information.
A list of valid arguments for that function appears.
% help des_report_instance
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-file string () File name
?objects? string () List instances.

Note
In interactive mode, you can use command -help to get the list of command
information. However, most commands in the -help option are not true option, and the
Tcl interpreter interprets command -help as a usage error, which prevents a script from
finishing execution if it encounters this option. It is recommended to use help
{command} as this works in both interactive and script settings.

Changes in the Interface

The Radiant Tcl has the same Windows settings and appearance as the
Radiant Tcl, with some GUI improvements.
 Running the radiantc replaces the standalone tools such as Map, PAR,
and Bitgen for milestone runs for Map Design, Place & Route, and
Export Files using specific Tcl files, which are stored in the
implementation directory as <prj>_<impl>_map/par/bit.tcl.
 When you open the milestone run result, the File > Open menu displays
the Post-Synthesis Milestone, Post-Map Milestone, and Post-Par
Milestone, allowing you to perform non-project commands such as
des_report in the new radiantc terminal.

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See Also
 Launching the Tcl Console
 Running Radiant Tcl
 Accessing Command Help and Command Options in the Tcl Console
 Creating and Running Custom Tcl Scripts
 Running Tcl Scripts When Launching the Radiant Software
 Radiant Software Tool Tcl Command Syntax
 Tcl Manual

Creating and Running Custom Tcl Scripts

This topic describes how to easily create Tcl scripts using the Radiant
software’s user interface and manual methods. FPGA design using Tcl scripts
provides some distinct advantages over using the graphical user interface’s
lists, views and menu commands. For example, Tcl scripts allow you to do the
following:
 Set the tool environment to exactly the same state for every design run.
This eliminates human errors caused by forgetting to manually set a
critical build parameter from a drop-down menu.
 Manipulate intermediate files automatically, and consistently on every run.
For example, .vm file errors can be corrected prior to performing
additional netlist transformation operations.
 Run your script automatically by using job control software. This gives you
the flexibility to run jobs at any time of day or night, taking advantage of
idle cycles on your corporate computer system.

Creating Tcl Scripts

There are a couple of different methods you can use to create the Radiant
software Tcl scripts. This section will discuss each one and provide step-by-
step instructions for you to get started Tcl scripting repetitious Radiant
software commands or entire workflows.

One method you have available is to use your favorite text editor to enter a
sequence of the Radiant software Tcl commands. The syntax of each the
Radiant software Tcl commands is available in later topics in this portion of the
Help. This method should only be used by very experienced Radiant software
Tcl command line users.

The preferred method is to let the Radiant software GUI assist you in getting
the correct syntax for each Tcl command. When you interact with the Radiant
software user interface each time you launch a scriptable process and the
corresponding Radiant software Tcl command is echoed to the Tcl Console.
This makes it much simpler to get the correct command line syntax for each
Radiant software command. Once you have the fundamental commands
executed in the correct order, you can then add additional Tcl code to perform
error checking, or customization steps.

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To create a Tcl command script in the Radiant software:

1. Start the Radiant software design software and close any project that may
be open.
2. In the Tcl Console execute the custom reset command. This clears the Tcl
Console command history.
3. Use the Radiant software graphical user interface to start capturing the
basic command sequence. The Tcl Console echos the commands in its
window. Start by opening the project for which you wish to create the Tcl
script. Then click on the processes in the Process bar to run them. For
example, run these processes in their chronological order in the design
flow:
 Synthesize Design
 Map Design
 Place & Route Design
 Export Files
4. In the Tcl Console window enter the command,
save_script <filename.ext>
The <filename.ext> is any file identifier that has no spaces and contains
no special characters except underscores. For example, myscript.tcl or
design_flow_1.tcl are acceptable save_script values, but my$script or
my script are invalid. The <filename.ext> entry can be preceded with a
absolute or relative path. Use the "/" (i.e. forward slash) character to
delimit the path elements. If the path is not specified explicitly the script is
saved in the current working directory. The current working directory can
be determined by using the Tcl pwd command.
5. You can now use your favorite text editor to make any changes to the
script you feel are necessary. Start your text editor, navigate to the
directory the save_script command saved the base script, and open the
file.

Note
In most all cases, you will have to clean up the script you saved and remove any
invalid arguments or any commands that cannot be performed in the Radiant
software environment due to some conflict or exception. You will likely have to
revisit this step later if after running your script you experience any run errors due
to syntax errors or technology exceptions.

Sample Radiant software Tcl Script

The following the Radiant software Tcl script shows a very simple script that
opens a project, runs the entire design flow through the Place & Route
process, then closes the project. A typical script will contain more tasks and
will check for failure conditions. Use this simple example as a general
guideline.

Running Tcl Scripts

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Figure 83: Simple Radiant software Script

prj_archive -dir "C:/my_radiant/counter" -extract "C:/lscc/
radiant/1.1/examples/counter.zip"
prj_run_par
prj_close

The Radiant software Tcl scripts are run exclusively from the Radiant Tcl
Console. You can use either the Tcl Console integrated into the Radiant
software UI, or by launching the stand-alone Tcl Console.

To run a Tcl script in the Radiant software:

1. Launch the Radiant software GUI, or the stand-alone Tcl Console.
Open the Radiant software but do not open your project. If your project is
open, choose File > Close Project.
2. If you are using the Radiant software main window, click the small arrow
pane switch in the bottom of the Radiant software main window, and then
click on the Tcl Console tab in the Output area at the bottom to open the
console.
3. Use the Tcl source command to load and run your Tcl script. The source
command requires, as it's only argument, the filename of the script you
want to load and run. Prefix the script file name with any required relative
or absolute path information. To run the example script shown in the
previous section use:
source C:/lscc/radiant/<version_number>/examples/counter/
myscript2.tcl
As long as there are no syntax errors or invalid arguments, the script will
open the project, synthesize, map, and place-and-route the design. Once
the design finishes it closes the project. If there are errors in the script,
you will see the errors in red in the Tcl Console after you attempt to run it.
Go back to your script and correct the errors that prevented the script from
running.

See Also
 Launching the Tcl Console
 Running Radiant Tcl
 Accessing Command Help and Command Options in the Tcl Console
 Creating and Running Custom Tcl Scripts
 Running Tcl Scripts When Launching the Radiant Software
 Radiant Software Tool Tcl Command Syntax
 Tcl Manual

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Running Tcl Scripts When Launching the Radiant

Software
This topic describes how launch the Radiant software and automatically run
Tcl scripts using a command line shell or the stand-alone Tcl console. Your Tcl
script can be standard Tcl commands as well as the Radiant software-specific
Tcl commands.

Refer to Creating and Running Custom Tcl Scripts for more information on
creating custom Tcl scripts.

To launch the Radiant software and run a Tcl script from a command line
shell or the stand-alone Tcl console:
 Enter the following command:
On Windows:
pnmain.exe -t <tcl_path_file>

On Linux:
radiant -t <tcl_path_file>

Sample Radiant software Tcl Script The following Radiant software Tcl
script shows a very simple script, running in Windows, that opens a project
and runs the design flow through the MAP process. Use this simple example
as a general guideline.

Figure 84: Simple Radiant Software Script

prj_open C:/test/iobasic_radiant/io1.rdf
prj_run_map

The above example is saved in Windows as the file mytcl.tcl in the directory
C:/test. By running the following command from either a DOS shell or the Tcl
console in Windows, the Radiant software GUI starts, the project io1.rdf
opens, and the MAP process automatically runs.
pnmain.exe -t c:/test/mytcl.tcl

See Also
 Launching the Tcl Console
 Running Radiant Tcl
 Accessing Command Help and Command Options in the Tcl Console
 Creating and Running Custom Tcl Scripts
 Running Tcl Scripts When Launching the Radiant Software
 Radiant Software Tool Tcl Command Syntax
 Tcl Manual

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Radiant Software Tool Tcl Command Syntax

This part of the Tcl Command Reference Guide introduces the syntax of each
of the Radiant software tools and provides you with examples to help you
construct your own commands and scripts.

The Radiant software tries to make it easy to develop Tcl scripts by mirroring
the correct command syntax in the Tcl Console based on the actions
performed by you in the GUI. This process works well for most designs, but
there are times when a greater degree of control is required. More control
over the build process is made available through additional command line
switches. The additional switches may not be invoked by actions taken by you
when using the GUI. This section provides additional information about all of
the Tcl commands implemented in the Radiant software.
The Tcl Commands are broken into major categories. The major categories
are:
 Radiant Software Tcl Console Commands
 Radiant Software Timing Constraints Tcl Commands
 Radiant Software Physical Constraints Tcl Commands
 Technology Mapping Tcl Commands
 Synthesis Tcl Command
 Design Object Tcl Commands
 System Tcl Commands
 Radiant Software Project Tcl Commands
 Design Tcl Commands
 Place & Route Tcl Commands
 Device Tcl Commands
 Place & Route Tcl Commands
 Timing Analysis Tcl Commands
 Simulation Libraries Compilation Tcl Commands
 Reveal Inserter Tcl Commands
 Reveal Analyzer Tcl Commands
 Power Calculator Tcl Commands
 Programmer Tcl Commands
 Engineering Change Order Tcl Commands
 IP Version Update Tcl Commands
 Message Control Tcl Commands
 Placement Tcl Commands
 Routing Tcl Commands
 Bitstream Generation Tcl Commands

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Radiant Software Tcl Console

Commands
The Radiant software Tcl Console provides a small number of commands that
allow you to perform some basic actions upon the Tcl Console Pane. The
Radiant software Tcl Console commands differ from the other Tcl commands
provided in the Radiant software. This dtc program’s general Tcl Console
commands do not use the dtc_ prefix in the command syntax as is the
convention with other tools in the Radiant software.

Note:
Tcl Command Log is always listed after the project is closed. You can find it in the
Reports section under Misc Report > Tcl Command Log.

The following table provides a listing of all valid Radiant software Tcl Console-
related commands.

Table 25: Radiant Software Tcl Console Commands

Command Description

clear Erase anything present in the Tcl Console pane

and print the current prompt character in the upper
left corner of the Tcl Console pane without erasing
the command history.

history List the command history in the Tcl Console that

you executed in the current session.
Every command entered into the Tcl Console,
either by the GUI, or by direct entry in the Tcl
Console, is recorded so that it can be recalled at
any time.
The command history list is cleared when a project
is opened or when the Tcl Console reset command
is executed.

reset Clear the Tcl Console pane and erase all entries in
the command line history.
**This command is only used in the GUI Tcl
console and not supported in the standalone Tcl
console.

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Table 25: Radiant Software Tcl Console Commands

Command Description

save_script Save the contents of the command line history

memory buffer into the script file specified.
The script is, by default, stored into the current
working directory. File paths using forward slashes
used with an identifier are valid if using an
absolute file path to an existing script folder.
Usage: save_script <filename.ext>
**This command is only used in the GUI Tcl
console and not supported in the standalone Tcl
console.

set_prompt Set the default prompt character.

The default prompt character in the Tcl Console is
the “greater than” symbol or angle bracket (i.e., >).
You can change this prompt character to some
other special character such as a dollar sign ($) or
number symbol (#) if you prefer.
Usage: set_prompt <new_character>
**This command is only used in the GUI Tcl
console and not supported in the standalone Tcl
console.

Radiant Software Tcl Console Command Examples

This section illustrates and describes a few samples of Radiant Tcl Console
commands.

Example 1

To save a script, use the save_script command in the Tcl Console window
with a name or file path/name argument. In the first example command line,
the file path is absolute, that is, it includes the entire path. Here you are saving
“myscript.tcl” to the existing current working directory. The second example
creates the same “myscript.tcl” file in the current working directory.
save_script C:/lscc/radiant/myproject/scripts/myscript.tcl
save_script myscript.tcl

See Creating and Running Custom Tcl Scripts for details on how to save and
run scripts in the Radiant software.

Example 2

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The following set_prompt command reassigns the prompt symbol on the

command line as a dollar sign ($). The default is an angle bracket or “greater
than” sign (>).
set_prompt $

Example 3

The following history command will print all of the command history that was
recorded in the current Tcl Console session.
history

Radiant Software Timing Constraints

Tcl Commands
The section describes the commands are used to set timing constraints.

Radiant Software Timing Constraints Tcl Command Descriptions

The following table provides a listing of all valid Radiant software timing
constraints-related Tcl command options and describes option functionality.

Table 26: Radiant Software Timing Constraints Tcl Commands

Command Description

create_clock Create a named or virtual clock.

create_generated_clock Create a generated clock object.

set_clock_groups Set clock groups.

set_clock_latency Define a clock’s source or network latency.

set_clock_uncertainty Set clock uncertainty.

set_false_path Define false path.

set_input_delay Set input delay on ports.

set_load Set capacitance on ports.

set_max_delay Specify maximum delay for timing paths.

set_max_skew Define maximum skew of path.

set_min_delay Specify minimum delay for timing paths.

set_multicycle_path Define multicycle path.

set_output_delay Set output delay on ports.

set_hierarchy_separator Set or get hierarchy separator.

This section displays the usage information of the commands:

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create_clock
% help create_clock
create_clock - Commands to new clock object
Usage:
create_clock -period <period_value> [-name <clock_name>] [-
waveform <edge_list>] [<port_list|pin_list|net_list>]

create_generated_clock
% help create_generated_clock
create_generated_clock - Commands to new generated clock
object
Usage:
create_generated_clock [-name <clock_name>] -source
<master_pin> [-edges <edge_list>] [-edge_shift <shift_list>] [-
divide_by <factor>] [-multiply_by <factor>] [-duty_cycle
<percent>] [-invert] [-add] <pin_list|net_list|port_list>

set_clock_groups
% help set_clock_groups
set_clock_groups - Commands to set clock groups
Usage:
set_clock_groups <-logically_exclusive | -
physically_exclusive | -asynchronous> -group <clock_list>

set_clock_latency
% help set_clock_latency
set_clock_latency - Commands to defines a clock's source or
network latency
Usage:
set_clock_latency [-rise] [-fall] [-early | -late] -source
<latency> [<object_list> | all_clocks]

set_clock_uncertainty
% help set_clock_uncertainty
set_clock_uncertainty - Commands to set clock uncertainty.
Usage:
set_clock_uncertainty [-setup] [-hold] [-from <clock>] [-to
<clock>] <uncertainty> [<clock_list>]

set_false_path
% help set_false_path
set_false_path - Commands to define false path.
Usage:
set_false_path [-from
<port_list|pin_list|instance_list|net_list|clock_list>]

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[-to
<port_list|pin_list|instance_list|net_list|clock_list>]
[-through
<port_list|pin_list|instance_list|net_list>]
[-rise_from <clock_list>] [-rise_to
<clock_list>]
[-fall_from <clock_list>] [-fall_to
<clock_list>]

set_input_delay
% help set_input_delay
set_input_delay - Commands to set input delay on ports.
Usage:
set_input_delay -clock <clock_name> [-clock_fall] [-max | -
min] [-add_delay] <delay> [<port_list> | all_inputs]

set_load
% help set_load
set_load - Commands to set capacitance on ports
Usage:
set_load <capacitance> <objects>

set_max_delay
% help set_max_delay
set_max_delay - Commands to specify maximum delay for timing
paths.
Usage:
set_max_delay [-from
<port_list|pin_list|instance_list|net_list|clock_list>]
[-to
<port_list|pin_list|instance_list|net_list|clock_list>]
[-through
<port_list|pin_list|instance_list|net_list>] [-datapath_only]
[-rise_from <clock_list>] [-rise_to
<clock_list>]
[-fall_from <clock_list>] [-fall_to
<clock_list>] <delay>

set_max_skew
% help set_max_skew
set_max_skew - Commands to define max skew of path.
Usage:
set_max_skew <net_list|pin_list> <skew_value>

set_min_delay
% help set_min_delay
set_min_delay - Commands to specify minimum delay for timing
paths.
Usage:

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set_min_delay [-from
<port_list|pin_list|instance_list|net_list|clock_list>]
[-to
<port_list|pin_list|instance_list|net_list|clock_list>]
[-through
<port_list|pin_list|instance_list|net_list>]
[-rise_from <clock_list>] [-rise_to
<clock_list>]
[-fall_from <clock_list>] [-fall_to
<clock_list>] <delay>

set_multicycle_path
% help set_multicycle_path
set_multicycle_path - Commands to define multicycle path.
Usage:
set_multicycle_path [-from
<port_list|pin_list|instance_list|net_list|clock_list>]
[-to
<port_list|pin_list|instance_list|net_list|clock_list>]
[-through
<port_list|pin_list|instance_list|net_list>]
[-rise_from <clock_list>] [-rise_to
<clock_list>]
[-fall_from <clock_list>] [-fall_to
<clock_list>]
[-setup | -hold] [-start | -end]
<path_multiplier>

set_output_delay
% help set_output_delay
set_output_delay - Commands to set output delay on ports.
Usage:
set_output_delay -clock <clock_name> [-clock_fall] [-max |
-min] [-add_delay] <delay> [<port_list> | all_outputs]

set_hierarchy_separator

Although this is not a standard timing constraint command, it is used in

constraint files for specifying hierarchy. The default hierarchy separator for
Synplify Pro is a “.” (period), while Radiant tools use “/” (forward slash). If you
create a sub-module under more than two hierarchy levels, you need to
manually add the set_hierarchy_separator {/} line or change the separator
from “/” to “.”
% help set_hierarchy_separator
set_hierarchy_separator - Commands to set or get hierarchy
separator
Usage:
set_hierarchy_separator <separator>

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Radiant Software Physical Constraints

Tcl Commands
The ldc commands are used to set physical constraints.

Radiant Software Physical Constraints Tcl Command Descriptions

The following table provides a listing of all valid Radiant software physical
constraints-related Tcl command options and describes option functionality.

Table 27: Radiant Software Physical Constraints Tcl Commands

Command Description

ldc_create_group Define a single identifier that refers to a group of

objects.

ldc_create_macro Define a macro.

ldc_create_region Define a rectangular area.

ldc_create_vref Define a voltage reference.

ldc_define_attribute Define LSE attributes.

ldc_define_global_attribute Define LSE global attributes.

ldc_delete_constraint Clear constraints by given IDs.

ldc_get_groups Return group objects.

ldc_list_constraint List constraints from database.

ldc_prohibit Prohibit site or region.

ldc_read Read constraint file.

ldc_set_attribute Set object attributes.

ldc_set_location Set object location.

ldc_set_port Set port constraint attributes.

ldc_set_sysconfig Set sysconfig attributes.

ldc_set_vcc Set the voltage and/or derate for the bank, core or
dphy.

ldc_write Write constraint file.

This section displays the usage information of the commands:

ldc_create_group
% help ldc_create_group
ldc_create_group - Commands to create group
Usage:

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ldc_create_group -name <group_name> [-bbox {height width}]

<objects>

ldc_create_macro
% help ldc_create_macro
ldc_create_macro - Commands to create macro
Usage:
ldc_create_macro [-name <macro_name>] [-use_pio
<ports_list>] <instance>

ldc_create_region
% help ldc_create_region
ldc_create_region - Commands to create region
Usage:
ldc_create_region -name <region_name> (–anchor <anchor>|-
site <site>) -width <width> -height <height> [–buffer_left
<left> –buffer_right <right> –buffer_top <top> –buffer_bottom
<bottom>] [-exclusive] [-routing_exclusive]

ldc_create_vref
% help ldc_create_vref
ldc_create_vref - Commands to create a voltage vref
Usage:
ldc_create_vref -name <vref_name> -site <site_name>

ldc_define_attribute
% help ldc_define_attribute
ldc_define_attribute - Commands to define LSE attribute
Usage:
ldc_define_attribute -attr <attr_type> -value <attr_value>
-object_type <object type> -object <object> [-disable] [-
comment <comment>]

ldc_define_global_attribute
% help ldc_define_global_attribute
ldc_define_global_attribute - Commands to define gloabl LSE
attribute
Usage:
ldc_define_global_attribute -attr <attr_type> -value
<attr_value> [-disable] [-comment <comment>]

ldc_delete_constraint
% help ldc_delete_constraint
ldc_delete_constraints - Commands to clear constraints by given
IDs.Delete all constraints if ID is'-1'
Usage:
ldc_delete_constraint [-all] <id> [<id>...]

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ldc_get_groups
% help ldc_get_groups
ldc_get_groups - Commands to return group objects
Usage:
ldc_get_groups [-regexp] [-nocase] <patterns>

ldc_list_constraint
% help ldc_list_constraint
ldc_list_constraints - Commands to list constraints from
database
Usage:
ldc_list_constraint [-all]

ldc_prohibit
% help ldc_prohibit
ldc_prohibit - Commands to probibit site or region
Usage:
ldc_prohibit -site <site> | -region <region>

ldc_read
% help ldc_read
ldc_read - Commands to read constraint file
Usage:
ldc_read <file>

ldc_set_attribute
% help ldc_set_attribute
ldc_set_attribute - Commands to set attribute
Usage:
ldc_set_attribute <key-value list> [objects]

ldc_set_location
% help ldc_set_location
ldc_set_location - Commands to set location.
Usage:
ldc_set_location [-site <site_name>] [-bank <bank_num>] [-
region <region_name>] <object>

ldc_set_port
% help ldc_set_port
ldc_set_port - Commands to set port constraint attributes
Usage:
ldc_set_port [-iobuf [-vref <vref_name>]]|[-sso] <key-value
list> <ports>

ldc_set_sysconfig

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% help ldc_set_sysconfig
ldc_set_sysconfig - Commands to set sysconfig attributes
Usage:
ldc_set_sysconfig <key-value list>

ldc_set_vcc
% help ldc_set_vcc
ldc_set_vcc - Commands to set the voltage and/or derate for
the bank, core or dphy
Usage:
ldc_set_vcc [-bank bank|-core|-dphy DPHY0/DPHY1] [-derate
derate] [voltage]

ldc_write
% help ldc_write
ldc_write - Commands to write constraint file
Usage:
ldc_write [-overwrite|w] [-sdc] [-exclude_sdc] [-
include_error] <file>

Radiant Software Physical Constraints Tcl Commands Examples

This section illustrates and describes a few samples of Radiant Physical

Constraints Tcl commands.

Example 1

The ldc_create_group command creates a sample group with 3 instances,

and places all instances within the group to a 2x2 bbox.
ldc_create_group -name sample_group -bbox {2 2} [get_cells
{i16_1_lut i18_2_lut i25_3_lut }]

Example 2

The ldc_set_location command places the port clk to pin E7.

ldc_set_location -site {E7} [get_ports clk]

Example 3

The ldc_set_port command sets IO_TYPE, DRIVE, SLEWRATE attributes of

the port rst.

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ldc_set_port -iobuf {IO_TYPE=LVCMOS33 DRIVE=8 SLEWRATE=FAST}

[get_ports rst]

Technology Mapping Tcl Commands

The map commands are used to map or transfer a design from a logical view
to a physical view.

Radiant Software Technology Mapping Tcl Command Descriptions

The following table provides a listing of all valid Radiant software mapping-
related Tcl command options and describes option functionality.

Table 28: Technology Mapping Tcl Commands

Command Description

map_list_option List map options.

map_run Run map tool.

map_set_option Set map options.

This section displays the usage information of the commands:

map_list_option
% help map_list_option
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

map_run
% help map_run
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

map_set_option
% help map_set_option
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
?key_values? list () Option <key, value> pairs

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Synthesis Tcl Command

The syn command is used to run the synthesis process. You can change from
project flow to a non-project flow by using the syn_run command.

Radiant Software Synthesis Tcl Command Description

The following table provides a listing of all valid Radiant software synthesis-
related Tcl command options and describes option functionality.

Table 29: Synthesis Tcl Command

Command Description

syn_run Run synthesis tool.

This section displays the usage information of the command:

syn_run
% help syn_run
syn_run - Run synthesis tool
Usage:
syn_run

Design Object Tcl Commands

Design objects can be referred to in the SDC as a single object, or as a
collection of objects. Single objects must be referred to as a collection of a
single object. The current implementation of the SDC commands allows only
single objects in the collection. The exception to this are the all_* commands.
The get_info commands are used for constraints to return a single object, or
a collection of objects. You can get this command by using help {get_*}.

Radiant Software Design Object Tcl Command Descriptions

The following table provides a listing of all valid Radiant software design
object-related Tcl command options and describes option functionality.

In the example below, <target name> is a regular expression that matches

one object only.

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Clock Object

SDC Collection Description

get_clocks Return clock objects.

all_clocks Return a list of all clocks in the current design.

This section displays the usage information of the commands:

get_clocks
% help get_clocks
get_clocks - Commands to get clocks
Usage:
get_clocks [-regexp] [-nocase] <patterns>

all_clocks
% help all_clocks
all_clocks - Commands to get a list of all clocks in the
current design
Usage:
all_clocks

Radiant Software Clock Object Tcl Commands Example

This section illustrates and describes a few samples of Radiant clock object
Tcl commands.

Example 1

<target name> is the name of the clock. Clock is either given a name or gets
its name from the port/net on which it is defined.
get_clocks <target name>
[get_clocks clock_fast]

[all_clocks]

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Port Object

SDC Collection Description

get_port_info Return port object information.

get_ports Return port objects.

all_inputs Return a list of all input ports in the current design.

all_outputs Return a list of all output ports in the current

design.

This section displays the usage information of the commands:

get_port_info
% help get_port_info
get_port_info - Commands to return port info
Usage:
get_port_info [-name] [-is_inout] [-is_input] [-is_output]
<port_object>

get_ports
% help get_ports
get_ports - Commands to get ports
Usage:
get_ports [-regexp] [-nocase] <patterns>

all_inputs
% help all_inputs
all_inputs - Commands to get a list of all input ports in the
current design
Usage:
all_inputs

all_outputs
% help all_outputs
all_outputs - Commands to get a list of all output ports in
the current design
Usage:
all_outputs

Radiant Software Port Object Tcl Commands Example

This section illustrates and describes a few samples of Radiant port object Tcl
commands.

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Example 1

<target name> is the name of the port.

[get_ports <target name>]
[get_ports indata*]
[all_inputs]

Cell Object

SDC Collection Description

get_cell_info Return cell information.

get_cells Return instance objects.

This section displays the usage information of the commands:

get_cell_info
% help get_cell_info
get_cell_info - Commands to return cell info
Usage:
get_cell_info [-name] [-inpins] [-outpins] [-pins]
<cell_object>

get_cells
% help get_cells
get_cells - Commands to get instances
Usage:
get_cells [-hierarchical] [-regexp] [-nocase] [-of_objects
<objects>] <patterns>

Radiant Software Cell Object Tcl Commands Example

This section illustrates and describes a few samples of Radiant cell object Tcl
commands.

Example 1

The command returns collection of a design instance that matches <target

name>.
[get_cells <target name>

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[get_cells {reg6 reg7}]

Net Object

SDC Collection Description

get_net_info Return net information.

get_nets Return net objects.

This section displays the usage information of the commands:

get_net_info
% help get_net_info
get_net_info - Commands to return net info
Usage:
get_net_info [-name] [-pin] <net_object>

get_nets
% help get_nets
get_nets - Commands to get nets
Usage:
get_nets [-hierarchical] [-regexp] [-nocase] [-of_objects
<objects>] <patterns>

Radiant Software Net Object Tcl Commands Example

This section illustrates and describes a few samples of Radiant net object Tcl
commands.

Example 1

The command returns collection of a design net that matches <target name>.
Hierarchy is specified using regular expression.
[get_nets <target name>]
[get_nets clk1]

The get_nets command can used to define the target for a

create_generated_clock command.

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Pin Object

SDC Collection Description

get_pin_info Return pin objects.

get_pins Return pin information.

This section displays the usage information of the commands:

get_pin_info
% help get_pin_info
get_pin_info - Commands to return pin info
Usage:
get_pin_info [-name] [-is_clock] [-is_input] [-is_output]
[-net] [-parent_cell] <pin_object>

get_pins
% help get_pins
get_pins - Commands to get pins
Usage:
get_pins [-hierarchical] [-regexp] [-nocase] [-of_objects
<objects>] <patterns>

Radiant Software Pin Object Tcl Commands Example

This section illustrates and describes a few samples of Radiant pin object Tcl
commands.

Example 1

The command returns collection of design pin that matches <instance name>
| <pin name>. Hierarchy is specified using regular expression.
[get_pins <instance name> | <pin name>]
[get_pins ff2/D]

Wildcard Support
Multiple wildcard (*) is supported. In addition, the wildcard should be at the
end or beginning of the object name string. For example:
ab* matches abc, ab, abdefg, etc.
*bc matches abc, bbc, debc, etc.

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Note:
1. Wildcard * can be used in any position of object name such as a*, *b, a*b etc.
2. Wildcard * cannot cross hierarchical separator /. For example get_cells sub1/* only
returns sub1/sub2 and does not return sub1/sub2/sub1 or sub1/sub2/sub1/sub2.
3. When -hierarchical is set, it will search all levels of the design hierarchy starting at
the current instance.

System Tcl Commands

The sys commands are used to show Radiant tool and system settings
information. You can get these commands by using help {sys_*}.

Radiant Software System Tcl Command Descriptions

The following table provides a listing of all valid Radiant software system-
related Tcl command options and describes option functionality.

Table 30: System Tcl Commands

Command Description

sys_install_path Return Radiant executable path.

sys_install_version Return Radiant version.

sys_list_attribute List system attributes.

sys_set_attribute Set system attributes.

This section displays the usage information of the commands:

sys_install_path
% help sys_install_path
sys_install_path - Return Radiant executable path
Usage:
sys_install_path

sys_install_version
% help sys_install_version
sys_install_version - Return Radiant version
Usage:
sys_install_version

sys_list_attribute
% help sys_list_attribute

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Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

sys_set_attribute
% help sys_set_attribute
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-echo choice ("" on off) Allows you to enable or
disable the command summary line.
-reg choice ("" on off) Allows you to output
RAT_REG_RECORD_ON or RAT_REG_RECORD_OFF.
-gui choice ("" on off) The run is called from gui
if its value = on.
-msg string () The msg setting file.

Radiant Software Project Tcl

Commands
The Radiant software Project Tcl Commands allow you to control the contents
and settings applied to the tools, and source associated with your design.
Projects can be opened, closed, and configured to a consistent state using
the commands described in this section.

Radiant Software Project Tcl Command Descriptions

The following table provides a listing of all valid Radiant software project-
related Tcl command options and describes option functionality.

Table 31: Radiant Software Project Tcl Commands

Command Description

prj_activate_impl Activate implementation in the current project.

prj_add_source Add sources to the current project.

prj_archive Archive the current project.

prj_clean_impl Clean up the implementation result files in the

current project.

prj_clone_impl Clone an existing implementation.

prj_close Close the current project. Any unsaved changes

are discarded.

prj_copy_strategy Create a new strategy by copying from an existing

strategy.

prj_create Create a project.

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Table 31: Radiant Software Project Tcl Commands

Command Description

prj_create_impl Create a new implementation in the current

project.

prj_create_reveal_impl Create a Reveal implementation from existing

implementation.

prj_create_strategy Create a new strategy with default settings.

prj_device List the device.

prj_disable_source Disable the design sources from the current

project.

prj_enable_source Enable the design sources from the current

project.

prj_get_impl_path Return active or given implementation folder path.

prj_get_strategy_value Get value of a strategy item.

prj_import_strategy Import an existing strategy file.

prj_list_source List source files in current project.

prj_list_strategy List value of strategy items.

prj_open Open a project.

prj_open_milestone Open project milestone netlist files.

prj_remove_impl Delete the specified implementation from the

current project.

prj_remove_source Delete design source from the current project.

prj_remove_strategy Delete an existing strategy.

prj_run_bitstream Run bitstream process.

prj_run_map Run map process.

prj_run_par Run place & route process.

prj_run_synthesis Run synthesis process.

prj_save Save current project.

prj_saveas Save the current project as a new project with

specified name and directory.

prj_set_device Set the device.

prj_set_impl_opt List, set or remove implementation options in the

current project.

prj_set_opt List, set or remove a project option.

prj_set_postscript List or set user Tcl script after running milestone.

prj_set_prescript List or set user Tcl script before running milestone.

prj_set_source_format Set a source format.

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Table 31: Radiant Software Project Tcl Commands

Command Description

prj_set_source_opt List, set or remove a source option.

prj_set_strategy Associate the strategy with the specified

implementation.

prj_set_strategy_value Set value to a strategy item.

prj_set_top_module Set top module in the current implementation.

This section displays the usage information of the commands:

prj_activate_impl
% help prj_activate_impl
prj_activate_impl - Activate implementation in the current
project
Usage:
prj_activate_impl <impl name>

prj_add_source

This command adds a VHDL source file to the specified or active

implementation. The syntax used for the Add function depends upon the
source file’s implementation language.

[-work <VHDL lib name>]: Assigns the source code to the specified library
name space.

[-impl <implementation name>]: This switch is used to add a source file to a

Radiant software implementation. If this switch is not specified the source file
is added to the active implementation.

[-format <format name>]: This switch is used to add a source file format is
Verilog or VHDL.

[-opt name=value]: The -opt argument allows you to set a custom, user-
defined option. See Example 7 for guidelines and usage.

<sre file>...: One or more VHDL source files to add to the specified
implementation.
% help prj_add_source
prj_add_source - Add sources to the current project
Usage:
prj_add_source [-impl <implement name>] [-simulate_only|-
synthesis_only] [-include <path list for Verilog include search
path>] [-work <VHDL lib name>] [[-opt <name=value>] ...] [-
exclude] <src file>...

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prj_archive
% help prj_archive
prj_archive - Archive the current project
Usage:
prj_archive [-includeAll] <archive_file>
: Archive the current project into the archive_file
prj_archive -extract -dir <destination directory>
<archive_file>
: Extract the archive file and load the project

prj_clean_impl
% help prj_clean_impl
prj_clean_impl - Clean up the implementation result files in
the current project
Usage:
prj_clean_impl [-impl <implement name>]

prj_clone_impl

The -copyRef argument is used to copy source files from the original
implementation source folder to a new implementation source folder. If this is
not used, the existing implementation source files will be referenced in the
new implementation.
% help prj_clone_impl
prj_clone_impl - Clone an existing implementation
Usage:
prj_clone_impl <new impl name> [-dir <new impl directory>]
[-copyRef] [-impl <original impl name>]

prj_close
% help prj_close
prj_close - Close the current project
Usage:
prj_close

prj_copy_strategy
% help prj_copy_strategy
prj_copy_strategy - Create a new strategy by copying from an
existing strategy
Usage:
prj_copy_strategy -from <source strategy name> -name <new
strategy name> -file <strategy file name>

prj_create

This command creates a new project inside the current working directory. The
new command can only be used when no other project is currently open.

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The -name <project name> argument specifies the name of the project. This
creates a <project name>.rdf file in the current working directory.

The -dir <project directory> argument defines the directory where project file
.rdf is stored. If this is not specified, the current working directory is used.

The -dev <device name> argument specifies the FPGA family, density,
footprint, performance grade, and temperature grade to generate designs for.
Use the Lattice OPN (Ordering Part Number) for the <device name>
argument.

The -performance <performance grade> argument specifies the device

performance grade explicitly. For iCE40 UltraPlus device, performance grade
cannot be inferred from the device part name such as iCE40UP3K-
UWG30ITR. If no performance grade specified, default performance value is
used.

The -impl <initial implementation name> argument specifies the active

implementation when the project is created. If this is left unspecified, a default
implementation called “Implemenation0” is created.

The -impl_dir <initial implementation directory> argument defines the

directory where temporary files are stored. If this is not specified the current
working directory is used.
% help prj_create
prj_create - Create a new project
Usage:
prj_create -name <project name> [-dir <project directory>]
[-dev <device name>] [-performance <performance grade>] [-impl
<initial implementation name>] [-impl_dir <initial
implementation directory>] [-synthesis <synthesis tool name>]

prj_create_impl

The new implementation will use the current active implementation’s strategy
as the default strategy if no valid strategy is set.
% help prj_create_impl
prj_create_impl - Create a new implementation in the current
project
Usage:
prj_create_impl <new impl name> [-dir <implementation
directory>] [-strategy <default strategy name>] [-synthesis
<synthesis tool name>]

prj_create_reveal_impl
% help prj_create_reveal_impl
prj_create_reveal_impl - Create an reveal implementation from
existed implementation
Usage:
prj_create_reveal_impl [<new reveal impl name>] [-dir <new
impl directory>] -impl <original impl name>

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prj_create_strategy
% help prj_create_strategy
prj_create_strategy - Create a new strategy with default
setting
Usage:
prj_create_strategy -name <new strategy name> -file
<strategy file name>

prj_device
% help prj_device
prj_device - List the device
Usage:
prj_device [-family|-device|-package|-performance|-
operation|-part]
: List the device information of the current
project in family, device, package, performance, operation,
part, ASC sequence Tcl list

prj_disable_source

This command disables the excluded design sources from the current project,
that is, it will activate a source file for synthesis, to be used as a constraint or
for Reveal debugging.
% help prj_disable_source
prj_disable_source - Disable the design sources from the
current project
Usage:
prj_disable_source [-impl <implement name>] <src file> ...

prj_enable_source

This command enables the excluded design sources from the current project,
that is, it will activate a source file for synthesis, to be used as a constraint, or
for Reveal debugging.
% help prj_enable_source
prj_enable_source - Enable the design sources from the current
project
Usage:
prj_enable_source [-impl <implement name>] <src file> ...

prj_get_impl_path
% help prj_get_impl_path
prj_get_impl_path - Return active or given implementation
folder path
Usage:
prj_get_impl_path [-impl <implement>]

prj_get_strategy_value
% help prj_get_strategy_value

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prj_get_strategy_value - Get value of a strategy item

Usage:
prj_get_strategy_value [-strategy <strategy name>] <option
name>

prj_import_strategy
% help prj_import_strategy
prj_import_strategy - Import an existing strategy file
Usage:
prj_import_strategy -name <new strategy name> -file
<strategy file name>

prj_list_source
% help prj_list_source
prj_list_source - List source files in current project
Usage:
prj_list_source [-o <output_file>]

prj_list_strategy

The prj_list_strategy <pattern> specifies a strategy ID by <pattern> which

supports wildcard.
% help prj_list_source
prj_list_source - List source files in current project
Usage:
prj_list_source [-o <output_file>]

prj_open
% help prj_open
prj_open - Open a project file
Usage:
prj_open <project file>

prj_open_milestone
% help prj_open_milestone
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-postsyn boolflag (false) Open post-syn logical netlist
-postmap boolflag (false) Open post-map physical
netlist
-postpar boolflag (false) Open post-par physical
netlist

prj_remove_impl
% help prj_remove_impl

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prj_remove_impl - Delete the specified implementation in the

current project
Usage:
prj_remove_impl <impl name>

prj_remove_source

This command removes the specified source files from the specified
implementation. If an implementation is not listed explicitly the source files are
removed from the active implementation. The source files are not removed
from the file system, they are only removed from consideration in the
specified implementation.
% help prj_remove_source
prj_remove_source - Remove design source from the current
project
Usage:
prj_remove_source [-impl <implement name>] -all
: Remove all the design sources in project
prj_remove_source [-impl <implement name>] <src file> ...
: Remove the specified sources from the current
project

prj_remove_strategy
% help prj_remove_strategy
prj_remove_strategy - Delete an existing strategy
Usage:
prj_remove_strategy <strategy name>

prj_run_bitstream
% help prj_run_bitstream
prj_run_bitstream - Run bitstream process
Usage:
prj_run_bitstream

prj_run_map
% help prj_run_map
prj_run_map - Run map process
Usage:
prj_run_map

prj_run_par
% help prj_run_par
prj_run_par - Run place & route process
Usage:
prj_run_par

prj_run_synthesis
% help prj_run_synthesis

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prj_run_synthesis - Run synthesis process

Usage:
prj_run_synthesis

prj_save

This command updates the project with all changes made during the current
session and the project file is saved.
% help prj_save
prj_save - Save the current project
Usage:
prj_save [project file]

prj_saveas

The -copy_gen argument is used to copy intermediate database files, report

files, and other Radiant-generated files into a new project.
% help prj_saveas
prj_saveas - Save the current project as a new project with
specified name and directory and change current workaround to
the new project
Usage:
prj_saveas -name <new project name> -dir <new project
directory> [-copy_gen]

prj_set_device
% help prj_set_device
prj_set_device - Set the device
Usage:
prj_set_device [-family <family name>] [-device <device
name>] [-package <package name>] [-performance <performance
grade>] [-operation <operation>] [-part <part name>]
: Change the device to the specified family,
device, package, performance, operation, part or ASC

prj_set_impl_opt

If the -rem option is used, the following option names appearing after it will be
removed.

If no argument is used (i.e., “prj_set_impl_opt”), the default is to list all

implementation options.

If only the <option name> argument is used (i.e., “prj_impl option <option
name>), then the value of that option in the project will be returned.

If the <option name> is VerilogStandard, then the valid option value must be
Verilog 95, Verilog 2001 or System Verilog.

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The command will set the option value to the option specified by <option
name>. If the <option value> is empty then the option will be removed and
ignored (e.g., prj_impl option -rem).

The -run_flow argument allows you to switch from the normal mode to an
“initial” incremental flow mode and “incremental” which is the mode you
should be in after an intial design run during the incremental design flow. With
no value parameters specified, -run_flow will return the current mode setting.
% help prj_set_impl_opt
prj_set_impl_opt - List, set or remove implementation options
in the current project
Usage:
prj_set_impl_opt [-impl <implement name>]
: List all the options in the specified
implementation
prj_set_impl_opt [-impl <implement name>] <option name>
[option value list]
: List or set the implementation's option value
prj_set_impl_opt [-impl <implement name>] -append <option
name> <option value>
: Append a value to the specified option value
prj_set_impl_opt [-impl <implement name>] -rem <option
name>...
: Remove the the options in the implementation

prj_set_opt
% help prj_set_opt
prj_set_opt - List, set or remove a project option
Usage:
prj_set_opt
: List all the options in the current project
prj_set_opt <option name> [option value list]
: List or set the option value
prj_set_opt -append <option name> <option value>
: Append a value to the specified option value
prj_set_opt -rem <option name>...
: Remove the options of the current project

prj_set_postscript
% help prj_set_postscript
prj_set_postscript - List or set user Tcl script after running
milestone
Usage:
prj_set_postscript [-impl <implement name>] <milestone
name> <script_file>
: milestone name can be ‘syn’, ‘map’, ‘par’,
‘export’

prj_set_prescript
% help prj_set_prescript
prj_set_prescript - List or set user Tcl script before running
milestone

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Usage:
prj_set_prescript [-impl <implement name>] <milestone name>
<script_file>
: milestone name can be ‘syn’, ‘map’, ‘par’,
‘export’

prj_set_source_format
% help prj_set_source_format
prj_set_source_format - Set a source format
Usage:
prj_set_source_format -src <source name> [-impl <implement
name>] <format>
: Currently, only Verilog or VHDL is supported

prj_set_source_opt
% help prj_set_source_opt
prj_set_source_opt - List, set or remove a source option
Usage:
prj_set_source_opt -src <source name> [-impl <implement
name>]
: List all the options in the specified source
prj_set_source_opt -src <source name> [-impl <implement
name>]
<option name> [option value list]
: List or set the source's option value
prj_set_source_opt -src <source name> [-impl <implement
name>]
-append <option name> <option value>
: Append a value to the specified option value
prj_set_source_opt -src <source name> [-impl <implement
name>]
-rem <option name>...
: Remove the options of the source

prj_set_strategy
% help prj_set_strategy
prj_set_strategy - Associate the strategy with the specified
implementation
Usage:
prj_set_strategy [-impl <implementation name>] <strategy
name>

prj_set_strategy_value
% help prj_set_strategy_value
prj_set_strategy_value - Set value to a strategy item
Usage:
prj_set_strategy_value [-strategy <strategy name>] <option
name=option value> ...

prj_set_top_module

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% help prj_set_top_module
prj_set_top_module - Set top module in the current
implementation
Usage:
prj_set_top_module <top module>

Project Tcl Command Examples

This section illustrates and describes a few samples of Radiant software

project Tcl commands.

Example 1

To create a new project, your command may appear something like the
following which shows the creation of an iCE40 UltraPlus device.
prj_create -name "m" -impl "m" -dev iCE40UP3K-UWG30ITR

Example 2

To save a project and give it a certain name (save as), use the project save
command as shown below:
prj_save "my_project"

To simply save the current project just use the save function with no values:
prj_save

Example 3

To open an existing project, the command syntax would appear with the
absolute file path on your system as shown in the following example:
prj_open "C:/projects/radiant/adder/my_project.rdf"

Example 4

To add a source file, in this case a source LDC file, use the prj_src add
command as shown below and specify the complete file path:
prj_add_source "C:/my_project/radiant/counter/counter.ldc"

Example 5

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In these examples, place & route and synthesis are run.

prj_run_par
prj_run_synthesis

Example 6

To copy another project strategy that is already established in another Radiant

software project from your console, use the prj_copy_strategy copy command
as shown below and specify the new strategy name and the strategy file
name.
prj_copy_strategy -from source_strategy -name new_strategy -
file strategy.stg

Example 7

The prj_add_source command allows you to set a custom, user-defined

option. This -opt argument value, however, cannot conflict with existing
options already in the system, that is, its identifier must differ from system
commands such as "include" and "lib" for example. In addition, a user-defined
option may not affect the internal flow but can be queried for any usage in a
user's script to arrange their design and sources. All user-defined options can
be written to the Radiant software project RDF file.

In the example below, the -opt argument is used as a qualifier to make a

distinction between to .rvl file test cases.
prj_add_source test1.rvl -opt "debug_case=golden_case"
prj_add_source test2.rvl -opt "debug_case=bad_case"

Example 8

After you modify your strategy settings in the Radiant software interface the
values are saved to the current setting via a Tcl command. For example, a
command similar to the following will be called if Synplify frequency and area
options are changed.
prj_set_strategy_value -strategy strategy1 SYN_Frequency=300
SYN_Area=False

Example 9

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To set the top-level module of a project, use the prj_set_impl_opt command

as shown below and specify the implementation name and module name that
will be set as top-level.
prj_set_impl_opt -impl impl1 top count

Example 10

To list all Synplify strategy key-values, use the prj_list_strategy <pattern>

command as shown below:

prj_list_strategy syn_*

Design Tcl Commands

The des commands are used to read or write the Radiant Design database
file (.rdb) and list and report netlist objects such as instance, net, or port. You
can get these commands by using help {des_*}.
The following table provides a listing of all valid Radiant software design-
related Tcl command options and describes option functionality.

Table 32: Design Tcl Commands

Command Description

des_list_attribute List design attributes.

des_list_instance List instance.

des_list_net List all nets.

des_list_port List port.

des_read_udb Read in a .udb file.

des_reload_milestone Reload milestone result.

des_report Report design info.

des_report_flow_status Report design flow status.

des_report_instance Report instance information.

des_report_net Report a net.

des_report_operating_condition Report operating condition.

des_report_port Report port information.

des_set_attribute Set design attributes.

des_set_operating_condition Change operating condition.

des_write_udb Write the design into a .udb file.

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This section displays the usage information of the commands:

des_list_attribute
% help des_list_attribute
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

des_list_instance
% help des_list_instance
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
?objects? string (*) List instances

des_list_net
% help des_list_net
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-clock boolflag (false) List clock nets only
-fanout int (0) List net with # of fanouts >=
specified value
-lsort int (0) Sorting method: 0 - id; 1 -
all pins; 2 - clk pins; 3 - global control pins; 4 - normal
pins
-lsize int (-1) The # of listed nets
?objects? string (*) Net names

des_list_port
% help des_list_port
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
?objects? string (*) List ports

des_read_udb
% help des_read_udb
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-logview string () Logical view UDB file name
-phyview string () Physical view UDB file name

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?udbFileName? string () UDB file name

des_reload_milestone
% help des_reload_milestone
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-force boolflag (false) Force to open the milestone
-inc boolflag (false) Loading the milestone result
incrementally
-postsyn boolflag (false) Open postsyn milestone
-postmap boolflag (false) Open postmap milestone
-postplc boolflag (false) Open postplc milestone
-postrte boolflag (false) Open postrte milestone
-postpar boolflag (false) Open postpar milestone
?udb_name? string () Milestone udb name

des_report
% help des_report
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

des_report_flow_status
% help des_report_flow_status
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

des_report_instance
% help des_report_instance
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-file string () File name
?objects? string () List instances

des_report_net
% help des_report_net
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-file string () File name
?objects? string () Report the given nets

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des_report_operating_condition
% help des_report_operating_condition
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

des_report_port
% help des_report_port
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
?objects? string () List ports

des_set_attribute
% help des_set_attribute
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-impl_dir string () implementation name

des_set_operating_condition
% help des_set_operating_condition
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-temperature int (-1000) Temperature in Celsius
-speed_grade string () Set the design speed grade

des_write_udb
% help des_write_udb
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-w boolflag (false) Force to overwrite the
existing file
-logview boolflag (false) Output logical view
-phyview boolflag (false) Output physical view
?udbFileName? string () UDB file name

Device Tcl Commands

The dev commands are used re used to access or report device information.
You can get these commands by using help {dev_*}.

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The following table provides a listing of all valid Radiant software device-
related Tcl command options and describes option functionality.

Table 33: Device Tcl Commands

Command Description

dev_list_device List device.

dev_list_family List family.

dev_list_operation List operation.

dev_list_package List package.

dev_list_performance List performance grade.

dev_report Report the device info.

This section displays the usage information of the commands:

dev_list_device
% help dev_list_device
dev_list_device - List device
Usage:
dev_list_device -family <family> [-p <pattern>]

dev_list_family
% help dev_list_family
dev_list_family - List family
Usage:
dev_list_family [-p <pattern>]

dev_list_operation
% help dev_list_operation
dev_list_operation - List operation
Usage:
dev_list_operation -family <family> -device <device> -
package <package> -performance <performance>

dev_list_package
% help dev_list_package
dev_list_package - List package
Usage:
dev_list_package -family <family> -device <device> [-p
<pattern>]

dev_list_performance
% help dev_list_performance

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dev_list_performance - List performance grade

Usage:
dev_list_performance -family <family> -device <device> -
package <package>

dev_report
% help dev_report
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

Place & Route Tcl Commands

The par commands are used to run the place & route process. You can run
place & route results from project flow to a non-project flow by using the
par_run command.

Radiant Software Place & Route Tcl Command Descriptions

The following table provides a listing of all valid Radiant software place &
route-related Tcl command options and describes option functionality.

Table 34: Place & Route Tcl Command

Command Description

par_list_option List placement routing options.

par_run Run placement routing.

par_list_option Set placement routing options.

This section displays the usage information of the commands:

par_list_option
% help par_list_option
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

par_run
% help par_run
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----

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(-help gives this help)

par_set_option
% help par_set_option
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
?key_values? list () par_opt option <key, value> pairs

Timing Analysis Tcl Commands

The sta commands are used to run timing analysis interactively, with two
major categories, namely sta_get and sta_report. The sta_get command
returns the value, which can be used in other sta commands or printed out to
the standard output. The sta_report command sends the information to the
standard output.
You can get these commands by using help {sta_*}.
The following table provides a listing of all valid Radiant software timing
analysis-related Tcl command options and describes option functionality.

Table 35: Timing Analysis Tcl Commands

Command Description

sta_get_clocks Get a list of clocks that satisfy the name.

sta_get_coverage Get the timing coverage for connections.

sta_get_info Get information about a clock or a terminal (port/

pin).

sta_get_paths Collect detailed paths for query.

sta_get_slack Get the total negative, worst or terminal slack for

the design.

sta_get_terms Get a list of ports and pins that satisfy the name.

sta_path_info Get the total negative, worst or terminal slack for

the design.

sta_report_clocks Report on a clock or clocks.

sta_report_constraints List timing constraints.

sta_report_timing Report detailed or summary timing.

sta_report_unconstrained List unconstrained ports, pins, or nets.

sta_set_option Change the style of the timing report.

This section displays the usage information of the commands:

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sta_get_clocks

This command provides a list of clocks that satisfy the name including
wildcard characters.
% help sta_get_clocks
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
name string () Name of clocks

sta_get_coverage

This command returns the percent of connections with valid slack. The
removed connections are not part of a complete timing path and are not
considered in the computation. False path on their own do not contribute to
the coverage.
% help sta_get_coverage
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

sta_get_info

This command provides information about a clock or a terminal (port/pin).

A terminal can be a top-level port or a pin of an instance. The Boolean flags

waveform, period and duty_cycle can only be used with the -clock option and
the other flags can only be used with the -term option.
% help sta_get_info
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-clock string () Name of clocks
-waveform boolflag (false) Get the waveform of the clock
-period boolflag (false) Get the period of the clock
-duty_cycle boolflag (false) Get the duty cycle of the
clock
-terminal string () Name of terminal
-isclockpin boolflag (false) Is clock pin?
-isinput boolflag (false) Is input pin?
-isoutput boolflag (false) Is output pin?
-net boolflag (false) Net connected to terminal
-cell boolflag (false) Cell of terminal

sta_get_paths

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% help sta_get_paths
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-n int (-2) Number of paths to report
-from string () Name/s of ports and/or pins
-from_clock string () Name/s of clocks
-to string () Name/s of ports and/or pins
-to_clock string () Name/s of clocks
-hold boolflag (false) Report hold paths

sta_get_slack

The various flags associated with the command determine the returned slack.
% help sta_get_slack
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-tns boolflag (false) Get the total negative setup
or hold slack
-worst boolflag (false) Get the worst setup or hold
slack of the design
-hold boolflag (false) Get hold slack if this flag
is true
-terminal string () Get the worst slack for the
given pin or port. The name has to represent exactly one port
or pin

sta_get_terms

The Boolean flags determine the type of terminals returned.

% help sta_get_terms
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-ports boolflag (false) Return ports only
-pins boolflag (false) Return pins only
name string () Name of terminals

sta_path_info
% help sta_path_info
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-path string () Path in question
-slack boolflag (false) The slack of the path
-constraint boolflag (false) The constraint of the path
-skew boolflag (false) The clock skew -- common
skew not removed

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-launch_clock boolflag (false) The launch clock

-latch_clock boolflag (false) The latch clock?
-levels boolflag (false) Number of logic levels

sta_report_clocks
% help sta_report_clocks
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-clocks string () The clock name

sta_report_constraints

The command returns a list of the sdc commands associated with the design
and constraints generated by the timing engine.
% help sta_report_constraints
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

sta_report_timing

This command takes a list of ports or pins for a detailed report. The summary
option dumps the number of endpoints with negative slack and the total
negative slack. While the endpoints option dumps a table of endpoints and
associated slacks. Hold data is dumped if the hold option is used.
% help sta_report_timing
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-n int (-2) Number of paths to report
-endpoints boolflag (false) Report the endpoints only
-from string () Name/s of ports and/or pins
-from_clock string () Name/s of clocks
-to string () Name/s of ports and/or pins
-to_clock string () Name/s of clocks
-hold boolflag (false) Report hold paths
-summary boolflag (false) Report the timing summary

sta_report_unconstrained

The command writes out unconstrained endpoints indicated by the various

flags. If no flags are provided, all types of unconstrained objects will be
dumped.
% help sta_report_unconstrained
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----

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(-help gives this help)

-n int (10) Need to provide an integer
-start boolflag (false) Reports unconstrained
internal start points
-end boolflag (false) Reports unconstrained
internal endpoints
-io boolflag (false) Reports unconstrained IO
start and end points.
-clock_nets boolflag (false) Report clock nets without
clock definition. Start has no effece on -clock_nets

sta_set_option
% help sta_set_option
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-name string (logical) Use logical or physical
names in reports
-worst_delays boolflag (false) Enable worst case delay if
true

Simulation Libraries Compilation Tcl

Commands
This section provides Simulation Libraries Compilation extended Tcl
command syntax and usage examples.

Simulation Libraries Compilation Tcl Command Descriptions

The following table provides a listing of all valid Radiant software Simulation
Libraries Compilation-related Tcl command options and describes option
functionality.

Note:
Running cmpl_libs may take a long time and may cause the Radiant software to hang.
 It is recommended to run cmpl_libs using the Radiant Tcl Console (Start Menu >
Lattice Radiant Software > Accessories > TCL Console).
or,
 Run cmpl_libs.tcl using the command line console. Refer to Running cmpl_libs.tcl
from the Command Line.

Table 36: Simulation Libraries Compilation Tcl Command

Command Description

cmpl_libs Compile simulation library.

sim_generate_script Generate a simulation script for use with

ModelSim or QuestaSim.

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This section displays the usage information of the commands:

cmpl_libs

The -sim_path argument specifies the path to the simulation tool executable
(binary) folder. This option is mandatory. Currently, only ModelSim and
QuestaSim simulators from Mentor, Xcelium simulator from Cadence and
Active-HDL simulator from Aldec are supported.

Note:
 If you are a Windows user and prefer the \ notation in the path, you must surround
it with {}. And "" or {} will be needed if the path has spaces.
 To execute this script error free, Siemens Questa 2020.4 or a later version should
be used for compilation.

The -sim_vendor argument specifies simulation vendor. This argument is

optional. If you do not use this argument, Mentor is chosen by default, and the
libraries are compiled for ModelSim. If you are using QuestaSim choose
mentor, Xcelium choose cadence, Active-HDL choose aldec for -sim_vendor.

The -device argument specifies the Lattice FPGA device to compile

simulation libraries for. This argument is optional, and the default is to compile
libraries for all the Lattice FPGA devices.

The -target_path argument specifies the target path, where you want the
compiled libraries and modelsim.ini file to be located. This argument is
optional, and the default target path is the current folder.

Note:
 This argument is recommended if you did not change the current folder from the
Radiant software startup (binary) folder, or if the current folder is write-protected.
 If you are a Windows user and prefer the \ notation in the path, you must surround
it with {}. And "" or {} will be needed if the path has spaces.

% cmpl_libs
Usage: cmpl_libs -sim_path <sim_path> [-sim_vendor
{mentor<default>|cadence|aldec}] [-device
{ice40up|lifcl|lfcpnx|lfd2nx|lfmxo5-25|lfmxo5-15d|lfmxo5-
100t|lfmxo5-55t|lavat|ut24c|ut24cp|all<default>}] [-target_path
<target_path>]

sim_generate_script

The sim_generate_script command is used to generate the ModelSim (.mdo)

or QuestaSim template file from the current Radiant project settings, including
RTL, test bench, and other files. If there is no open Radiant project, this
command will fail to run.

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This command does not support modifying the original file list of the Radiant
project. Simulation Wizard does not call this command to generate the .mdo
file. If you want to modify simulation files, you can edit the .mdo file manually.

Note:
The sim_generate_script command does not launch ModelSim as the Simulation
Wizard. However, as long as ModelSim executes the command correctly, it can
generate any type of file as an extension of the script.

% help sim_generate_script
sim_generate_script - Generate a simulation script for use with
ModelSim or QuestaSim
Usage:
sim_generate_script -top <top module> [-stage
<rtl|postsyn|postroute|timing>] [-inst <instance name>]
[-run <timesteps><time_units>|0] [-t
<multiplier><time_unit>] [-w] -o <do file>
-top : top module for simulation.
-stage: (optional) valid types are 'rtl', 'postsyn',
'postroute', 'timing'. 'rtl' is default.
-inst : (optional) specify instance for the associated SDF
file.
-run : (optional) specify the number of timesteps for the
simulation to run.
valid <time_unit> must be one of the fs, ps, ns, us, ms,
sec. '0' means 'run -all'.
-t : (optional) specify the simulator time resolution.
<multiplier> is optional.
<time_unit> must be one of the fs, ps, ns, us, ms, sec.
-w : (optional) allow to overwrite existed simulation do
file.
-o : specify simulation do file path.

Simulation Libraries Compilation Tcl Command Examples

This section illustrates and describes a few examples of Simulation Libraries

Compilation Tcl command.

Example 1

The following command will compile all the Lattice FPGA libraries for both
Verilog and VHDL simulation, and place them under the folder specified by -
target_path. The path to Modelsim is specified by -sim_path.
cmpl_libs -sim_path C:/questasim64_10.4e/win64 -target_path c:/
mti_libs

Example 2

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The following example shows the usage of the sim_generate_script

command.
sim_generate_script -stage rtl -top count -instance UUT -run
100ns -t 1ns -o rtl_test.mdo

Reveal Inserter Tcl Commands

This section provides Reveal Inserter extended Tcl command syntax,
command options, and usage examples.

Reveal Inserter Tcl Command Descriptions

The following table provides a listing of all valid Radiant software Reveal
Inserter-related Tcl command options and describes option functionality.

Table 37: Reveal Inserter Tcl Commands

Command Description

rvl_add_controller Add Controller core.

rvl_add_core Add Inserter core.

rvl_add_serdes Add SerDes core.

rvl_add_te Add Inserter trigger expression.

rvl_add_trace Add Inserter trace signals.

rvl_add_tu Add Inserter trigger unit.

rvl_close_project Close Inserter project.

rvl_del_controller Delete Controller core.

rvl_del_core Delete Inserter core.

rvl_del_serdes Delete Serdes core.

rvl_del_te Delete Inserter trigger expression.

rvl_del_trace Delete Inserter trace signal.

rvl_del_tu Delete inserter trigger unit.

rvl_group_trace Group Inserter trace signals.

rvl_list_core List Inserter core.

rvl_list_te List Inserter trigger expression.

rvl_list_trace List Inserter trace signals.

rvl_list_tu List Inserter trigger units.

rvl_move_trace Move Inserter trace signals.

rvl_new_project Create inserter project.

rvl_open_project Open Inserter project.

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Table 37: Reveal Inserter Tcl Commands

Command Description

rvl_rename_core Rename Inserter core.

rvl_rename_te Rename Inserter trigger expression.

rvl_rename_trace Rename Inserter trace bus.

rvl_rename_tu Rename Inserter trigger unit.

rvl_run_project Run Inserter project.

rvl_save_project Save Inserter project.

rvl_set_controller List or set Controller options.

rvl_set_core Set Inserter core.

rvl_set_serdes List or set SerDes core options.

rvl_set_te Set Inserter trigger expression.

rvl_set_traceoptn List or set Inserter trace options.

rvl_set_trigoptn List or set Inserter trigger options.

rvl_set_tu Set Inserter trigger unit.

rvl_ungroup_trace Ungroup Inserter trace signals.

This section displays the usage information of the commands:

rvl_add_controller
% help rvl_add_controller
rvl_add_controller - Add the Controller Core into current
project
Usage:
rvl_add_controller

rvl_add_core
% help rvl_add_core
rvl_add_core - Add a new core in current project
Usage:
rvl_add_core <core name>

rvl_add_serdes
% help rvl_add_serdes
rvl_add_serdes - Add the Serdes Core into current project
Usage:
rvl_add_serdes

rvl_add_te

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% help rvl_add_te
rvl_add_te - Add a new trigger expression to a debug core in
current project
Usage:
rvl_add_te [-core <core name>] [-ram <EBR|Slice>] [-name
<new TE name>] [-expression <expreesion string>] [-
max_seq_depth <max depth>] [-max_event_count <max event count>]
A default trigger expression name will be created if it's
omitted in command.

rvl_add_trace
% help rvl_add_trace
rvl_add_trace - Add signals in a debug core in current project
Usage:
rvl_add_trace [-core <core name>] [-insert_at <position>]
<signals list>
You can specify an existing trace signal/bus name or a
position number in a trace bus as the inserting position. For
example "signal1", "Bus1<1>", "Bus1<.end.>"...

rvl_add_tu
% help rvl_add_tu
rvl_add_tu - Add a new trigger unit to a debug core in current
project
Usage:
rvl_add_tu [-core <core name>] [-radix <bin|oct|dec|hex>]
[-name <new TU name>] <TU definition>
TU definition format: "{signal list} Operator Value"
Operator must be "==", "!=", ">", ">=", "<", "<=",
".RE."(rising edge), ".FE."(falling edge) and ".SC."(serial
compare).
A default trigger unit name will be created if it's omitted
in command.

rvl_close_project
% help rvl_close_project
rvl_close_project - Close the current reveal insert project
Usage:
rvl_close_project [-force>

rvl_del_controller
% help rvl_del_controller
rvl_del_controller - Remove the Controller Core from current
project
Usage:
rvl_del_controller

rvl_del_core
% help rvl_del_core
rvl_del_core - Remove an existing core from current project

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Usage:
rvl_del_core <core name>

rvl_del_serdes
% help rvl_del_serdes
rvl_del_serdes - Remove the Serdes Core from current project
Usage:
rvl_del_serdes

rvl_del_te
% help rvl_del_te
rvl_del_te - Delete an existing trigger expression in a debug
core in current project
Usage:
rvl_del_te [-core <core name>] [TE name]

rvl_del_trace
% help rvl_del_trace
rvl_del_trace - Delete trace signals in a debug core in current
project
Usage:
rvl_del_trace [-core <core name>] <signals list>

rvl_del_tu
% help rvl_del_tu
rvl_del_tu - Delete an existing trigger unit in a debug core in
current project
Usage:
rvl_del_tu remove [-core <core name>] <TU name>

rvl_group_trace
% help rvl_group_trace
rvl_group_trace - Group specified trace signals in a debug core
in current project into a bus
Usage:
rvl_group_trace [-core <core name>] -bus <bus name>
<signals list>

rvl_list_core
% help rvl_list_core
rvl_list_core - List the default core in current project
Usage:
rvl_list_core

rvl_list_te
% help rvl_list_te

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rvl_list_te - List all trigger expressions in a debug core in

current project
Usage:
rvl_list_te [-core <core name>

rvl_list_trace
% help rvl_list_trace
rvl_list_trace - List all trace signals in a debug core in
current project
Usage:
rvl_trace list_sig [-core <core name>]

rvl_list_tu
% help rvl_list_tu
rvl_list_tu - List all trigger units in a debug core in current
project
Usage:
rvl_list_tu [-core <core name>]

rvl_move_trace
% help rvl_move_trace
rvl_move_trace - Move and rearrange the order of signals in a
debug core in current project
Usage:
rvl_move_trace [-core <core name>] [-move_to <position>]
<signals list>
You can specify an existing trace signal/bus name or a
position number in a trace bus as the new position. For example
"signal1", "Bus1<1>", "Bus1<.end.>"...

rvl_new_project
% help rvl_new_project
rvl_new_project - Create a new reveal insert project
Usage:
rvl_new_project [-overwrite] [<new rvl file name>]

rvl_open_project
% help rvl_open_project
rvl_open_project - Open a reveal insert project file
Usage:
rvl_open_project <rvl file name>

rvl_rename_core
% help rvl_rename_core
rvl_rename_core - Rename an existing core in current project
Usage:
rvl_rename_core <core name> <new name>

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rvl_rename_te
% help rvl_rename_te
rvl_rename_te - Rename an existing trigger expression in a
debug core in current project
Usage:
rvl_rename_te [-core <core name>] <old name> <new name>

rvl_rename_trace
% help rvl_rename_trace
rvl_rename_trace - Change the name of a trace bus in a debug
core in current project
Usage:
rvl_rename_trace [-core <core name>] -bus <bus name> <new
bus name>

rvl_rename_tu
% help rvl_rename_tu
rvl_rename_tu - Rename an existing trigger unit in a debug core
in current project
Usage:
rvl_rename_tu [-core <core name>] <old name> <new name>

rvl_run_project
% help rvl_run_project
rvl_run_project - Run inserting debug core task or DRC checking
on the current reveal insert project
Usage:
rvl_run_project [-save] [-saveAs <file_name>] [-overwrite]
[-drc] [-insert_core <core_name>]...
-save: Save the project before run command
-saveAs: Save as a different file before run command
-overwrite: Overwrite the existing file if the saved as to
file exists already
-drc: Run DRC checking only
-insert_core: Specify the core to be inserted
All cores will be inserted if none is specified.

rvl_save_project
% help rvl_save_project
rvl_save_project - Save the current reveal insert project
Usage:
rvl_save_project [-overwrite] [<new rvl file name>]

rvl_set_controller
% help rvl_set_controller
rvl_set_controller - List or set options of Controller items in
current project
Usage:

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rvl_set_controller [-item
LED|Switch|Register|PLL1|PLL2|...] [-set_opt {opt_list}] [-
set_sig {sig_list}]
You can set opt_list with the following:
Insert=[on|off] for all item
Width=[1..32] for LED and Switch
You can set sig_list with the following:
SWn=signal where n=1 to Width for Switch
LEDn=signal where n=1 to Width for LED
Clock=clk_signal for Register
Clock_enable=en_signal for Register
Wr_Rdn=wr_rdn_signal for Register
Address=addr_bus for Register
WData=wdata_bus for Register
RData=rdata_bus for Register

rvl_set_core
% help rvl_set_core
rvl_set_core - Set a core as the default core in current
project
Usage:
rvl_set_core [core name]

rvl_set_serdes
% help rvl_set_serdes
rvl_set_serdes - List or set options of Serdes debug core
Usage:
rvl_set_serdes [<clk=clock name> [<rst=reset signal,
default value is VLO>]

rvl_set_te
% help rvl_set_te
rvl_set_te - Change an existing trigger expression in a debug
core in current project
Usage:
rvl_set_te [-core <core name>] [-ram <EBR|Slice>] [-
expression <expreesion string>] [-max_seq_depth <max depth>] [-
max_event_count <max event count>] <TE name>

rvl_set_traceoptn

You can set the following option: SampleClk = [signal name].

% help rvl_set_traceoptn
rvl_set_traceoptn - List or set trace options of a debug core
in current project
Usage:
rvl_set_traceoptn [-core <core name>] [option=value]
You can set the following option:
SampleClk = [signal name]
SampleEnable = [on|off]
SampleEnableSig = [signal name] (depend on SampleEnable
is on)

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SampleEnablePri = [Active_Low|Active_High] (depend on

SampleEnable is on)
BufferDepth = [16,32,...,65536]
Implementation = [EBR|DRAM]
Timestamp = [on|off]
TimestampBits = [<BufferDepth bits + 1> - 63] (depend
on Timestamp is on and BufferDepth)
CaptureMode = [single|multiple]
MinimumSamplesPerTrigger (depend on CaptureMode is
multiple and BufferDepth)
IncludeTrigger = [on|off]

rvl_set_trigoptn
% help rvl_set_trigoptn
rvl_set_trigoptn - List or set trigger options of a debug core
in current project
Usage:
rvl_set_trigoptn [-core <core name>] [option=value]
You can set the following option:
DefaultRadix = [bin|oct|dec|hex]
EventCounter = [on|off]
CounterValue = [2,4,8,16,...,65536] (depend on
FinalCounter is on)
TriggerOut = [on|off]
OutNetType = [IO|NET|BOTH] (depend on TriggerOut is on)
OutNetName = [net name] (depend on TriggerOut is on)
OutNetPri = [Active_Low|Active_High] (depend on
TriggerOut is on)
OutNetMPW = [pulse number]\n (depend on TriggerOut is
on)

rvl_set_tu
% help rvl_set_tu
rvl_set_tu - Set a trigger unit in a debug core in current
project
Usage:
rvl_set_tu [-core <core name>] [-radix <bin|oct|dec|hex>] -
name <TU name> [-add_sig <signal list>] [-del_sig <signal
list>] [-set_sig <signal list>][-expr <TU definition>] [-op
operator] [-val value]
TU definition format: "{signal list} Operator Value"
Operator must be "==", "!=", ">", ">=", "<", "<=",
".RE."(rising edge), ".FE."(falling edge) and ".SC."(serial
compare).

rvl_ungroup_trace
% help rvl_ungroup_trace
rvl_ungroup_trace - Ungroup trace signals in a trace bus in a
debug core in current project
Usage:
rvl_ungroup_trace [-core <core name>] <bus name>

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Reveal Inserter Tcl Command Examples

This section illustrates and describes a few samples of Reveal Inserter Tcl
commands.

Example 1

To create a new Reveal Inserter project with the .rvl file extension in your
project directory, use the rvl_project command as shown below using the new
option.
rvl_new_project my_project.rvl

Example 2

The following example shows how to set up TU parameters for Reveal

Inserter:

rvl_set_tu -name TU -add_sig {count[7:0]} -op == -val C3 -radix

Hex

Reveal Analyzer Tcl Commands

This section provides Reveal Analyzer extended Tcl command syntax,
command options, and usage examples.

Reveal Analyzer Tcl Command Descriptions

The following table provides a listing of all valid Radiant software Reveal
Analyzer-related Tcl command options and describes option functionality.

Table 38: Reveal Analyzer Tcl Commands

Command Description

rva_add_token Add Analyzer token.

rva_add_tokenset Add Analyzer token set.

rva_close_controller Close Controller connection.

rva_close_project Close Analyzer project.

rva_del_token Delete Analyzer token.

rva_del_tokenset Delete Analyzer token set.

rva_export_project Export Analyzer waveform.

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Table 38: Reveal Analyzer Tcl Commands

Command Description

rva_export_tokenset Export Analyzer token set.

rva_get_trace List Analyzer trace signals.

rva_import_tokenset Import Analyser token set.

rva_manualtrig Manual Trigger to capture data.

rva_new_project Create Analyzer project.

rva_open_controller Open Controller connection.

rva_open_project Open Analyzer project file.

rva_read_controller Read data from 32-bit address in hex.

rva_rename_te Rename Analyzer trigger expression.

rva_rename_tu Rename Analyzer trigger unit.

rva_run Run Analyzer project.

rva_run_controller Run Controller command.

rva_save_project Save the current Analyzer project.

rva_set_controller Set Controller options.

rva_set_core Set Analyzer core.

rva_set_project Set Analyzer options.

rva_set_te Set Analyzer trigger expression.

rva_set_token Set Analyzer token.

rva_set_tokenset Set Analyzer token set.

rva_set_trigoptn Set Analyzer trigger options.

rva_set_tu Set Analyzer trigger unit.

rva_stop Stop Analyzer project without capturing data.

rva_target_controller Set Controller core as target.

rva_write_controller Write Controller data to 32-bit address in hex.

This section displays the usage information of the commands:

rva_add_token
% help rva_add_token
rva_add_token - Add a token with new name and value in a
specific token set
Usage:
rva_add_token <tokenset name> <name=value>

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rva_add_tokenset
% help rva_add_tokenset
rva_add_tokenset - Add a token set
Usage:
rva_add_tokenset [-tokenset <tokenset name>] [-bits <token
bits>] [-token <name=value>]
-tokenset: Set token set name
-bits: Set token set bits
-token: Add extra token
If no arguments specified, add a token set with default
name and bits.

rva_close_controller
% help rva_close_controller
rva_close_controller - Close Controller connection to Lattice
device after read/write finished
Usage:
rva_close_controller

rva_close_project
% help rva_close_project
rva_close_project - Close the current Reveal Analyzer project
Usage:
rva_close_project

rva_del_token
% help rva_del_token
rva_del_token - Delete a specific token in a specific token set
Usage:
rva_del_token <tokenset name> <token name>

rva_del_tokenset
% help rva_del_tokenset
rva_del_tokenset - Delete the specific token set
Usage:
rva_del_tokenset <tokenset name>

rva_export_project
% help rva_export_project
rva_export_project - Export waveform in VCD or TEXT from the
current Reveal Analyzer project
Usage:
rva_export_project <-vcd|-txt> <file name> [option]
You can set the following option:
-vcd <file name> [module <title>]
-txt <file name> [-siglist <signal list>]
By default, the module title is "<unknown>" and all signals
are exported.

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rva_export_tokenset
% help rva_export_tokenset
rva_export_tokenset - Export all token set to a specific file
Usage:
rva_export_tokenset <file name>

rva_get_trace
% help rva_get_trace
rva_get_trace - Lists all trace signals in Analyzer core
Usage:
rva_get_trace

rva_import_tokenset
% help rva_import_tokenset
rva_import_tokenset - Import and merge all token set from a
specific file
Usage:
rva_import_tokenset <file name>

rva_manualtrig
% help rva_manualtrig
rva_manualtrig - Manual Trigger Reveal Analyzer to capture data
Usage:
rva_manualtrig

rva_new_project
% help rva_new_project
rva_new_project - Create a new Reveal Analyzer project
Usage:
rva_new_project -rva <file name> -rvl <file name> -dev
<val> -cable <val> -port <val> [-xcf <file name>]
-rva: Set the new rva file name
-rvl: Set the associated rvl file name
-dev: Set the device name
-cable: Set type of cable as USB or USB2
-port: Set logical port of cable as integer
-xcf: Optional xcf file name for multiple device chain

rva_open_controller
% help rva_open_controller
rva_open_controller - Open Controller connection to Lattice
device before read/write began
Usage:
rva_open_controller

rva_open_project
% help rva_open_project
rva_open_project - Open a Reveal Analyzer project file

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Usage:
rva_open_project <rva file name>

rva_read_controller
% help rva_read_controller
rva_read_controller - Read data from 32bit address in hex
Usage:
rva_read_controller -addr <addr32>

rva_rename_te
% help rva_rename_te
rva_rename_te - Rename an existing trigger expression in a
debug core in current project
Usage:
rva_rename_te <name> <new name>

rva_rename_tu
% help rva_rename_tu
rva_rename_tu - Rename an existing trigger unit in a debug core
in current project
Usage:
rva_rename_tu <name> <new name>

rva_run
% help rva_run
rva_run - Run Reveal Analyzer until trigger condition to
capture data
Usage:
rva_run

rva_run_controller
% help rva_run_controller
rva_run_controller - Run command for Virtual LED, Virtual
Switch, User Memory and Hard IP Run command for User Control
Register and User Status Register
Usage:
rva_run_controller -read_led|-read_switch|-write_switch
<data>|-dump_memfile <mem_file>|-load_memfile <mem_file>|
-read_ip <ipname>|-write_ip <ipname>|-
eye_monitor <ipname>|
-read_status <regname>|-read_control
<regname>|-write_control <regname> -data <data>|-toggle_control
<regname>|
-dump_status <reg_file>|-dump_control
<reg_file>|-load_control <reg_file>
-read_led: Read data from Virtual LED
-read_switch: Read data from Virtual Switch
-write_switch: Write data to Virtual Switch
-dump_memfile: Dump data from User Memory to mem_file
-load_memfile: Load data from mem_file to User Memory

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-read_ip: Read data from Hard IP register of ipname

-write_ip: Write data to Hard IP register of ipname
-eye_monitor: Run Eye-Opening Monitor for PCS channel of
ipname
-read_status: Read data from User Status Register of
regname
-read_control: Read data from User Control Register of
regname
-write_control: Write data to User Control Register of
regname
-toggle_control: Toggle data bit in User Control Register
of regname
-dump_status: Dump data from User Status Register to
reg_file
-dump_control: Dump data from User Control Register to
reg_file
-load_control: Load data from reg_file to User Control
Register

rva_save_project
% help rva_save_project
rva_save_project - Save the current Reveal Analyzer project
Usage:
rva_save_project [<new rva file name>]

rva_set_controller
% help rva_set_controller
rva_set_controller - Set the options for Controller core
Usage:
rva_set_controller [-option <value>]
-cable_type: Set type of cable as USB or USB2
-cable_port: Set logical port of cable as integer
If no arguments specified, then return list of options and
values.

rva_set_controller -hard_ip <ipname> [-option <value>]

-hard_ip: Set options of DPHY1, DPHY2, I2CFIFO1, SGMIICDR1,
SGMIICDR2, PCIELL1, PCSCH1 to PCSCH8
If no option/value specified, then return list of options
and values.

DPHY1, DPHY2 options and values:

-high_speed_select: Set value as "1.5Gbps and
below","2.5Gbps"
-bypass_pll_clock: Set value as Enabled,Disabled
-pll_cn_counter: Set value as integer from 0 to 31
-pll_cm_counter: Set value as integer from 0 to 255
-pll_co_counter: Set value as integer from 0 to 7

I2CFIFO1 options and values:

-generic_call_response: Set value as Enabled,Disabled
-sda_input_delay: Set value as Enabled,Disabled
-sda_output_delay: Set value as Enabled,Disabled
-fifo_mode_select: Set Value as "Register Mode","FIFO Mode"
-fifo_clock_stretching: Set value as Enabled,Disabled

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-fifo_almost_full_value: Set value as integer from 0 to 31

-fifo_sleep_clock: Set value as Enabled,Disabled
-slave_address_match_wakeup: Set value as Enabled,Disabled
-fifo_almost_full_wakeup: Set value as Enabled,Disabled
-master_read_complete_wakeup: Set value as Enabled,Disabled

SGMIICDR1, SGMIICDR2 options and values:

-cdr_loss_of_lock: Set value as "Lock=+/-1000ppm x2
Unlock=+/-1500ppm x2",
"Lock=+/-2000ppm x2 Unlock=+/-2500ppm
x2",
"Lock=+/-4000ppm Unlock=+/-7000ppm",
"Lock=+/-300ppm Unlock=+/-450ppm"
-loopback_control: Set value as Disabled,"Bit Clock to
IO","Serial Data to IO"

PCIELL1 options and values:

-swing_control: Set value as full,reduced

PCSCH1 to PCSCH8 options and values:

-tx_differential_amplitude: Set value as
1000mV,900mV,800mV,700mV,600mV,500mV,400mV,300mV,200mV,100mV,0m
V
-tx_output_termination: Set value as "100 ohm","150 ohm"
-tx_postcursor_ratio: Set value as integer from 0 to 63 of
128th
-tx_precursor_ratio: Set value as integer from 0 to 63 of
128th
-tx_invert_polarity: Set value as on,off
-rx_input_termination: Set value as "100 ohm","150 ohm"
-rx_equalization: Set value as "RL2plus 8GT/s","RL2plus
5GT/s","RL2plus 2.5GT/s",
"SS_LMS 8GT/s","SS_LMS 5GT/s","SS_LMS
2.5GT/s"
-rx_invert_polarity: Set value as on,off
-loopback_mode: Set value as Disabled,"PMA Near-End Serial
Loopback","PMA Far-End Parallel Loopback",
"8B/10B PCS Near-End Parallel
Loopback","8B/10B PCS Far-End Parallel Loopback",
"64B/66B PCS Loopback Path A","64B/66B PCS
Loopback Path B","64B/66B PCS Loopback Path C"
-reset_tx_mpcs: Set value as on,off
-reset_rx_mpcs: Set value as on,off
-reset_tx_pll: Set value as on,off
-reset_rx_pll: Set value as on,off
-force_tx_driver: Set value as on,off
-force_rx_driver: Set value as on,off
-eye_quality: Set quality of eye diagram as high, normal,
low

rva_set_core
% help rva_set_core
rva_set_core - Set a core as the default core in current
project
Usage:
rva_set_core [-name <name>] [-run <on|off>]
-name: Select core. Needed for other actions

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-run: Turn run option on/off for core

If no arguments specified, then return list of core.

rva_set_project
% help rva_set_project
rva_set_project - Set the current Reveal Analyzer project
options
Usage:
rva_set_project [-frequency <val>] [-period <val>] [-
tckdelay <val>] [-cabletype <val>] [-cableport <val>]
-frequency: Set the frequency value for sample clockin MHz
-period: Set the period value for sample clock in ns or ps
-tckdelay: Set the TCK clock pin pulse width delay value
-cabletype: Set the type of cable. Values must be
"LATTICE","USB","USB2"
-cableport: Set the port number as integer >=0

rva_set_te
% help rva_set_te
rva_set_te - Change an existing trigger expression in a debug
core in current project
Usage:
rva_set_te [-name <name>] [-expression <expression list>]
[-enable <on|off>]
-name: Select TE. If no options specified, return options
and values for the selected TE.
-expression: Set TE expression
-enable: Enable/disable TE
If no arguments specified, then return list of TE.

rva_set_token
% help rva_set_token
rva_set_token - Select a specific token in a specific token set
Usage:
rva_set_token <tokenset name> <token name> -name <new token
name> -value <new token value>
-name: Set token name
-value: Set token value

rva_set_tokenset
% help rva_set_tokenset
rva_set_tokenset - Select a specific token set
Usage:
rva_set_tokenset <tokenset name> [-name <new token set
name>] [-bits <new token bits>]
-name: Rename a token set
-bits: Set number of bits in token

rva_set_trigoptn
help rva_set_trigoptn

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rva_set_trigoptn - Set trigger options of Analyzer core in

current project
Usage:
rva_set_trigoptn [-teall <AND|OR>] [-finalcounter
<on|off>] [-finalcountervalue <val>] [-samples <val>] [-
numtriggers <val>] [-position <pre|center|post|val>]
-teall: Set AND ALL or OR ALL for all TE
-finalcounter: Turn final trigger counter on/off
-finalcountervalue: Set final trigger counter value
-samples: Set number of samples to capture
-numtriggers: Set number of triggers to capture
-position: Set trigger position to pre-selected or user
value
If no arguments specified, then return list of options.

rva_set_tu
% help rva_set_tu
rva_set_tu - Set a trigger unit in a debug core in current
project
Usage:
rva_set_tu [-name <name>] [-operator {== | != | > | >= | <
| <= | "rising edge" | "falling edge"}][-value <value>] [-radix
{bin | oct | dec | hex | <token>}]
-name: Select TU. If no options specified, return options
and value for the selected TU.
-operator: Sets TU comparison operator
-value: Sets TU value
-radix: Sets TU radix
If no arguments specified, return list of TU.

rva_stop
% help rva_stop
rva_stop - Stop Reveal Analyzer without capturing data
Usage:
rva_stop

rva_target_controller

Set Controller core as target. before read/write begins.

% help rva_target_controller
rva_target_controller - Set Controller core as target before
read/write began
Usage:
rva_target_controller

rva_write_controller
% help rva_write_controller
rva_write_controller - Write data to 32bit address in hex
Usage:
rva_write_controller -addr <addr32> -data <data>

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Reveal Analyzer Tcl Command Examples

This section illustrates and describes a few samples of Reveal Analyzer Tcl
commands.

Example 1

The following command line example shows how to specify a new project that
uses a parallel cable port.
rva_new_project –rva untitled –rvl "count.rvl" –dev "LFXP2-
5E:0x01299043" –port 888 –cable LATTICE

Example 2

The following example shows how to set up TU parameters for Reveal

Analyzer:
rva_set_tu -name TU1 -operator == -value 10110100 -radix bin

Power Calculator Tcl Commands

This section provides Power Calculator extended Tcl command syntax,
command options, and usage examples.

Power Calculator Tcl Command Descriptions

The following table provides a listing of all valid Radiant software Power
Calculator-related Tcl command options and describes option functionality.

Table 39: Power Calculator Tcl Commands

Command Description

pwc_add_inactiveimpl Add inactive implementation name.

pwc_add_ipblock Add IP Block row.

pwc_calculate Run power calculation for current project.

pwc_close_project Close the current project.

pwc_gen_htmlreport Generate HTML report and write to file.

pwc_gen_report Generate text report and write to file.

pwc_new_project Create a new project.

pwc_open_project Open a project file.

pwc_remove_ipblock Remove IP Block row.

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Table 39: Power Calculator Tcl Commands

Command Description

pwc_save_project Save the current project.

pwc_set_af Set default activity factor.

pwc_set_afpervcd Open vcd file and set frequency and activity factor.

pwc_set_ambienttemp Set ambient temperature value.

pwc_set_device Set device information.

pwc_set_estimation Sets estimated routing option.

pwc_set_freq Set frequency.

pwc_set_ipblock Set IP Block row.

pwc_set_processtype Set device power process type.

pwc_set_supply Set multiplication factor and voltage of named

power supply.

pwc_set_thetaja Set user defined theta JA.

This section displays the usage information of the commands:

pwc_add_inactiveimpl
% help pwc_add_inactiveimpl
pwc_add_inactiveimpl - Add inactive implementation name
Usage:
pwc_add_inactiveimpl [<implementation name>]

pwc_add_ipblock
% help pwc_add_ipblock
pwc_add_ipblock - Add IP Block row
Usage:
pwc_add_ipblock -iptype <iptype name>

pwc_calculate
% help pwc_calculate
pwc_calculate - Run power calculation for current project
Usage:
pwc_calculate

pwc_close_project
% help pwc_close_project
pwc_close_project - Close the current project
Usage:
pwc_close_project

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pwc_gen_htmlreport
% help pwc_gen_htmlreport
pwc_gen_htmlreport - Generate HTML report and write to file
Usage:
pwc_gen_htmlreport <report file>

pwc_gen_report
% help pwc_gen_report
pwc_gen_report - Generate text report and write to file
Usage:
pwc_gen_report <report file>

pwc_new_project
% help pwc_new_project
pwc_new_project - Create a new project
Usage:
pwc_new_project <project file>

pwc_open_project
% help pwc_open_project
pwc_open_project - Open a project file
Usage:
pwc_open_project <project file>

pwc_remove_ipblock
% help pwc_remove_ipblock
pwc_remove_ipblock - Remove IP Block row
Usage:
pwc_remove_ipblock -iptype <iptype name> -matchkeys {<key1>
<value1>}+

pwc_save_project
% help pwc_save_project
pwc_save_project - Save the current project
Usage:
pwc_save_project <project file>

pwc_set_af
% help pwc_set_af
pwc_set_af - Set default activity factor
Usage:
pwc_set_af <activity factor>

pwc_set_afpervcd

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% help pwc_set_afpervcd
pwc_set_afpervcd - Open vcd file and set frequency and activity
factor
Usage:
pwc_set_afpervcd <vcd file>

pwc_set_ambienttemp
% help pwc_set_ambienttemp
pwc_set_ambienttemp - Set ambient temperature value
Usage:
pwc_set_ambienttemp <ambient temperature>

pwc_set_device
% help pwc_set_device
pwc_set_device - Set device information
Usage:
pwc_set_device -family <family name>
: Set family
pwc_set_device -device <device name>
: Set device
pwc_set_device -package <package name>
: Set package
pwc_set_device -speed <speed name>
: Set speed
pwc_set_device -operating <operating name>
: Set operating
pwc_set_device -part <part name>
: Set part

pwc_set_estimation
% help pwc_set_estimation
Usage:
pwc_set_estimation <estimated routing option>

pwc_set_freq
% help pwc_set_freq
pwc_set_freq - Set frequency
Usage:
pwc_set_freq <frequency>
: Set default frequency
pwc_set_freq <clock> <frequency>
: Set clock frequency
pwc_set_freq -freq <frequency> -usefreqtwr <0|1> -
freqtwropt <min|pref|trace>
: Set frequency by importing timing report

pwc_set_ipblock
% help pwc_set_ipblock
pwc_set_ipblock - Set IP Block row
Usage:

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pwc_set_ipblock -iptype <iptype name> -matchkeys {<key1>

<value1>}+ -setkey <key> <value>

pwc_set_processtype
% help pwc_set_processtype
pwc_set_processtype - Set device power process type
Usage:
pwc_set_processtype <process type>

pwc_set_supply
% help pwc_set_supply
pwc_set_supply - Set multiplication factor and voltage of named
power supply
Usage:
pwc_set_supply -type <type> -voltage <voltage> -dpm <dpm>

pwc_set_thetaja
% help pwc_set_thetaja
pwc_set_thetaja - Set user defined theta JA
Usage:
pwc_set_thetaja <theta JA>

Power Calculator Tcl Command Examples

This section illustrates and describes a few samples of Power Calculator Tcl
commands.

Example 1

The follow command below creates a PWC project (.pcf) file namced “abc.pcf”
from an input UDB file named “abc.UDB”:
pwc_new_project abc.pcf -udb abc.udb

Example 2

To set the default frequency to, for example, 100 Mhz:

pwc_set_freq 100

Example 3

The command below saves the current project to a new name:

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pwc_save_project newname.pcf

Example 4

To create an HTML report, you would run a command like the one shown
below:
pwc_gen_htmlreport c:/abc.html

Programmer Tcl Commands

The Programmer Tcl Commands are only supported in Standalone
Programmer. For more information, refer to the Using Programmer Tcl
Commands section in User Guides > Programming the FPGA > Using the
Radiant Programmer > Using Programmer Tcl Commands.

Engineering Change Order Tcl

Commands
This section provides Engineering Change Order (ECO) extended Tcl
command syntax, command options, and usage examples.

ECO Tcl Command Descriptions

The following table provides a listing of all valid Radiant software ECO-related
Tcl command options and describes option functionality.

Table 40: ECO Tcl Commands

Command Description

eco_config_block Config general IP.

eco_config_memory Update memory initial value.

eco_config_sysio Config sysio setting.

eco_save_design Save design in memory to disk.

This section displays the usage information of the commands:

eco_config_block
% help eco_config_block
eco_config_block - Config general IP
Usage:

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eco_config_block -comp <comp_name> {<key=value>}...

eco_config_memory
% help eco_config_memory
eco_config_memory - Update memory initial value
Usage:
eco_config_memory -mem_id <memory_id> {-init_file
<mem_file> -format HEX|BIN|ADDR} | -all_0 | -all_1

eco_config_sysio
% help eco_config_sysio
eco_config_sysio - Config sysio setting
Usage:
eco_config_sysio -comp <comp_name> {<key=value>}...

eco_save_design
% help eco_save_design
eco_save_design - Save cuurent design to disk
Usage:
eco_save_design [-udb <udb_file>]

ECO Tcl Command Examples

This section illustrates and describes a few samples of ECO Tcl commands.

Example 1

The following demonstrates the sysio command.

eco_config_sysio -comp {data}
{clamp=OFF;diffdrive=NA;diffresistor=OFF;drive=2;glitchfilter=O
FF;hysteresis=NA;opendrain=OFF;pullmode=NONE;slewrate=SLOW;term
ination=OFF;vref=OFF}

Example 2

The following demonstrates the memory command.

eco_config_mem -mem_id {mem} -init_file {D:/mem/init_hex.mem} -
format HEX

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IP Version Update Tcl Commands

This section provides the IP upgrade version Tcl command syntax, command
options, and usage examples.

IP Version Update Command Descriptions

The following table provides a listing of all valid Radiant software IP version
update-related Tcl command options and describes option functionality.

Table 41: IP Version Update Commands

Command Description

ip_catalog_list List supported IPs in local.

ip_upgrade Update all .ipx resource files with the new IP

version in the Radiant project.

This section displays the usage information of the commands:

ip_catalog_list
% help ip_catalog_list
ip_catalog_list - Return a list of IP, it contains the IP from
Radiant install package, IP server and customer's packaged IP.
Usage:
ip_catalog_list [-name <IP name>]

ip_upgrade
% help ip_upgrade
ip_upgrade - Upgrade and regenerate the IP in a project with a
more recent version
Usage:
ip_upgrade -all [-force_update]
: Upgrade all IPs to the latest version that can be
found locally.
ip_upgrade -ipx <ipx file path> [-force_update] [-version
<version number>]
: Upgrade one IP to the latest version or specified
version that can be found locally.

-force_update: Upgrade the ipx file with latest version

regardless of whether it is compatible or not, which may cause
generation errors.

IP Version Update Command Examples

This section illustrates and describes few samples of ip_upgrade Tcl

commands.

Example 1

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The following demonstrates the ip_upgrade to update one ipx file command.
ip_upgrade -ipx {D:\temp\ip_upgrade_test\i3c102\i3c102.ipx}

Example 2

The following demonstrates the ip_upgrade to update all ipx files command.
ip_upgrade -all

Message Control Tcl Commands

This section provides Message Control extended Tcl command syntax,
command options, and usage examples.

Message Control Tcl Command Descriptions

The following table provides a listing of all valid Radiant software message
control-related Tcl command options and describes option functionality.

Table 42: Message Control Tcl Commands

Command Description

msg_clean Reset the setting of promoted and disabled

message(s) from the current project.

msg_demote Demote the message from the current project.

msg_disable Disable the message from the current project.

msg_list_status List all promoted or disabled messages from the

current project.

msg_load Load the setting of all promoted and disabled

messages from the file. Default is promote.xml.

msg_promote Promote the message from the current project.

msg_save Save the setting of all promoted and disabled

messages to the file.

msg_suppress Suppress the message from the current project.

Note:
Run the msg_save command after entering msg_promote. Otherwise, the information
will not be saved.

This section displays the usage information of the commands:

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msg_clean
% help msg_clean
msg_clean - Reset the setting of promoted and disabled
message(s) from the current project
Usage:
msg_clean <message Id>|-all

msg_demote
% help msg_demote
msg_demote - Demote the message from the current project
Usage:
msg_demote <message Id>

msg_disable
% help msg_disable
msg_disable - Disable the message from the current project
Usage:
msg_disable <message Id>

msg_list_status
% help msg_list_status
msg_list_status - List all promoted or disabled messages from
the current project
Usage:
msg_list_status [-promoted|-disabled]

msg_load
% help msg_load
msg_load - Load the setting of all promoted and disabled
messages from the file, default is promote.xml
Usage:
msg_load [<message xml or pmt file>]

msg_promote
% help msg_promote
msg_promote - Set the message promotion type, 0is error, 1 is
critical, 2 is warning, and 3 is info
Usage:
msg_promote <message Id> [-type <0|1|2|3>]

msg_save

Default is promote.xml.
% help msg_save

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msg_save - Save the setting of all promoted and disabled

messages to the file, default is promote.xml
Usage:
msg_save [<message xml or pmt file>]

msg_suppress
%help msg_suppress
msg_suppress - Suppress the message from the current project,
set maximum display count
Usage:
msg_suppress <message Id> -cnt <0|10>
: Set maximum display count for the
message, 0 is disabled, and 10 means only display the message
10 times

Message Control Tcl Command Examples

This section illustrates and describes a few samples of Message Control Tcl
commands.

Example 1

The following demonstrates how to promote the message to error from the
current project.
msg_promote 70001926 -type 0

Example 2

The following demonstrates how to show all promoted messages from the
current project.
msg_list_status –promoted

Example 3

The following demonstrates how to save the settings of all promoted and
disabled messages to defaut promote.xml file.
msg_save

Placement Tcl Commands

The plc commands are used for automatic/interactive placement.

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Placement Tcl Command Descriptions

The following table provides a listing of all valid Radiant software placement-
related Tcl command options and describes option functionality.

Table 43: Placement Tcl Commands

Command Description

plc_list_option List placement options.

plc_output_instance_location Output instance locations in LDC format.

plc_report Report placement information.

plc_run Run placement tool.

plc_set_option Set placement options.

This section displays the usage information of the commands:

plc_list_option
% help plc_list_option

Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

plc_output_instance_location
% help plc_output_instance_location
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-all boolflag (false) All instance types
-pio boolflag (false) PIO instance types
-dsp boolflag (false) DSP instance types
-ebr boolflag (false) EBR instance types
-slice boolflag (false) Slice instance types
-all_constraint boolflag (false) Include all constraints
-file string () File name
?inst_names? list () Instance names

plc_report
% help plc_report
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

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plc_run
% help plc_run
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

plc_set_option
% help plc_set_option
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
?key_values? list () Placement <key, value> pairs

Routing Tcl Commands

The rte commands are used for automatic/interactive routing.

Routing Tcl Command Descriptions

The following table provides a listing of all valid Radiant software routing-
related Tcl command options and describes option functionality.

Table 44: Routing Tcl Commands

Command Description

rte_list_option List routing option.

rte_report Report routing results.

rte_run Run the routing tool.

rte_set_option Set routing options.

This section displays the usage information of the commands:

rte_list_option
% help rte_list_option
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

rte_report
% help rte_report

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Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
-net boolflag (false) Report the nets

rte_run
% help rte_run
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

rte_set_option
% help rte_set_option
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
?key_values? list () Routing options

Bitstream Generation Tcl Commands

The bit command is used for bitstream generation.

Bitstream Generation Tcl Command Descriptions

The following table provides a listing of all valid Radiant software bitstream
generation-related Tcl command options and describes option functionality.

Table 45: Bitstream Generation Tcl Commands

Command Description

bit_generate Generate a bitstream file.

bit_list_option List bit generation options.

bit_set_option Set bit generation options.

This section displays the usage information of the commands:

bit_generate
% help bit_generate
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

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-w boolflag (false) Force to overwrite the

existing file
?file_name? string () The bitstream file name

bit_list_option
% help bit_list_option
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)

bit_set_option
% help bit_set_option
Usage information:
Var/FlagName Type Value Help
------------ ---- ----- ----
(-help gives this help)
?key_values? list () bitgen options

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Chapter 10

Advanced Topics

This chapter explains advanced concepts, features and operational methods

for the Radiant software.

Shared Memory Environment

The Radiant software design environment uses a shared memory
architecture. Shared memory allows all internal tool views to access the same
image of the design at any point in time. Understanding how shared memory
is being used can give you insight into managing the environment for optimum
performance, especially when your design is large.

There is one shared database that contains the device, design, and constraint
information in system memory.

Generating the hierarchy of your design uses an additional database separate

from the primary shared memory database.

External tools referenced from within the Radiant software, such as those for
synthesis and simulation, use their own memory in addition to what is used by
the Radiant software.

Because it is accessing shared memory, the initial tool view launch will take
longer than the launch of subsequent views.

Clear Tool Memory

The “Clear Tool Memory command, available from the Tools menu, clears the
device, design, and constraint information from system memory. Clearing the
tool memory can speed up memory-intensive processes such as place and
route. When your design is very large, it is good practice to clear memory
prior to running place and route.

If you have open tool views that will be affected by clearing the tool memory, a
confirmation dialog box will open to give you the opportunity to cancel the
memory clear.

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Figure 85: Clear Tool Memory Dialog

Environment and Tool Options

The Radiant software provides many environment control and tool view
display options that enable you to customize your settings. Choose Tools >
Options to access these options.

Figure 86: Tools Options

The Options dialog box is organized into functional folders.

Commonly configured items include:

 General settings -- allows you to set some common options, including.

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 Startup – enables you to configure the default action at startup and

also to control the frequency of checking for software updates.
 File Associations – allows you to set the programs to be associated
with different file types based on the file extensions.
 Directories – Set directory location for Synthesis and Simulation tools.
 Network Settings – Apply a proxy server and specify a host and port.
 Color settings -- allows you to set colors for such GUI features as fonts
and backgrounds for various Radiant software tools. You can also change
the Theme color of the Radiant software (Dark or Light) using the Themes
drop-down menu.
 Tools settings -- allows you to set options for various Radiant software
tools, including the Device Constraint Editor, Netlist Analyzer, Timing
Constraint Editor, and Source Editor. You can also set the constraint
design rule check (DRC) time to real time, prior to saving or when
launching a tool.

Batch Tool Operation

The core tools in the FPGA implementation design flow can all be run in batch
mode using command-line tool invocation or scripts. For detailed information,
refer to the Radiant Software Help. See Reference Guides > Command
Line Reference Guide.

Tcl Scripts
The Radiant Extended Tcl language enables you to create customized scripts
for tasks that you perform often in the Radiant software. Automating these
operations through Tcl scripts not only saves time, but also provides a uniform
approach to design. This is especially useful when you try to find an optimal
solution using numerous design implementations.

Creating Tcl Scripts from Command

History
A good first step in Tcl programming is to create a Tcl script by saving some
command history and then modifying it as needed. This allows you to get
started by using existing command information.

To create a Tcl command script using command history:

1. In the Tcl Console window, perform a reset command so that your script
won’t contain any of the actions that may have already been executed.
reset

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2. Open the project and perform the commands that you want to save as a
script.
3. Optionally, enter the history command in the Tcl Console window to
ensure that the commands you wish to save are in the console’s memory.
In the Tcl Console window type
save_script <filename.tcl>
The <filename.tcl> can be any file identifier that has no spaces and
contains no special characters except underscores. For example,
myscript.tcl or design_flow_1.tcl are acceptable save_script values, but
my$script or my script are invalid. A file name with an extension of .ext
will not work.
The <filename.ext> entry can be preceded with an absolute or relative
path. Use the "/" (i.e. forward slash) symbol to delimit the path elements.
If the path is not specified, the script is saved in the current working
directory. The current working directory can be determined by using the
TCL pwd command.
4. Navigate to your script file and use the text editing tool of your choice to
make any necessary changes, such as deleting extraneous lines or
invalid arguments.

In most cases, you will need to edit the script you saved and take out any
invalid arguments or any commands that cannot be performed in the Radiant
software environment due to a conflict or exception. You will likely have to
revisit this step later if after running your script, you experience any run errors
due to syntax errors or technology exceptions.

Creating Tcl Scripts from Scratch

Tcl commands can be written directly into a script file. You can use any text
editor, such as Notepad or vi, to create a file and type in the Tcl commands.

Sample Tcl Script

The following Tcl example shows a simple script that opens a project, runs the
entire design flow through the Place & Route process, and then closes the
project. A typical script would probably contain more steps, but you can use
this example as a general guideline.
prj_project open "C:/lscc/Radiant/counter/counter.rdf"
prj_run PAR -impl counter -forceAll
prj_project close
save_script c:/lscc/radiant/examples/counter/myscript2.tcl

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Running Tcl Scripts

You can run scripts from the Radiant software integrated Tcl Console whether
your project is opened or not. You can also run scripts from the external Tcl
Console prompt window. The following example procedure uses the
integrated Tcl Console and the sample Tcl script from the previous section:

To run a Tcl script that opens a project, runs processes and closes the
project:
1. Open the Radiant software but do not open your project. If your project is
open, choose File > Close Project.
2. If you are using the Radiant software main window, click the small arrow
pane switch in the bottom of the Radiant software main window, and then
click on the Tcl Console tab in the Output area at the bottom to open the
console.
3. If there are previously issued commands in the console, type reset in the
console command line to refresh your session and clear out all previous
commands.
reset
4. Use the TCL source command to load and run your TCL script. Since it’s
the only argument, the source command requires the filename of the
script you want to load and run. Prefix the script file name with any
required relative or absolute path information. To run the example script
shown in the previous section use the following:
source C:/lscc/radiant/<version_number>/examples/counter/
myscript2.tcl
5. As long as there are no syntax errors or invalid arguments, the script will
open the project, synthesize, map, and place-and-route the design. Once
the design finishes it closes the project. If there are errors in the script,
you will see the errors in red in the Tcl Console after you attempt to run it.
Go back to your script and correct the errors that prevented the script from
running.

Project Archiving
A Radiant software project archive is a single compressed file (.zip) of your
entire project. The project archive can contain all of the files in your project
directory, or it can be limited to source-related files. When you use the File >
Archive Project command, the dialog box provides the option to “Archive all
files under the Project directory.” When you select this option, the entire
project is archived. When you clear this option, only the project’s source-
related files, including strategies, are archived. Many of these source-related
files must be archived in order to achieve the same bitstream results for a fully
implemented design.

Whichever archiving method you select, if your project contains source files
stored outside the project folder, the remote files will be compressed under
the remote_files subdirectory in the archive; for example:

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<project_name>/remote_files/sources
<project_name>remote_files/strategies

When unarchiving, you must manually move the archived remote files to the
original locations or the project will not work.

File Descriptions
This section provides a list of the file types used in the Radiant software,
including those generated during design implementation. The Archive column
indicates the files that must be archived in order to achieve the same
bitstream results.

Table 46: Source Files

File Type Definition Function Archive?

.fdc FPGA Design Constraint file Used for specifying design constraints for
Synplify-Pro synthesis tool.

.ipk Radiant Software IP Package file. Package file for Radiant software Soft IP.

.ipx Manifest file generated by IP Catalog. Enables changes to be made to a module or IP

Catalog.

.ldc Lattice Design Constraint file Used for specifying timing constraints for LSE
synthesis flow. The .ldc contents will be
combined into design database file .udb.

.pcf Power Calculator project file Stores power analysis results from information
extracted from the design project.

.pdc Post-Synthesis constraint file. Used for specifying post-synthesis constraints

(timing/physical) for Lattice engines such as
MAP and PAR.

.rdf Radiant Software Project file Used for managing and implementing all project
files in the Radiant software.

.rva Reveal Analyzer file Defines the Reveal Analyzer project and
contains data about the display of signals in
Waveform View.

.rvl Reveal Inserter debug file Defines the Reveal project and its modules,
identifies the trace and trigger signals, and
stores the trace and trigger options.

.sdc SDC constraints file Used for specifying design-specific constraints

for Synplify-Pro. SDC is replaced by the FDC
format in but is still supported in the Radiant
software.

.spf Simulation project file, a script file Used for running the simulator for your project
produced by the Simulation Wizard from the Radiant software.

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Table 46: Source Files (Continued)

File Type Definition Function Archive?

.sty Strategy file Defines the optimization control settings of

implementation tools such as logic synthesis,
mapping, and place and route.

.sv SystemVerilog

.v Verilog source file Contains Verilog description of the circuit

structure and function.

.vhd VHDL source file Contains VHDL description of the circuit

structure and function.

.xcf Configuration chain file Used for programming devices in a JTAG daisy
chain.

Table 47: IP Files

File Type Definition Function Archive?

<instName>_bb.v Verilog IP black box file Provides the Verilog synthesis black box
for the IP core and defines the port list.

<instName>.cfg IP parameter configuration file Used for re-creating or modifying the core
in the IP Catalog tool.

<instName>.svg Scalable Vector Graphics file A graphic file used to display module/IP
schematic and ports.

<instName>_tmpl.v Verilog template file A template for instantiating the generated

module. This file can be copied into a
user Verilog file.

<instName>_tmpl.vhd VHDL module template file A template for instantiating the generated
module. This file can be copied into a
user VHDL file.

<instName>.v Verilog module file Verilog netlist generated by IP Catalog to

match the user configuration of the
module.

Table 48: Implementation Files

File Type Definition Function Archive?

.bgn Bitstream generation report file Reports results of a bit generation

(bitgen) run and displays information
on options that were set.

.bin Bitstream file Used for SRAM FPGA programming.

.ibs Post-Route I/O buffer information Used for analyzing signal integrity
specification file (IBIS) and electromagnetic compatibility
(EMC) on printed circuit boards.

.mcs PROM file Used for SRAM FPGA programming.

.mrp Map Report file Provides statistics about component

usage in the mapped design.

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Table 48: Implementation Files (Continued)

File Type Definition Function Archive?

.pad Post-Route PAD report file Lists all programmable I/O cells used
in the design and their associated
primary pins.

.par Post-Route Place & Route report file Summarizes information from all
iterations and shows the steps taken
to achieve a placement and routing
solution.

.sso Post-PAR SSO analysis file Reports the noise caused by

simultaneously switching outputs.

.tw1 Post-Map Timing analysis file Estimates pre-route timing.

.twr Post-PAR Timing analysis file Reports post-route timing.

.vo Post-Route Verilog simulation file Used for post-route simulation.

<Design name>_vo.sdf Post-Route SDF simulation file for Used for timing simulation.
Verilog

.vm Synthesized netlist file Netlist file generated by the Radiant

software Synthesis tools.

.udb Unified Design Database file Compiled from HDL design source. It
may contain both design netlist and
constraints.

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Revision History

The following table gives the revision history for this document.

Date Version Description

11/24/2023 2023.2 Updated to reflect changes in Radiant 2023.2 software.

6/26/2023 2023.1 Updated to reflect changes in Radiant 2023.1 software.

2/9/2023 2022.1.1 Updated to reflect changes in Radiant 2022.1.1 software.

11/21/2022 2022.1 Updated to reflect changes in Radiant 2022.1 software.

6/8/2022 3.2 Updated to reflect changes in Radiant 3.2 software.

3/29/2022 3.1.1 Updated to reflect changes in Radiant 3.1.1 MachXO5-NX

Update Device Update.

3/22/2022 3.1.1 Updated to reflect changes in Radiant 3.1.1 software.

12/7/2021 3.1 Updated to reflect changes in Radiant 3.1 software.

6/14/2021 3.0 Updated screen captures.

Updated Chapter 5, Pre-Synthesis Constraint File.

4/5/2021 3.0 Updated to reflect changes in Radiant 3.0 software.

10/20/2020 2.2 Updated to reflect changes in Radiant 2.2 software,

including replacing the Active-HDL simulator with Mentor
ModelSim.

7/10/2020 2.1.1 Updated to reflect changes in Radiant 2.1.1 software.

5/7/2020 2.1 Updated to reflect changes in Radiant 2.1 software.

11/27/2019 2.0 Updated to reflect changes in Radiant 2.0 software.

Removed Appendix A, Reveal User Guide. Starting with
Radiant software v2.0, this is now a stand-alone user guide.
Removed Appendix B, Programming Tools User Guide.
Starting with Radiant software v2.0, this is now a stand-
alone user guide.

03/25/2019 1.1 Updated to reflect changes in Radiant 1.1 software.

02/08/2018 1.0 Initial release.

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