Design Block Specifications:
Our design comprises 7 basic sections. We describe each one below:
1. Opcode Decoder
2. Arithmetic Block
3. Logical Block
4. Comparator Block
5. Shifter Block
6. Code Conversion Block
7. Result Fetching Block
Opcode Decoder: The proposed design consists of a primary opcode decoder
unit which activates the respective function block on the basis of the instruction
opcode executed by the processor and forwarded to the ALU block. The
respective output lines will feed the enable lines of respective function blocks.
The decoder is a 4:16 unit l.e. It takes 4 bits of opcode as input and in turn
activates the respective function block to perform the desired operation. We can
have macro value usage in the Verilog code for an enhanced readability of the
HDL source code. Using a case Implementation statement, we can select and
activate the respective function block for the required operation. For the
reference consider the following
Arithmetic Block: This block is used to implement arithmetic operations such as
Addition, Subtraction, Multiplication and division. The Accumulator and the
auxiliary B register feed as inputs to this block. The outputs of Sum and Carry
are stored in respective output registers which are then demultiplexed by help
of opcode and displayed on the output
Comparator block: This block consists of combinational circuit HDL code which
performs bit matching and comparisons. Respective outputs may be used to
branch Instructions on the basis of a comparison. Similarly, numerically larger or
smaller Indications on respective operands may be used. In case of equal
comparison match, the accumulator as well as the carry bit is set to zero, and
the respective Zero flag Is set.
In case if the operand in the accumulator is larger, the MSB of the result 8 bit Is
set, and so 80 is resulted on the output. Otherwise, 01.
Logical block: This block comprises basic logic gate units such as AND, OR, NOT,
XOR, etc. Such operations on data operands are served by this block. Outputs
are stored in respective latches. The entire logical block comprises one
dedicated output register. This is so because at any point of time, although
multiple operations may be Issued to the ALU In parallel, simultaneously only
those operations may execute that run on Independent block sections of the
ALU. Thus, on the basis of the Issued operation, the respective output is fetched
from the sectional output register and delivered to the final 8bit result register
on the basis of opcode demultiplexing.
Shifter/Rotate block: This block consists of basic shifters and mechanisms for bit
rotation. Provisions for updates In respective flag bits after each operation may
be provided in future Improved versions. In case of these operations, as they
accept only one 8-bit operand, thus the type of rotation and the type of
shifting/rotation command may be specified explicitly by means of the
b-register bus mapped to the onboard DIP switches. The higher 4 bits of the
b-register bus, l.e. 7:4 bits specify the number by which the bits have to rotate
as per the command in a bitwise fashion. The lower 4 bits of the b register bus
l.e. 3:0 bits specify the particular command which is to be executed for the
respective shifter section.
Code Conversion: This block consists of basic 4 bit-binary code
conversions with flag bit 'Done' Indicator. The LSB [3:0] from the b-register
provides the type of code conversion and the 4-bit value to convert. This
block has the option to select the 8-bit value either from the external
switches or the shift result but only one at a time. The following reference
can be taken for code selection. After enabling the 'Done' signal, the result
is stored in the register and should be popped on a command signal.
Note:
1. All the circuits are active low enabled and the system can go to initial
condition by active low control Input 'init' at any time.
2. Prepare the technical document for every block you develop for future
reference and model design such that it is compatible for bit size
expansion. The technical document has to provide the basic port lists and
usage for block/ module development.
3. Preferably an optimized design is expected for each block developed.
