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PCEC-515 Code

The document contains VHDL code for various digital circuits including half adders, full adders, 4:1 multiplexers, and 3:8 decoders. Each circuit is defined as an entity with specified input and output ports, and the architecture details the logic operations performed. The code is structured for three different entities named Souvik Mandal, Alen Binukumar, and Adutiya Pandey for each circuit type.

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Souvik
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9 views5 pages

PCEC-515 Code

The document contains VHDL code for various digital circuits including half adders, full adders, 4:1 multiplexers, and 3:8 decoders. Each circuit is defined as an entity with specified input and output ports, and the architecture details the logic operations performed. The code is structured for three different entities named Souvik Mandal, Alen Binukumar, and Adutiya Pandey for each circuit type.

Uploaded by

Souvik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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library IEEE; Half Adder

use IEEE.STD_LOGIC_1164.ALL;

entity Souvik_Mandal is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end Souvik_Mandal;

architecture Reg_2343009 of Souvik_Mandal is

begin
s <= a xor b;
c <= a and b;

end Reg_2343009;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Alen_Binukumar is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end Alen_Binukumar;

architecture Reg_2343010 of Alen_Binukumar is

begin
s <= a xor b;
c <= a and b;

end Reg_2343010;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Adutiya_Pandey is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end Adutiya_Pandey;

architecture Reg_2343025 of Adutiya_Pandey is

begin
s <= a xor b;
c <= a and b;

end Reg_2343025;
library IEEE; Full Adder
use IEEE.STD_LOGIC_1164.ALL;

entity Souvik_Mandal is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end Souvik_Mandal;

architecture Reg_2343009 of Souvik_Mandal is

begin
S <= a xor b xor Cin;
Cout <= (a and b)or(Cin and(a xor b));

end Reg_2343009;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Alen_Binukumar is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end Alen_Binukumar;

architecture Reg_2343010 of Alen_Binukumar is

begin
S <= a xor b xor Cin;
Cout <= (a and b)or(Cin and(a xor b));

end Reg_2343010;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Adutiya_Pandey is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end Adutiya_Pandey;

architecture Reg_2343025 of Adutiya_Pandey is

begin
S <= a xor b xor Cin;
Cout <= (a and b)or(Cin and(a xor b));

end Reg_2343025;
4:1 MUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Souvik_Mandal is
Port ( I0,I1,I2,I3,S0,S1 : in STD_LOGIC;
Y : out STD_LOGIC);
end Souvik_Mandal;

architecture Reg_2343009 of Souvik_Mandal is

begin
process(I0,I1,I2,I3,S0,S1)
begin
if (S0 = '0' and S1 = '0')then
Y <= I0;
elsif (S0 = '1' and S1 = '0')then
Y <= I1;
elsif (S0 = '0' and S1 = '1')then
Y <= I2;
else
Y <= I3;
end if;
end process;
end Reg_2343009;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Alen_Binukumar is
Port ( I0,I1,I2,I3,S0,S1 : in STD_LOGIC;
Y : out STD_LOGIC);
end Alen_Binukumar;

architecture Reg_2343010 of Alen_Binukumar is

begin
process(I0,I1,I2,I3,S0,S1)
begin
if (S0 = '0' and S1 = '0')then
Y <= I0;
elsif (S0 = '1' and S1 = '0')then
Y <= I1;
elsif (S0 = '0' and S1 = '1')then
Y <= I2;
else
Y <= I3;
end if;
end process;
end Reg_2343010;
4:1 MUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Adutiya_Pandey is
Port ( I0,I1,I2,I3,S0,S1 : in STD_LOGIC;
Y : out STD_LOGIC);
end Adutiya_Pandey;

architecture Reg_2343025 of Adutiya_Pandey is

begin
process(I0,I1,I2,I3,S0,S1)
begin
if (S0 = '0' and S1 = '0')then
Y <= I0;
elsif (S0 = '1' and S1 = '0')then
Y <= I1;
elsif (S0 = '0' and S1 = '1')then
Y <= I2;
else
Y <= I3;
end if;
end process;
end Reg_2343025;

3:8 Decoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Souvik_Mandal is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
D : out STD_LOGIC_VECTOR (7 downto 0));
end Souvik_Mandal;

architecture Reg_2343009 of Souvik_Mandal is


begin
process(A)
begin
case A is
when "000" => D <= "00000001";
when "001" => D <= "00000010";
when "010" => D <= "00000100";
when "011" => D <= "00001000";
when "100" => D <= "00010000";
when "101" => D <= "00100000";
when "110" => D <= "01000000";
when "111" => D <= "10000000";
when others => D <= "00000000";
end case;
end process;
end Reg_2343009;
3:8 Decoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Alen_Binukumar is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
D : out STD_LOGIC_VECTOR (7 downto 0));
end Alen_Binukumar;

architecture Reg_2343010 of Alen_Binukumar al is


begin
process(A)
begin
case A is
when "000" => D <= "00000001";
when "001" => D <= "00000010";
when "010" => D <= "00000100";
when "011" => D <= "00001000";
when "100" => D <= "00010000";
when "101" => D <= "00100000";
when "110" => D <= "01000000";
when "111" => D <= "10000000";
when others => D <= "00000000";
end case;
end process;
end Reg_2343010;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Adutiya_Pandey is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
D : out STD_LOGIC_VECTOR (7 downto 0));
end Adutiya_Pandey;

architecture Reg_2343025 of Adutiya_Pandey is


begin
process(A)
begin
case A is
when "000" => D <= "00000001";
when "001" => D <= "00000010";
when "010" => D <= "00000100";
when "011" => D <= "00001000";
when "100" => D <= "00010000";
when "101" => D <= "00100000";
when "110" => D <= "01000000";
when "111" => D <= "10000000";
when others => D <= "00000000";
end case;
end process;
end Reg_2343025;

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