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VHDL Ex4

The document defines several VHDL entities including a decoder (DEC), a data latch (BD), a multiplexer (Mux1), and a register (Registre). Each entity has specific input and output ports and uses conditional assignments or processes to determine the output based on the inputs. The architecture of the register integrates the other entities to create a functional component in a digital design.

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9 views2 pages

VHDL Ex4

The document defines several VHDL entities including a decoder (DEC), a data latch (BD), a multiplexer (Mux1), and a register (Registre). Each entity has specific input and output ports and uses conditional assignments or processes to determine the output based on the inputs. The architecture of the register integrates the other entities to create a functional component in a digital design.

Uploaded by

khadijaelaalawi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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LIBRARY IEEE ;

use ieee.std_logic_1164.all;

ENTITY DEC is

PORT(C1: IN bit_vector ( 0 to 1);

T1: OUT bit_vector (0 to 3));

end DEC ;

ARCHITECTURE X of DEC is

BEGIN

with C1 select

T1 <= "0001" when "00" ,

"0010" when "01" ,

"0100" when "10" ,

"1000" when "11" ;

end X ;

LIBRARY IEEE ;

use ieee.std_logic_1164.all;

ENTITY BD is

PORT( D1, T2 : IN bit ;

Q1 : OUT bit );

end BD ;

ARCHITECTURE X1 of BD is

begin

Process (T2)

begin

if T2 = '1' then Q1<= D1 ;

end if ;

end Process;

end X1 ;
LIBRARY IEEE ;

use ieee.std_logic_1164.all;

ENTITY Mux1 is

PORT(Q1: IN bit_vector ( 0 to 2);

C2: IN bit_vector (0 to 1);

E : OUT bit);

end MUX1 ;

ARCHITECTURE Y of Mux1 is

BEGIN

with C2 select

E <= Q1(0) when "00" ,

Q1(1) when "01" ,

Q1(2) when "10" ,

Q1(3) when "11" ;

end Y

LIBRARY IEEE ;

use ieee.std_logic_1164.all;

ENTITY Registre is

port(D:IN std_logic;

C1,C2: IN std_logic_vector (0 to 1);

E: OUT std_logic );

end Registre ;

ARCHITECTURE R of Registre is

Signal T,Q: std_logic_vector (0 to 3);

BEGIN

ENTITY WORK.DEC port map(C1,T1) ;

for i in 0 to 3 generate

ENTITY WORK.BD port MAP(D,T(i),Q(i));

End generate;

ENTITY WORK.Mux1 generic MAP(Q,C2,E);

end R ;

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