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VHDL Ex2

The document defines four VHDL entities: Arith1, Logic1, Mux1, and Y. Arith1 performs various arithmetic operations based on the select signal S1, Logic1 performs logical operations based on S2, and Mux1 selects between two inputs based on S3. The entity Y integrates the other three entities, using their outputs based on the select signals S5 and S6.

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3 views4 pages

VHDL Ex2

The document defines four VHDL entities: Arith1, Logic1, Mux1, and Y. Arith1 performs various arithmetic operations based on the select signal S1, Logic1 performs logical operations based on S2, and Mux1 selects between two inputs based on S3. The entity Y integrates the other three entities, using their outputs based on the select signals S5 and S6.

Uploaded by

khadijaelaalawi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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LIBRARY IEEE ;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

ENTITY Arith1 is

port(a1,b1:in std_logic_vector (0 to 7);

S1:in std_logic_vector(0 to 2);

cin1: IN std_logic ;

y1: OUT std_logic_vector (0 to 7));

end Arith1;

Architecture Arch1 of Arith1 IS

BEGIN

with S1 select

y1<= a1 when "000" ,

a1+'1' when "001" ,

a1-'1' when "010" ,

b1 when "011" ,

b1 +'1' when "100",

b1-'1' when "101",

a1+b1 when "110",

a1+b1+cin1 when "111" ;

end Arch1;

LIBRARY IEEE ;
use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

ENTITY Logic1 is

port(a2,b2:in std_logic_vector (0 to 7);

S2:in std_logic_vector(0 to 2);

y2: OUT std_logic_vector (0 to 7));

end Logic1 ;

Architecture Arch2 of Logic1 IS

BEGIN

with S2 select

y2<= NOT a2 when "000" ,

NOT b2 when "001" ,

a2 AND b2 when "010" ,

a2 OR b2 when "011" ,

a2 NAND b2 when "100",

a2 NOR b2 when "101",

a2 XOR b2 when "110",

a2 XNOR b2 when "111" ;

end Arch2;

LIBRARY IEEE ;

use IEEE.std_logic_1164.all;
LIBRARY IEEE ;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

ENTITY Mux1 is

port(a3,b3:in std_logic_vector (0 to 7);

S3:in std_logic;

y3: OUT std_logic_vector (0 to 7));

end Mux1 ;

Architecture Arch3 of Mux1 IS

BEGIN

with S3 select

y3<= a3 when '0',

b3 when '1';

end Arch3;
LIBRARY IEEE ;

use IEEE.std_logic_1164.all;

ENTITY Y IS

PORT (A,B : in std_logic_vector (0 to 7);

S5: in std_logic_vector (0 to 2 ) ;

cin : in std_logic ;

S6 : in std_logic ;

y: out std_logic_vector (0 to 7));

end Y;

Architecture X of Y is

signal in1,in2 : std_logic_vector (0 to 7);

begin

U0: entity work.Logic1 port map (A,B,S5,in1);

U1: entity work.Arith1 port map (A,B,S5,cin,in2);

U2: entity work.Mux1 port map (in1,in2,S6,y);

end X;

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