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The document describes a VHDL code for a digital circuit entity named 'pract1' that takes a 4-bit input vector 'E' and produces two 7-bit output vectors 's' and 'o'. The architecture includes a process that uses a case statement to define the output values based on the input combinations. Each input corresponds to specific output values for a 7-segment display representation.

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7 views2 pages

Library Ieee

The document describes a VHDL code for a digital circuit entity named 'pract1' that takes a 4-bit input vector 'E' and produces two 7-bit output vectors 's' and 'o'. The architecture includes a process that uses a case statement to define the output values based on the input combinations. Each input corresponds to specific output values for a 7-segment display representation.

Uploaded by

gilbert
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY pract1 IS

PORT

E: IN std_logic_vector (3 downto 0);

s: out std_logic_vector (6 downto 0);

o : out std_logic_vector ( 6 downto 0)

);

END pract1;

ARCHITECTURE ARCHI OF pract1 IS

BEGIN

PROCESS ( E)

BEGIN

CASE E IS

WHEN "0000" => S<= "1000000"; o<="1111111"; --0

WHEN "0001" => S<="1111001"; o<="1111111"; --1

WHEN "0010" => S<= "0100100"; o<="1111111"; --2

WHEN "0011" => S<= "0110000"; o<="1111111"; --3

WHEN "0100" => S<= "0011001"; o<="1111111"; --4

WHEN "0101" => S<= "0010010"; o<="1111111"; --5


WHEN "0110" => S<= "0000010"; o<="1111111"; --6

WHEN "0111" => S<= "1111000"; o<="1111111";

WHEN "1000" => S<= "0000000"; o<="1111111";

WHEN "1001" => S<= "0011000"; o<="1111111";

WHEN "1010" => s<= "1000000"; o<="1111001";

WHEN "1011" => s<= "1111001"; o<="1111001";

WHEN "1100" => s<= "0100100"; o<="1111001";

WHEN "1101" => s<= "0110000"; o<="1111001";

WHEN "1110" => s<= "0011001"; o<="1111001";

WHEN "1111" => s<= "0010010"; o<="1111001";

WHEN OTHERS => S<= "1111111"; o<="1111111";

END CASE;

END PROCESS;

END ARCHI;

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