4 2.2.3 Miscellaneous Features a a x 4 A 16-bit address in an instruction oF a 16-bit a $ehene oe 16-bit address : ccess a memory locaton, although cee lines. This is made possible using teen ia *gmentation that divides the memory. components, Here the ‘Memory is divided into 16 segments of a ‘Capacity of 2% (= 65536 B =, 64 KB) each and is used as: ‘Code, Stack, Data and Extra: ‘Segment. Interrupts Registers Instruction set Data size for ALU 1. Ithas 256 vectored interrupts : There are also on-vectored interrupts in 8086, but they are ‘routed to one of these interrupts, Ithas 14, 16-bit registers. 3. It has a powerful instruction set, that supports ‘MULTIPLY AND DIVIDE operations also. (These operations were not possible in the processors earlier to 8086). £8086 can perform operations on bit, byte (8-bit), word (16-bit) or a string (block of data) types of data, 4 8086 Internal Architecture Before talking about programming, we need to discuss | _ the special features and Internal architecture of Intel 8086. Fig. 23:1 shows the block schematic of the iy structure of Intel 8086 Fig, 2.3.1 : 8086 flag register format ‘As shown in Fig, 2.31, the 8086 CPU Is divided into sections namely: 1. The bus interfacing unit (BIU) 2, The execution unit (EU). Bus Interface Unit (BIU) is mainly responsible & external accesses Le. read or writing from memory ¢ 1/0 devices. Hence it is called the external world interface of th Processor. It works in synchronous with machine cycles. kr-tn subsequent chapter we wil see. machine cytes. Execution Unit (EU) is the main processing section a the processor. It Is responsible for doing al calculations, arithmetic and logical operations. It alse Controls the different operations in the processor. EU takes care of performing operations on the data. UIs called as the execution heart of the processor. Teworks in synchronous with t-states. We withalso-se¢ © scanned with OKEN Scanner© scanned with OKEN ScannerS microprocessor. ‘ t 8259A is the commonly used priority ine controller. It also helps giving interrupt type to the processor for hon-vectored interrupt of 8086 i.e. INTR. 8.2.1 Features of 8259A IC 8259 is a Programmable Interrupt Controller that can work with 8085, 8086 etc. A single 8259 can handle 8 interrupts while a cascaded configuration of 1 master 8259 and 8 slave 8259s can handle upto 64 interrupts. 8259 can handle edge as well as level triggered interrupts. 8259 has a flexible priority structure. In 8259 interrupts can be masked individually. The Vector address of the interrupts is programmable. Status of interrupts (pending, In-service, and masked) can be easily read by the pP. © scanned with OKEN Scanner© scanned with OKEN Scanner086 Instruction 424 n this mode of addressing, operand is in the register, and instruction specifies the particular register as ‘shown in Fig. 4.2.2. ‘The advantage of this addressing mode is that the access is faster. Instruction [Bho [Register adress R Registers eee obersn| Fig. 4.2.2 : Register addressing Registers may be used as source operands, destination ‘operands or both. ‘The registers may be 8/16 bit. egMOV AK, BX This instruction copies the contents of BX register to AX register. 4.2.2 Immediate Operand Addressing Mode In this case the operand is in the instruction itself. It is sald to be immediate addressing mode as the operand is in the immediate next location ‘of the OPCODE. Fig. 4.2.3 shows format of instruction encoded with Fig, 4.2.3 : Instruction encoded with an Immediate operand ‘The operand in this case could be either 8-bit or 16-bit. Let's take one example : eg MOVCL,02H This instruction copies the it the CL register. immediate number 02H In 4.2.3 Memory Addressing Modes for an array element access explain, @._ For the following instruction compute the ‘memory operanid for 8086 : () MOV AX, [BX] (i) MOV AL, [BP + SI] ‘Assume CS : 0100 H, DS : 0200 H, SS : 0400-H, ES : 0030 H, BP : 0010 H, ies BX : 0020 H, SI: 0030 H, SP = 0040 H. Clearly show ‘computations. @, Explain following addressing modes of Intel 6086. Write an instruction for each mode : 2 {a) Direct addressing mode “(b) Relative base indexed. = For memory accesses, the processor needs to generat a 20-bit address. The registers in 8086 are of 16-bit. W have seen in segmentation, that 8086 produces th 20-bit address by special method Le. segment registe multiplied by 10H and adding to it the effectiv address, The effective address can elther be a dire 16-bit address or can have various components |. base register value, index register value and th displacement. Based on the different combinatio there are various addressing modes. Once we get E (effective address), we can calculate PA (physic address) as, PA = Segment :Offset u u -=Segment register EA ‘=Segment register :BASE + INDEX + DISPLACEMENT 5,88 Sl\_{ 8 or 16bit {ts st Be}+{otLapacemen Effective Address : The address effective from starting of the segment is called as the effective address. ‘example, if the effective address is 10, then it indicates the location to be accesses is 10th from the starting o! segment 2 wae © scanned with OKEN Scanner‘e the physical SANG {ase reiter) + (index regitet) = {83} {nh PA = Segment register : EA oe sl (ox (st) e = : {eet {G3} a al © scanned with OKEN Scannerrocessor (MU Instruction 4-5 Fig. 4.2.7 : Based indexed addressing mode Let's see one example, to clear the concept. F MOV [BX + SI], AL This instruction copies the contents of AL register to mee memory location whose effective address is given byBX + SI ie, the physical address = DS *10H + BX + SI. Register Relative Addressing Mode 2 In this addressing mode the effective address is given by a base register or index register along with an 8-bIt | displacement, specified in the instruction. This effective address is added with the segment register * ah 10H to generate the physical address as shown in Fig. 4.2.8, © scanned with OKEN Scanner© scanned with OKEN Scanner© scanned with OKEN Scanner@ Cerner 23. 1C8255 Programmable Peripheral Inter Gg _ 8255 Programmable Peripheral intertace(PPl) Functional Block Diagram ;and explain the block diagram of 8255 Programmable Peripheral Interface(PP) with control word OnE | Power +5 supplies | ——+ Gno | ==> 110 Fig. 9.3.1 : Block diagram of 8255 ‘The architecture of 8255 can be divided into the | - The address bits (A1, AO) are used to select the ports, following parts: or the Control Word Register as are follows : 1. Data Bus Buffer AL AO _| Selection Sample address ~ This is an 8-bit bi-directional buffer used to interface eee eer Dies ae the internal data bus of 8255 with the external (system) data bus. on PortB 81H (ie. 1000 0001) ~The CPU transfers data to and from the 8255 through 10 | Porte fatten 82H (Le, 1000 0010) Zia hasa Witte coutfat Lage 11 _ | Controiword | 83H (Le, 10000011) > Itaccepts address and control signals from the HP. ~The Ports are controlled by their respective Group ‘a Control Registers. ‘The Control signals determine whether itis a read or a ‘rite operation and also select or reset the 8255 chip, © scanned with OKEN Scanner© scanned with OKEN Scanner© scanned with OKEN ScannerBerti. Microprocessor (MU 10-3 sends ‘HOLD’ signal to the microprocessor and transfers next byte of data block. 10.1.1(C) Transparent or Hidden DMA Transfer — The microprocessor executes some states during which it floats the address and data buses. — During these states, the microprocessor is isolated from the system bus. — The DMA controller transfers data between memory and I/O devices during these states. This operation is transparent to microprocessor. - This is the slowest DMA transfer, In this mode, the instruction execution speed of microprocessor is not reduced. But, the transparent DMA requires logic to detect the states when the microprocessor is floating the buses. Now, we will study DMA controller chip 8237. 10.2 Programmable DMA Controller 8257 © scanned with OKEN ScannerNo Operation io. date | First byte of Opcode from queue ot Empty the Queue oe Subsequent byte from queue "25° Memory Banking in s0a6 T “1 P a) WETS — 8086 has a 16-bit data bus hence it should be able to access 16-bit data in one operation. — But the memory chips available are normally such that each location has 8-bits i.e. a byte. © scanned with OKEN Scanner© scanned with OKEN Scanner© scanned with OKEN Scanner© scanned with OKEN Scanner© scanned with OKEN Scanner© scanned with OKEN Scannertol 8086 Archit ¥ or (MU The intel \rchitectury, 4, Finally, sharing of data or passing of data from one program to another Is easily possible due to segmentation ‘so the segmentation makes data relocatable as the program uses only offset register pointers while the segment polns to the base of segment.) Disadvantage of segmentation 1 becomes. complicated for the programmer as multiple registers (segment and pointer registers) to access amemory location, Tea Pin Definitions Table 2.4.1 : Signal Description of 8086 Name ofthe pins GND, ND CLK, RESET, READY Supply pins (3 pins) I. | Clock related pins @pins) Ml. | Address and Data | AD) - AD,s, »ins (21 pins) —_— ee Aue/Ss~ Aio/Se BHE / Sy NMI, INTR Interrupt pins (2 pins) — V._ | other control (3 pins) | = san / ink, RD vi | Mode multiplexed signals (8 pins) (MIN mode - MAX mode signals) HOLD- RQ) / GT, HLDA-RQ /GT;, WR - LOCK 9 DT /R ~S; DEN M/I0 ~S;, ALE- QS) INTA - QS; |. Supply pins (3 pins) - Used for power supply Le, +5V on Voc w.rt: GND. ~ Two separate GND pins for two layers of 8086 chip, improves the noise rejection, Il. Clock related pins (3 pins) (©) Functional pin diagram Fig. 2.4.4 CLK ~ This pin provides the basic timing for the processor. ~ 8086 does not has an on-chip clock generator hence an external clock generator like 8284 is used to provide the clock signal, ~~ Itis asymmetric with 33% duty cycle, TTL clock signal. Wy hotest © scanned with OKEN Scanner© scanned with OKEN Scanner© scanned with OKEN Scanner3. T (Transmit) Pin namos configuration ees Cy f \ s as N a x ” 7 (C) intemal circult diagram of 8286 Fig. 3.4.1 Description 1 Mn my . - ‘These ©'lnes are called as the local bus data nes, They can act as Input lines or as output lines depending onthe ‘status of the transmit (T) pin, ~ MT =4,then Ae Ay actas inputs, whereas i =O, then Ay A, will act as output lines. 2 B,-B, These G-lines are called as system bus data line, They too can act as input or output lines depending on the status of the transmit (T) pin. MT = 1 then By B, will act as output ines whereas with T = 0, they will actas the inputllines, Pin 11 Le. T or transmit pin Is an Input pin of 8286,a (Mu) operating Modes : Minimum and Maximum Modo Teeontrols the direction ofthe transceivers, as follows: fT #1; Ao~Aractas inputs and By ~ B, actas outputs. o UT #0; Ao~Aractas outputs with By ~ B, acting as inputs. ‘output Enable (OE ) ‘his isan active low Input to 8286, I is used for enabling the appropriate diver to put his data onto the respective bus. [FOE = 1 Le. in active, then the outputs will be in the high impedance (tri-state) T-state, 3.4.1 Features of 8286 — Available in the 20 pin package. _ Tristate (high impedance) outputs. — Contains fully parallel 8 bit transceivers (transmitters and receivers). = Capable of driving system data bus. — Used as data bus buffers for 8085, 8086 and 8088 based systems. Interfacing with 8086 The interfacing of the 8286 with 8086 is shown in Fig. 3.4.2. = The multiplexed address data bus AD to ADss is applied at the A inputs (Ao (ADs - ADrto first and ADs - ADssto the second), = The B outputs of the two 8286 chips actas the demultiplexed data bus. ‘The 8286 transceivers allow bi-directional data transfer. The T (transmit) input of both 8286 chi to A:) of the two 6286 ICs ips is connected to the DT/R_ output of 8086. = Sowhen DT/ R= 0, = 0,0 lines act as input lines, alines act as the ‘output lines and the data will flow from memory or ports to 8086, that means the read operation will take place. = Onthe otherhandifDT /R 4, then T= 1 and the data will get transferred from the processor to the memory or Ports. the 8286 chips are connected to the DEN output of 8086. Ths signal is used to enable or disable — The OE lines of both the transceivers. With DEN = the transceivers are enabled and with DEN = 1 they are disabled and go into tri-state Fig. 9.4.2 ; Intertacing of tranecelver 8286 with 8086 wren