07/01/2024

JK flip flop
A JK FF is a refinement of the RS FF in that the indeterminate state of the RS FF is defined in JK FF. The
input mark J is for set S and the input mark K is for reset R. when both J & K are 1, The JK FF switches
to its compliment state, that is if Q=1 it switches to Q=0 and vice versa. There are three operations
that can be performed with a flip-flop: Set it to 1, reset it to 0, or complement its output.

Q(t) J K Q (t+1)
0 0 0 0 N.C

0 0 1 0 Reset

0 1 0 1 Set
0 1 1 1 Toggle
1 0 0 1 N.C
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 0 Toggle

Q(t)=Present State before giving CP

Q(t+1)=Next State after giving CP
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JK flip flop

JK flip flop with preset and clear input

JK PR CL Q (t+1)
1 0 0 N.Use

1 0 1 Set

1 1 0 Clear

1 1 1 Normal
Preset and clear input are not depend on CP
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T flip flop
The T FF is single input variant of the JK FF. the designation T comes from the ability of the FF to
toggle or compliment its output when CP occurs while input T=1.
The T (toggle) flip-flop is a complementing flip-flop and can be obtained from a JK
flip-flop when inputs J and K are tied together. This is shown in Fig.. When
T = 0 (J = K = 0), a clock edge does not change the output. When T = 1 (J = K = 1), a clock edge
complements the output. The complementing flip-flop is useful for designing binary counters.
Q(t) T Q (t+1)
0 0 0 N.C

0 1 1 Toggle

1 0 1 N.C

1 1 0 Toggle

Racing problem of J-K FF

If clock pulse duration is long and if the input J=K=1 then the output of the JK FF may toggle
more than once , it is called racing problem.
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Master Slave JK Flip Flop

Race Around Condition In JK Flip-flop

For J-K flip-flop, if J=K=1, and if clock=1 for a long period of time, then Q output will toggle as long as CLK is
high, making the flip-flop output unstable or uncertain.
• This problem is called race around condition in J-K flip-flop. This problem (Race Around Condition) can be
avoided by ensuring that the clock input is at logic “1” only for a very short time. This introduced the concept
of Master Slave JK flip flop.

Master Slave JK flip flop

The Master-Slave Flip-Flop is a combination of two JK flip-flops connected in a series configuration. One acts as
the “master” and the other as a “slave”.
•The output from the master flip flop is connected to the two inputs of the slave flip flop whose output is fed
back to inputs of the master flip flop.
•In addition to these two flip-flops, the circuit also includes an inverter. The inverter is connected to clock pulse
in such a way that the inverted clock pulse is given to the slave flip-flop.

Master Slave JK Flip Flop

Working of a master slave flip flop

• When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the system.
• The slave flip-flop is isolated until the CP goes to 0.
• When the CP goes back to 0, information is passed from the master flip-flop to the slave and output is
obtained.
• Firstly the master flip flop is positive level triggered and the slave flip flop is negative level triggered, so
the master responds before the slave.
• If J=0 and K=1, the high Q′ output of the master goes to the K input of the slave and the clock forces the slave
to reset, thus the slave copies the master.
• If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the Negative transition of
the clock sets the slave, copying the master.
• If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on the negative
transition of the clock.
• If J=0 and K=0, the flip flop is disabled and Q remains unchanged.
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To overcome Racing problem of J-K FF

JK master slave FF

Q=0 and Q′ =1
SET J=1 K=0
CP=1 CP=0
Gate Output Output
1 0 NC
2 1 NC
3 1 NC
4 0 NC
CP Active 5 NC 0

0 Slave 6 NC 1
7 NC 1
1 Master 8 NC 0

To overcome Racing problem of J-K FF

JK master slave FF

Q=1 and Q′ =0
RESET J=0 K=1
CP=1 CP=0
Gate Output Output
1 1 NC
2 0 NC
3 0 NC
4 1 NC
CP Active 5 NC 1

0 Slave 6 NC 0
7 NC 0
1 Master 8 NC 1
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To overcome Racing problem of J-K FF

JK master slave FF

Q=1 and Q′ =0
TOGGLE J=1 K=1
CP=1 CP=0
Gate Output Output
1 1 NC
2 0 NC
3 0 NC
4 1 NC
CP Active 5 NC 1

0 Slave 6 NC 0
7 NC 0
1 Master 8 NC 1

To overcome Racing problem of J-K FF

JK master slave FF

Q=0 and Q′ =1
TOGGLE J=1 K=1
CP=1 CP=0
Gate Output Output
1 0 NC
2 1 NC
3 1 NC
4 0 NC
CP Active 5 NC 0

0 Slave 6 NC 1
7 NC 1
1 Master 8 NC 0
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FF characteristics table
JK FF SR FF
J K Q (t+1) S R Q (t+1)
0 0 Q(t) N.C 0 0 Q(t) N.C

0 1 0 Reset 0 1 0 Reset

1 0 1 Set 1 0 1 Set

1 1 Q′(t) Toggle 1 1 X Indeterminate

D FF T FF
D Q (t+1) T Q (t+1)
0 0 Reset 0 Q(t) NC

1 1 Set 1 Q′(t) Complement