Flip-Flops

A flip flop is an electronic circuit with two stable states that can be used to
store binary data.
A circuit that has two stable states is treated as a flip flop. These stable states are used to store binary
data that can be changed by applying varying inputs. The flip flops are the fundamental building blocks
of the digital system. Flip flops and latches are examples of data storage elements. In the sequential
logical circuit, the flip flop is the basic storage element. The latches and flip flops are the basic storage
elements but different in working. There are the following types of flip flops:

 SR Flip-Flop
 D Flip-Flop
 JK Flip-Flop
 T Flip-Flop

SR Flip-Flop
SR flip-flop operates with only positive clock transitions or negative clock transitions. Whereas,
SR latch operates with enable signal. The circuit diagram of SR flip-flop is shown in the
following figure.

This circuit has two inputs S & R and two outputs Q t & Qt’. The operation of SR flip-flop is
similar to SR Latch. But, this flip-flop affects the outputs only when positive transition of the
clock signal is applied instead of active enable.

Truth Table:
S R Q(t) Q(t)' STATE
0 0 0 1 NO CHANGE STATE
0 1 0 1 SET
1 0 1 0 RESET
1 1 --- --- INVALID

J-K Flip-flop
The JK flip flop is used to remove the drawback of the S-R flip flop, i.e., undefined states. The JK
flip flop is formed by doing modification in the SR flip flop. The S-R flip flop is improved in order
to construct the J-K flip flop. When S and R input is set to true, the SR flip flop gives an
inaccurate result. But in the case of JK flip flop, it gives the correct output.

Truth Table:
S R Q(t+1) STATE
0 0 Q(t) PREVIOUS STATE
(NO CHANGE STATE)
0 1 0 RESET
1 0 1 SET
1 1 Q(t)' COMPLEMENT(TOGGL
E STATE)

D Flip Flop
D flip-flop operates with only positive clock transitions or negative clock transitions. Whereas,
D latch operates with enable signal. That means, the output of D flip-flop is insensitive to the
changes in the input, D except for active transition of the clock signal. The circuit diagram of D
flip-flop is shown in the following figure The D flip flop is mostly used in shift-registers,
counters, and input synchronization.

Truth Table:
 T Flip-Flop
Just like JK flip-flop, T flip flop is used. Unlike JK flip flop, in T flip flop, there is only single input with the
clock input. The T flip flop is constructed by connecting both of the inputs of JK flip flop together as a
single input.

The T flip flop is also known as Toggle flip-flop. These T flip-flops are able to find the complement of its
state.

Truth Table:

Master-Slave JK Flip Flop

Explanation
The master-slave flip flop is constructed by combining two JK flip flops
  These flip flops are connected in a series configuration. In these two flip flops, the 1st flip flop
work as "master", called the master flip flop, and the 2nd work as a "slave", called slave flip flop.
The master-slave flip flop is designed in such a way that the output of the "master" flip flop is
passed to both the inputs of the "slave" flip flop
 The output of the "slave" flip flop is passed to inputs of the master flip flop.

In "master-slave flip flop", apart from these two flip flops, an inverter or NOT gate

is also used. For passing the inverted clock pulse to the "slave" flip flop, the inverter is connected to the
clock's pulse. In simple words, when CP set to false for "master", then CP is set to true for "slave", and
when CP set to true for "master", then CP is set to false for "slave".

Working:
o When the clock pulse is true, the slave flip flop will be in the isolated state, and the system's
state may be affected by the J and K inputs. The "slave" remains isolated until the CP is 1. When
the CP set to 0, the master flip-flop passes the information to the slave flip flop to obtain the
output.
o The master flip flop responds first from the slave because the master flip flop is the positive level
trigger, and the slave flip flop is the negative level trigger.
o The output Q'=1 of the master flip flop is passed to the slave flip flop as an input K when the
input J set to 0 and K set to 1. The clock forces the slave flip flop to work as reset, and then the
slave copies the master flip flop.
o When J=1, and K=0, the output Q=1 is passed to the J input of the slave. The clock's negative
transition sets the slave and copies the master.
o The master flip flop toggles on the clock's positive transition when the inputs J and K set to 1. At
that time, the slave flip flop toggles on the clock's negative transition.
o The flip flop will be disabled, and Q remains unchanged when both the inputs of the JK flip flop
set to 0.
Timing Diagram of a Master Flip Flop:

o When the clock pulse set to 1, the output of the master flip flop will be one until the clock input
remains 0.
o When the clock pulse becomes high again, then the master's output is 0, which will be set to 1
when the clock becomes one again.
o The master flip flop is operational when the clock pulse is 1. The slave's output remains 0 until
the clock is not set to 0 because the slave flip flop is not operational.
o The slave flip flop is operational when the clock pulse is 0. The output of the master remains one
until the clock is not set to 0 again.
o Toggling occurs during the entire process because the output changes once in the cycle.